[linux-2.6-block.git] / arch / powerpc / include / asm / book3s / 64 / hash-4k.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_POWERPC_BOOK3S_64_HASH_4K_H
#define _ASM_POWERPC_BOOK3S_64_HASH_4K_H
/*
 * Entries per page directory level.  The PTE level must use a 64b record
 * for each page table entry.  The PMD and PGD level use a 32b record for
 * each entry by assuming that each entry is page aligned.
 */
#define H_PTE_INDEX_SIZE  9
#define H_PMD_INDEX_SIZE  7
#define H_PUD_INDEX_SIZE  9
#define H_PGD_INDEX_SIZE  9

/*
 * Each context is 512TB. But on 4k we restrict our max TASK size to 64TB
 * Hence also limit max EA bits to 64TB.
 */
#define MAX_EA_BITS_PER_CONTEXT		46

#ifndef __ASSEMBLY__
#define H_PTE_TABLE_SIZE	(sizeof(pte_t) << H_PTE_INDEX_SIZE)
#define H_PMD_TABLE_SIZE	(sizeof(pmd_t) << H_PMD_INDEX_SIZE)
#define H_PUD_TABLE_SIZE	(sizeof(pud_t) << H_PUD_INDEX_SIZE)
#define H_PGD_TABLE_SIZE	(sizeof(pgd_t) << H_PGD_INDEX_SIZE)

#define H_PAGE_F_GIX_SHIFT	53
#define H_PAGE_F_SECOND	_RPAGE_RPN44	/* HPTE is in 2ndary HPTEG */
#define H_PAGE_F_GIX	(_RPAGE_RPN43 | _RPAGE_RPN42 | _RPAGE_RPN41)
#define H_PAGE_BUSY	_RPAGE_RSV1     /* software: PTE & hash are busy */
#define H_PAGE_HASHPTE	_RPAGE_RSV2     /* software: PTE & hash are busy */

/* PTE flags to conserve for HPTE identification */
#define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_HASHPTE | \
			 H_PAGE_F_SECOND | H_PAGE_F_GIX)
/*
 * Not supported by 4k linux page size
 */
#define H_PAGE_4K_PFN	0x0
#define H_PAGE_THP_HUGE 0x0
#define H_PAGE_COMBO	0x0

/* 8 bytes per each pte entry */
#define H_PTE_FRAG_SIZE_SHIFT  (H_PTE_INDEX_SIZE + 3)
#define H_PTE_FRAG_NR	(PAGE_SIZE >> H_PTE_FRAG_SIZE_SHIFT)

/* memory key bits, only 8 keys supported */
#define H_PTE_PKEY_BIT0	0
#define H_PTE_PKEY_BIT1	0
#define H_PTE_PKEY_BIT2	_RPAGE_RSV3
#define H_PTE_PKEY_BIT3	_RPAGE_RSV4
#define H_PTE_PKEY_BIT4	_RPAGE_RSV5

/*
 * On all 4K setups, remap_4k_pfn() equates to remap_pfn_range()
 */
#define remap_4k_pfn(vma, addr, pfn, prot)	\
	remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))

#ifdef CONFIG_HUGETLB_PAGE
static inline int hash__hugepd_ok(hugepd_t hpd)
{
	unsigned long hpdval = hpd_val(hpd);
	/*
	 * if it is not a pte and have hugepd shift mask
	 * set, then it is a hugepd directory pointer
	 */
	if (!(hpdval & _PAGE_PTE) &&
	    ((hpdval & HUGEPD_SHIFT_MASK) != 0))
		return true;
	return false;
}
#endif

/*
 * 4K PTE format is different from 64K PTE format. Saving the hash_slot is just
 * a matter of returning the PTE bits that need to be modified. On 64K PTE,
 * things are a little more involved and hence needs many more parameters to
 * accomplish the same. However we want to abstract this out from the caller by
 * keeping the prototype consistent across the two formats.
 */
static inline unsigned long pte_set_hidx(pte_t *ptep, real_pte_t rpte,
					 unsigned int subpg_index, unsigned long hidx,
					 int offset)
{
	return (hidx << H_PAGE_F_GIX_SHIFT) &
		(H_PAGE_F_SECOND | H_PAGE_F_GIX);
}

#ifdef CONFIG_TRANSPARENT_HUGEPAGE

static inline char *get_hpte_slot_array(pmd_t *pmdp)
{
	BUG();
	return NULL;
}

static inline unsigned int hpte_valid(unsigned char *hpte_slot_array, int index)
{
	BUG();
	return 0;
}

static inline unsigned int hpte_hash_index(unsigned char *hpte_slot_array,
					   int index)
{
	BUG();
	return 0;
}

static inline void mark_hpte_slot_valid(unsigned char *hpte_slot_array,
					unsigned int index, unsigned int hidx)
{
	BUG();
}

static inline int hash__pmd_trans_huge(pmd_t pmd)
{
	return 0;
}

static inline int hash__pmd_same(pmd_t pmd_a, pmd_t pmd_b)
{
	BUG();
	return 0;
}

static inline pmd_t hash__pmd_mkhuge(pmd_t pmd)
{
	BUG();
	return pmd;
}

extern unsigned long hash__pmd_hugepage_update(struct mm_struct *mm,
					   unsigned long addr, pmd_t *pmdp,
					   unsigned long clr, unsigned long set);
extern pmd_t hash__pmdp_collapse_flush(struct vm_area_struct *vma,
				   unsigned long address, pmd_t *pmdp);
extern void hash__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
					 pgtable_t pgtable);
extern pgtable_t hash__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
extern pmd_t hash__pmdp_huge_get_and_clear(struct mm_struct *mm,
				       unsigned long addr, pmd_t *pmdp);
extern int hash__has_transparent_hugepage(void);
#endif

#endif /* !__ASSEMBLY__ */

#endif /* _ASM_POWERPC_BOOK3S_64_HASH_4K_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
ab537dca AK	2	#ifndef _ASM_POWERPC_BOOK3S_64_HASH_4K_H
	3	#define _ASM_POWERPC_BOOK3S_64_HASH_4K_H
	4	/*
	5	* Entries per page directory level. The PTE level must use a 64b record
	6	* for each page table entry. The PMD and PGD level use a 32b record for
	7	* each entry by assuming that each entry is page aligned.
	8	*/
dd1842a2 AK	9	#define H_PTE_INDEX_SIZE 9
	10	#define H_PMD_INDEX_SIZE 7
	11	#define H_PUD_INDEX_SIZE 9
92d9dfda	12	#define H_PGD_INDEX_SIZE 9
ab537dca	13
f384796c AK	14	/*
	15	* Each context is 512TB. But on 4k we restrict our max TASK size to 64TB
	16	* Hence also limit max EA bits to 64TB.
	17	*/
	18	#define MAX_EA_BITS_PER_CONTEXT 46
	19
ab537dca	20	#ifndef __ASSEMBLY__
dd1842a2 AK	21	#define H_PTE_TABLE_SIZE (sizeof(pte_t) << H_PTE_INDEX_SIZE)
	22	#define H_PMD_TABLE_SIZE (sizeof(pmd_t) << H_PMD_INDEX_SIZE)
	23	#define H_PUD_TABLE_SIZE (sizeof(pud_t) << H_PUD_INDEX_SIZE)
	24	#define H_PGD_TABLE_SIZE (sizeof(pgd_t) << H_PGD_INDEX_SIZE)
ab537dca	25
273b4936 RP	26	#define H_PAGE_F_GIX_SHIFT 53
	27	#define H_PAGE_F_SECOND _RPAGE_RPN44 /* HPTE is in 2ndary HPTEG */
	28	#define H_PAGE_F_GIX (_RPAGE_RPN43 \| _RPAGE_RPN42 \| _RPAGE_RPN41)
9d2edb18	29	#define H_PAGE_BUSY _RPAGE_RSV1 /* software: PTE & hash are busy */
273b4936	30	#define H_PAGE_HASHPTE _RPAGE_RSV2 /* software: PTE & hash are busy */
9d2edb18	31
c605782b	32	/* PTE flags to conserve for HPTE identification */
945537df AK	33	#define _PAGE_HPTEFLAGS (H_PAGE_BUSY \| H_PAGE_HASHPTE \| \
	34	H_PAGE_F_SECOND \| H_PAGE_F_GIX)
	35	/*
	36	* Not supported by 4k linux page size
	37	*/
	38	#define H_PAGE_4K_PFN 0x0
	39	#define H_PAGE_THP_HUGE 0x0
	40	#define H_PAGE_COMBO 0x0
1c7ec8a4 AK	41
	42	/* 8 bytes per each pte entry */
	43	#define H_PTE_FRAG_SIZE_SHIFT (H_PTE_INDEX_SIZE + 3)
	44	#define H_PTE_FRAG_NR (PAGE_SIZE >> H_PTE_FRAG_SIZE_SHIFT)
1a2f7789 AK	45
	46	/* memory key bits, only 8 keys supported */
	47	#define H_PTE_PKEY_BIT0 0
	48	#define H_PTE_PKEY_BIT1 0
	49	#define H_PTE_PKEY_BIT2 _RPAGE_RSV3
	50	#define H_PTE_PKEY_BIT3 _RPAGE_RSV4
	51	#define H_PTE_PKEY_BIT4 _RPAGE_RSV5
	52
ab537dca	53	/*
368ced78	54	* On all 4K setups, remap_4k_pfn() equates to remap_pfn_range()
ab537dca	55	*/
ab537dca AK	56	#define remap_4k_pfn(vma, addr, pfn, prot) \
	57	remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
	58
26a344ae	59	#ifdef CONFIG_HUGETLB_PAGE
c0a6c719	60	static inline int hash__hugepd_ok(hugepd_t hpd)
26a344ae	61	{
20717e1f	62	unsigned long hpdval = hpd_val(hpd);
26a344ae	63	/*
6a119eae AK	64	* if it is not a pte and have hugepd shift mask
6a119eae AK	65	* set, then it is a hugepd directory pointer
26a344ae	66	*/
20717e1f AK	67	if (!(hpdval & _PAGE_PTE) &&
20717e1f AK	68	((hpdval & HUGEPD_SHIFT_MASK) != 0))
6a119eae AK	69	return true;
6a119eae AK	70	return false;
26a344ae	71	}
26a344ae AK	72	#endif
26a344ae AK	73
59aa31fd RP	74	/*
	75	* 4K PTE format is different from 64K PTE format. Saving the hash_slot is just
	76	* a matter of returning the PTE bits that need to be modified. On 64K PTE,
	77	* things are a little more involved and hence needs many more parameters to
	78	* accomplish the same. However we want to abstract this out from the caller by
	79	* keeping the prototype consistent across the two formats.
	80	*/
	81	static inline unsigned long pte_set_hidx(pte_t *ptep, real_pte_t rpte,
ff31e105 AK	82	unsigned int subpg_index, unsigned long hidx,
ff31e105 AK	83	int offset)
59aa31fd RP	84	{
	85	return (hidx << H_PAGE_F_GIX_SHIFT) &
	86	(H_PAGE_F_SECOND \| H_PAGE_F_GIX);
	87	}
	88
ab624762 AK	89	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
	90
	91	static inline char get_hpte_slot_array(pmd_t pmdp)
	92	{
	93	BUG();
	94	return NULL;
	95	}
	96
	97	static inline unsigned int hpte_valid(unsigned char *hpte_slot_array, int index)
	98	{
	99	BUG();
	100	return 0;
	101	}
	102
	103	static inline unsigned int hpte_hash_index(unsigned char *hpte_slot_array,
	104	int index)
	105	{
	106	BUG();
	107	return 0;
	108	}
	109
	110	static inline void mark_hpte_slot_valid(unsigned char *hpte_slot_array,
	111	unsigned int index, unsigned int hidx)
	112	{
	113	BUG();
	114	}
	115
	116	static inline int hash__pmd_trans_huge(pmd_t pmd)
	117	{
	118	return 0;
	119	}
	120
	121	static inline int hash__pmd_same(pmd_t pmd_a, pmd_t pmd_b)
	122	{
	123	BUG();
	124	return 0;
	125	}
	126
	127	static inline pmd_t hash__pmd_mkhuge(pmd_t pmd)
	128	{
	129	BUG();
	130	return pmd;
	131	}
	132
	133	extern unsigned long hash__pmd_hugepage_update(struct mm_struct *mm,
	134	unsigned long addr, pmd_t *pmdp,
	135	unsigned long clr, unsigned long set);
	136	extern pmd_t hash__pmdp_collapse_flush(struct vm_area_struct *vma,
	137	unsigned long address, pmd_t *pmdp);
	138	extern void hash__pgtable_trans_huge_deposit(struct mm_struct mm, pmd_t pmdp,
	139	pgtable_t pgtable);
	140	extern pgtable_t hash__pgtable_trans_huge_withdraw(struct mm_struct mm, pmd_t pmdp);
ab624762 AK	141	extern pmd_t hash__pmdp_huge_get_and_clear(struct mm_struct *mm,
	142	unsigned long addr, pmd_t *pmdp);
	143	extern int hash__has_transparent_hugepage(void);
	144	#endif
	145
ab537dca AK	146	#endif /* !__ASSEMBLY__ */
	147
	148	#endif /* _ASM_POWERPC_BOOK3S_64_HASH_4K_H */