[linux-2.6-block.git] / arch / powerpc / boot / dts / haleakala.dts

/*
 * Device Tree Source for AMCC Haleakala (405EXr)
 *
 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without
 * any warranty of any kind, whether express or implied.
 */

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "amcc,haleakala";
	compatible = "amcc,kilauea";
	dcr-parent = <&/cpus/cpu@0>;

	aliases {
		ethernet0 = &EMAC0;
		serial0 = &UART0;
		serial1 = &UART1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			model = "PowerPC,405EXr";
			reg = <0>;
			clock-frequency = <0>; /* Filled in by U-Boot */
			timebase-frequency = <0>; /* Filled in by U-Boot */
			i-cache-line-size = <20>;
			d-cache-line-size = <20>;
			i-cache-size = <4000>; /* 16 kB */
			d-cache-size = <4000>; /* 16 kB */
			dcr-controller;
			dcr-access-method = "native";
		};
	};

	memory {
		device_type = "memory";
		reg = <0 0>; /* Filled in by U-Boot */
	};

	UIC0: interrupt-controller {
		compatible = "ibm,uic-405exr", "ibm,uic";
		interrupt-controller;
		cell-index = <0>;
		dcr-reg = <0c0 009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
	};

	UIC1: interrupt-controller1 {
		compatible = "ibm,uic-405exr","ibm,uic";
		interrupt-controller;
		cell-index = <1>;
		dcr-reg = <0d0 009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
		interrupts = <1e 4 1f 4>; /* cascade */
		interrupt-parent = <&UIC0>;
	};

	UIC2: interrupt-controller2 {
		compatible = "ibm,uic-405exr","ibm,uic";
		interrupt-controller;
		cell-index = <2>;
		dcr-reg = <0e0 009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
		interrupts = <1c 4 1d 4>; /* cascade */
		interrupt-parent = <&UIC0>;
	};

	plb {
		compatible = "ibm,plb-405exr", "ibm,plb4";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		clock-frequency = <0>; /* Filled in by U-Boot */

		SDRAM0: memory-controller {
			compatible = "ibm,sdram-405exr";
			dcr-reg = <010 2>;
		};

		MAL0: mcmal {
			compatible = "ibm,mcmal-405exr", "ibm,mcmal2";
			dcr-reg = <180 62>;
			num-tx-chans = <2>;
			num-rx-chans = <2>;
			interrupt-parent = <&MAL0>;
			interrupts = <0 1 2 3 4>;
			#interrupt-cells = <1>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
					/*RXEOB*/ 1 &UIC0 b 4
					/*SERR*/  2 &UIC1 0 4
					/*TXDE*/  3 &UIC1 1 4
					/*RXDE*/  4 &UIC1 2 4>;
			interrupt-map-mask = <ffffffff>;
		};

		POB0: opb {
			compatible = "ibm,opb-405exr", "ibm,opb";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <80000000 80000000 10000000
				  ef600000 ef600000 a00000
				  f0000000 f0000000 10000000>;
			dcr-reg = <0a0 5>;
			clock-frequency = <0>; /* Filled in by U-Boot */

			EBC0: ebc {
				compatible = "ibm,ebc-405exr", "ibm,ebc";
				dcr-reg = <012 2>;
				#address-cells = <2>;
				#size-cells = <1>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				/* ranges property is supplied by U-Boot */
				interrupts = <5 1>;
				interrupt-parent = <&UIC1>;

				nor_flash@0,0 {
					compatible = "amd,s29gl512n", "cfi-flash";
					bank-width = <2>;
					reg = <0 000000 4000000>;
					#address-cells = <1>;
					#size-cells = <1>;
					partition@0 {
						label = "kernel";
						reg = <0 200000>;
					};
					partition@200000 {
						label = "root";
						reg = <200000 200000>;
					};
					partition@400000 {
						label = "user";
						reg = <400000 3b60000>;
					};
					partition@3f60000 {
						label = "env";
						reg = <3f60000 40000>;
					};
					partition@3fa0000 {
						label = "u-boot";
						reg = <3fa0000 60000>;
					};
				};
			};

			UART0: serial@ef600200 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <ef600200 8>;
				virtual-reg = <ef600200>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				current-speed = <0>;
				interrupt-parent = <&UIC0>;
				interrupts = <1a 4>;
			};

			UART1: serial@ef600300 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <ef600300 8>;
				virtual-reg = <ef600300>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				current-speed = <0>;
				interrupt-parent = <&UIC0>;
				interrupts = <1 4>;
			};

			IIC0: i2c@ef600400 {
				compatible = "ibm,iic-405exr", "ibm,iic";
				reg = <ef600400 14>;
				interrupt-parent = <&UIC0>;
				interrupts = <2 4>;
			};

			IIC1: i2c@ef600500 {
				compatible = "ibm,iic-405exr", "ibm,iic";
				reg = <ef600500 14>;
				interrupt-parent = <&UIC0>;
				interrupts = <7 4>;
			};


			RGMII0: emac-rgmii@ef600b00 {
				compatible = "ibm,rgmii-405exr", "ibm,rgmii";
				reg = <ef600b00 104>;
				has-mdio;
			};

			EMAC0: ethernet@ef600900 {
				linux,network-index = <0>;
				device_type = "network";
				compatible = "ibm,emac-405exr", "ibm,emac4";
				interrupt-parent = <&EMAC0>;
				interrupts = <0 1>;
				#interrupt-cells = <1>;
				#address-cells = <0>;
				#size-cells = <0>;
				interrupt-map = </*Status*/ 0 &UIC0 18 4
						/*Wake*/  1 &UIC1 1d 4>;
				reg = <ef600900 70>;
				local-mac-address = [000000000000]; /* Filled in by U-Boot */
				mal-device = <&MAL0>;
				mal-tx-channel = <0>;
				mal-rx-channel = <0>;
				cell-index = <0>;
				max-frame-size = <5dc>;
				rx-fifo-size = <1000>;
				tx-fifo-size = <800>;
				phy-mode = "rgmii";
				phy-map = <00000000>;
				rgmii-device = <&RGMII0>;
				rgmii-channel = <0>;
				has-inverted-stacr-oc;
				has-new-stacr-staopc;
			};
		};

		PCIE0: pciex@0a0000000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
			primary;
			port = <0>; /* port number */
			reg = <a0000000 20000000	/* Config space access */
			       ef000000 00001000>;	/* Registers */
			dcr-reg = <040 020>;
			sdr-base = <400>;

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <02000000 0 80000000 90000000 0 08000000
				  01000000 0 00000000 e0000000 0 00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <42000000 0 0 0 0 80000000>;

			/* This drives busses 0x00 to 0x3f */
			bus-range = <00 3f>;

			/* Legacy interrupts (note the weird polarity, the bridge seems
			 * to invert PCIe legacy interrupts).
			 * We are de-swizzling here because the numbers are actually for
			 * port of the root complex virtual P2P bridge. But I want
			 * to avoid putting a node for it in the tree, so the numbers
			 * below are basically de-swizzled numbers.
			 * The real slot is on idsel 0, so the swizzling is 1:1
			 */
			interrupt-map-mask = <0000 0 0 7>;
			interrupt-map = <
				0000 0 0 1 &UIC2 0 4 /* swizzled int A */
				0000 0 0 2 &UIC2 1 4 /* swizzled int B */
				0000 0 0 3 &UIC2 2 4 /* swizzled int C */
				0000 0 0 4 &UIC2 3 4 /* swizzled int D */>;
		};
	};
};
Commit	Line	Data
a4095516 SR	1	/*
	2	* Device Tree Source for AMCC Haleakala (405EXr)
	3	*
	4	* Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without
	8	* any warranty of any kind, whether express or implied.
	9	*/
	10
	11	/ {
	12	#address-cells = <1>;
	13	#size-cells = <1>;
	14	model = "amcc,haleakala";
	15	compatible = "amcc,kilauea";
	16	dcr-parent = <&/cpus/cpu@0>;
	17
	18	aliases {
	19	ethernet0 = &EMAC0;
	20	serial0 = &UART0;
	21	serial1 = &UART1;
	22	};
	23
	24	cpus {
	25	#address-cells = <1>;
	26	#size-cells = <0>;
	27
	28	cpu@0 {
	29	device_type = "cpu";
	30	model = "PowerPC,405EXr";
	31	reg = <0>;
	32	clock-frequency = <0>; /* Filled in by U-Boot */
	33	timebase-frequency = <0>; /* Filled in by U-Boot */
	34	i-cache-line-size = <20>;
	35	d-cache-line-size = <20>;
	36	i-cache-size = <4000>; /* 16 kB */
	37	d-cache-size = <4000>; /* 16 kB */
	38	dcr-controller;
	39	dcr-access-method = "native";
	40	};
	41	};
	42
	43	memory {
	44	device_type = "memory";
	45	reg = <0 0>; /* Filled in by U-Boot */
	46	};
	47
	48	UIC0: interrupt-controller {
	49	compatible = "ibm,uic-405exr", "ibm,uic";
	50	interrupt-controller;
	51	cell-index = <0>;
	52	dcr-reg = <0c0 009>;
	53	#address-cells = <0>;
	54	#size-cells = <0>;
	55	#interrupt-cells = <2>;
	56	};
	57
	58	UIC1: interrupt-controller1 {
	59	compatible = "ibm,uic-405exr","ibm,uic";
	60	interrupt-controller;
	61	cell-index = <1>;
	62	dcr-reg = <0d0 009>;
	63	#address-cells = <0>;
	64	#size-cells = <0>;
65	#interrupt-cells = <2>;
66	interrupts = <1e 4 1f 4>; /* cascade */
67	interrupt-parent = <&UIC0>;
68	};
69
70	UIC2: interrupt-controller2 {
71	compatible = "ibm,uic-405exr","ibm,uic";
72	interrupt-controller;
73	cell-index = <2>;
74	dcr-reg = <0e0 009>;
75	#address-cells = <0>;
76	#size-cells = <0>;
77	#interrupt-cells = <2>;
78	interrupts = <1c 4 1d 4>; /* cascade */
79	interrupt-parent = <&UIC0>;
80	};
81
82	plb {
83	compatible = "ibm,plb-405exr", "ibm,plb4";
84	#address-cells = <1>;
85	#size-cells = <1>;
86	ranges;
87	clock-frequency = <0>; /* Filled in by U-Boot */
88
89	SDRAM0: memory-controller {
90	compatible = "ibm,sdram-405exr";
91	dcr-reg = <010 2>;
92	};
93
94	MAL0: mcmal {
95	compatible = "ibm,mcmal-405exr", "ibm,mcmal2";
96	dcr-reg = <180 62>;
97	num-tx-chans = <2>;
98	num-rx-chans = <2>;
99	interrupt-parent = <&MAL0>;
100	interrupts = <0 1 2 3 4>;
101	#interrupt-cells = <1>;
102	#address-cells = <0>;
103	#size-cells = <0>;
104	interrupt-map = </TXEOB/ 0 &UIC0 a 4
105	/RXEOB/ 1 &UIC0 b 4
106	/SERR/ 2 &UIC1 0 4
107	/TXDE/ 3 &UIC1 1 4
108	/RXDE/ 4 &UIC1 2 4>;
109	interrupt-map-mask = <ffffffff>;
110	};
111
112	POB0: opb {
113	compatible = "ibm,opb-405exr", "ibm,opb";
114	#address-cells = <1>;
115	#size-cells = <1>;
116	ranges = <80000000 80000000 10000000
117	ef600000 ef600000 a00000
118	f0000000 f0000000 10000000>;
119	dcr-reg = <0a0 5>;
120	clock-frequency = <0>; /* Filled in by U-Boot */
121
122	EBC0: ebc {
123	compatible = "ibm,ebc-405exr", "ibm,ebc";
124	dcr-reg = <012 2>;
125	#address-cells = <2>;
126	#size-cells = <1>;
127	clock-frequency = <0>; /* Filled in by U-Boot */
128	/* ranges property is supplied by U-Boot */
129	interrupts = <5 1>;
130	interrupt-parent = <&UIC1>;
131
132	nor_flash@0,0 {
133	compatible = "amd,s29gl512n", "cfi-flash";
134	bank-width = <2>;
135	reg = <0 000000 4000000>;
136	#address-cells = <1>;
137	#size-cells = <1>;
138	partition@0 {
139	label = "kernel";
140	reg = <0 200000>;
141	};
142	partition@200000 {
143	label = "root";
144	reg = <200000 200000>;
145	};
146	partition@400000 {
147	label = "user";
148	reg = <400000 3b60000>;
149	};
150	partition@3f60000 {
151	label = "env";
152	reg = <3f60000 40000>;
153	};
154	partition@3fa0000 {
155	label = "u-boot";
156	reg = <3fa0000 60000>;
157	};
158	};
159	};
160
161	UART0: serial@ef600200 {
162	device_type = "serial";
163	compatible = "ns16550";
164	reg = <ef600200 8>;
165	virtual-reg = <ef600200>;
166	clock-frequency = <0>; /* Filled in by U-Boot */
167	current-speed = <0>;
168	interrupt-parent = <&UIC0>;
169	interrupts = <1a 4>;
170	};
171
172	UART1: serial@ef600300 {
173	device_type = "serial";
174	compatible = "ns16550";
175	reg = <ef600300 8>;
176	virtual-reg = <ef600300>;
177	clock-frequency = <0>; /* Filled in by U-Boot */
178	current-speed = <0>;
179	interrupt-parent = <&UIC0>;
180	interrupts = <1 4>;
181	};
182
183	IIC0: i2c@ef600400 {
184	compatible = "ibm,iic-405exr", "ibm,iic";
185	reg = <ef600400 14>;
186	interrupt-parent = <&UIC0>;
187	interrupts = <2 4>;
188	};
189
190	IIC1: i2c@ef600500 {
191	compatible = "ibm,iic-405exr", "ibm,iic";
192	reg = <ef600500 14>;
193	interrupt-parent = <&UIC0>;
194	interrupts = <7 4>;
195	};
196
197
198	RGMII0: emac-rgmii@ef600b00 {
199	compatible = "ibm,rgmii-405exr", "ibm,rgmii";
200	reg = <ef600b00 104>;
201	has-mdio;
202	};
203
204	EMAC0: ethernet@ef600900 {
205	linux,network-index = <0>;
206	device_type = "network";
207	compatible = "ibm,emac-405exr", "ibm,emac4";
208	interrupt-parent = <&EMAC0>;
209	interrupts = <0 1>;
210	#interrupt-cells = <1>;
211	#address-cells = <0>;
212	#size-cells = <0>;
213	interrupt-map = </Status/ 0 &UIC0 18 4
214	/Wake/ 1 &UIC1 1d 4>;
215	reg = <ef600900 70>;
216	local-mac-address = [000000000000]; /* Filled in by U-Boot */
217	mal-device = <&MAL0>;
218	mal-tx-channel = <0>;
219	mal-rx-channel = <0>;
220	cell-index = <0>;
221	max-frame-size = <5dc>;
222	rx-fifo-size = <1000>;
223	tx-fifo-size = <800>;
224	phy-mode = "rgmii";
225	phy-map = <00000000>;
226	rgmii-device = <&RGMII0>;
227	rgmii-channel = <0>;
228	has-inverted-stacr-oc;
229	has-new-stacr-staopc;
230	};
231	};
232
233	PCIE0: pciex@0a0000000 {
234	device_type = "pci";
235	#interrupt-cells = <1>;
236	#size-cells = <2>;
237	#address-cells = <3>;
e33eb074	238	compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
a4095516 SR	239	primary;
	240	port = <0>; /* port number */
	241	reg = <a0000000 20000000 /* Config space access */
	242	ef000000 00001000>; /* Registers */
	243	dcr-reg = <040 020>;
	244	sdr-base = <400>;
	245
	246	/* Outbound ranges, one memory and one IO,
	247	* later cannot be changed
	248	*/
	249	ranges = <02000000 0 80000000 90000000 0 08000000
	250	01000000 0 00000000 e0000000 0 00010000>;
	251
	252	/* Inbound 2GB range starting at 0 */
	253	dma-ranges = <42000000 0 0 0 0 80000000>;
	254
	255	/* This drives busses 0x00 to 0x3f */
	256	bus-range = <00 3f>;
	257
	258	/* Legacy interrupts (note the weird polarity, the bridge seems
	259	* to invert PCIe legacy interrupts).
	260	* We are de-swizzling here because the numbers are actually for
	261	* port of the root complex virtual P2P bridge. But I want
	262	* to avoid putting a node for it in the tree, so the numbers
	263	* below are basically de-swizzled numbers.
	264	* The real slot is on idsel 0, so the swizzling is 1:1
	265	*/
	266	interrupt-map-mask = <0000 0 0 7>;
	267	interrupt-map = <
	268	0000 0 0 1 &UIC2 0 4 /* swizzled int A */
	269	0000 0 0 2 &UIC2 1 4 /* swizzled int B */
	270	0000 0 0 3 &UIC2 2 4 /* swizzled int C */
	271	0000 0 0 4 &UIC2 3 4 /* swizzled int D */>;
	272	};
	273	};
	274	};