Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | ** SMP Support | |
3 | ** | |
4 | ** Copyright (C) 1999 Walt Drummond <drummond@valinux.com> | |
5 | ** Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com> | |
6 | ** Copyright (C) 2001,2004 Grant Grundler <grundler@parisc-linux.org> | |
7 | ** | |
8 | ** Lots of stuff stolen from arch/alpha/kernel/smp.c | |
9 | ** ...and then parisc stole from arch/ia64/kernel/smp.c. Thanks David! :^) | |
10 | ** | |
7022672e | 11 | ** Thanks to John Curry and Ullas Ponnadi. I learned a lot from their work. |
1da177e4 LT |
12 | ** -grant (1/12/2001) |
13 | ** | |
14 | ** This program is free software; you can redistribute it and/or modify | |
15 | ** it under the terms of the GNU General Public License as published by | |
16 | ** the Free Software Foundation; either version 2 of the License, or | |
17 | ** (at your option) any later version. | |
18 | */ | |
1da177e4 LT |
19 | #include <linux/types.h> |
20 | #include <linux/spinlock.h> | |
21 | #include <linux/slab.h> | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/sched.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/smp.h> | |
29 | #include <linux/kernel_stat.h> | |
30 | #include <linux/mm.h> | |
4e950f6f | 31 | #include <linux/err.h> |
1da177e4 LT |
32 | #include <linux/delay.h> |
33 | #include <linux/bitops.h> | |
34 | ||
35 | #include <asm/system.h> | |
36 | #include <asm/atomic.h> | |
37 | #include <asm/current.h> | |
38 | #include <asm/delay.h> | |
1b2425e3 | 39 | #include <asm/tlbflush.h> |
1da177e4 LT |
40 | |
41 | #include <asm/io.h> | |
42 | #include <asm/irq.h> /* for CPU_IRQ_REGION and friends */ | |
43 | #include <asm/mmu_context.h> | |
44 | #include <asm/page.h> | |
45 | #include <asm/pgtable.h> | |
46 | #include <asm/pgalloc.h> | |
47 | #include <asm/processor.h> | |
48 | #include <asm/ptrace.h> | |
49 | #include <asm/unistd.h> | |
50 | #include <asm/cacheflush.h> | |
51 | ||
5492a0f0 KM |
52 | #undef DEBUG_SMP |
53 | #ifdef DEBUG_SMP | |
54 | static int smp_debug_lvl = 0; | |
55 | #define smp_debug(lvl, printargs...) \ | |
56 | if (lvl >= smp_debug_lvl) \ | |
57 | printk(printargs); | |
58 | #else | |
59 | #define smp_debug(lvl, ...) | |
60 | #endif /* DEBUG_SMP */ | |
1da177e4 LT |
61 | |
62 | DEFINE_SPINLOCK(smp_lock); | |
63 | ||
64 | volatile struct task_struct *smp_init_current_idle_task; | |
65 | ||
8039de10 | 66 | static volatile int cpu_now_booting __read_mostly = 0; /* track which CPU is booting */ |
1da177e4 | 67 | |
8039de10 | 68 | static int parisc_max_cpus __read_mostly = 1; |
1da177e4 | 69 | |
3c97b5e9 | 70 | DEFINE_PER_CPU(spinlock_t, ipi_lock) = SPIN_LOCK_UNLOCKED; |
1da177e4 | 71 | |
1da177e4 LT |
72 | enum ipi_message_type { |
73 | IPI_NOP=0, | |
74 | IPI_RESCHEDULE=1, | |
75 | IPI_CALL_FUNC, | |
dbcf4787 | 76 | IPI_CALL_FUNC_SINGLE, |
1da177e4 LT |
77 | IPI_CPU_START, |
78 | IPI_CPU_STOP, | |
79 | IPI_CPU_TEST | |
80 | }; | |
81 | ||
82 | ||
83 | /********** SMP inter processor interrupt and communication routines */ | |
84 | ||
85 | #undef PER_CPU_IRQ_REGION | |
86 | #ifdef PER_CPU_IRQ_REGION | |
87 | /* XXX REVISIT Ignore for now. | |
88 | ** *May* need this "hook" to register IPI handler | |
89 | ** once we have perCPU ExtIntr switch tables. | |
90 | */ | |
91 | static void | |
92 | ipi_init(int cpuid) | |
93 | { | |
1da177e4 LT |
94 | #error verify IRQ_OFFSET(IPI_IRQ) is ipi_interrupt() in new IRQ region |
95 | ||
96 | if(cpu_online(cpuid) ) | |
97 | { | |
98 | switch_to_idle_task(current); | |
99 | } | |
100 | ||
101 | return; | |
102 | } | |
103 | #endif | |
104 | ||
105 | ||
106 | /* | |
107 | ** Yoink this CPU from the runnable list... | |
108 | ** | |
109 | */ | |
110 | static void | |
111 | halt_processor(void) | |
112 | { | |
1da177e4 LT |
113 | /* REVISIT : redirect I/O Interrupts to another CPU? */ |
114 | /* REVISIT : does PM *know* this CPU isn't available? */ | |
115 | cpu_clear(smp_processor_id(), cpu_online_map); | |
116 | local_irq_disable(); | |
117 | for (;;) | |
118 | ; | |
1da177e4 LT |
119 | } |
120 | ||
121 | ||
122 | irqreturn_t | |
c7753f18 | 123 | ipi_interrupt(int irq, void *dev_id) |
1da177e4 LT |
124 | { |
125 | int this_cpu = smp_processor_id(); | |
126 | struct cpuinfo_parisc *p = &cpu_data[this_cpu]; | |
127 | unsigned long ops; | |
128 | unsigned long flags; | |
129 | ||
130 | /* Count this now; we may make a call that never returns. */ | |
131 | p->ipi_count++; | |
132 | ||
133 | mb(); /* Order interrupt and bit testing. */ | |
134 | ||
135 | for (;;) { | |
3c97b5e9 KM |
136 | spinlock_t *lock = &per_cpu(ipi_lock, this_cpu); |
137 | spin_lock_irqsave(lock, flags); | |
1da177e4 LT |
138 | ops = p->pending_ipi; |
139 | p->pending_ipi = 0; | |
3c97b5e9 | 140 | spin_unlock_irqrestore(lock, flags); |
1da177e4 LT |
141 | |
142 | mb(); /* Order bit clearing and data access. */ | |
143 | ||
144 | if (!ops) | |
145 | break; | |
146 | ||
147 | while (ops) { | |
148 | unsigned long which = ffz(~ops); | |
149 | ||
d911aed8 JB |
150 | ops &= ~(1 << which); |
151 | ||
1da177e4 | 152 | switch (which) { |
d911aed8 | 153 | case IPI_NOP: |
5492a0f0 | 154 | smp_debug(100, KERN_DEBUG "CPU%d IPI_NOP\n", this_cpu); |
d911aed8 JB |
155 | break; |
156 | ||
1da177e4 | 157 | case IPI_RESCHEDULE: |
5492a0f0 | 158 | smp_debug(100, KERN_DEBUG "CPU%d IPI_RESCHEDULE\n", this_cpu); |
1da177e4 LT |
159 | /* |
160 | * Reschedule callback. Everything to be | |
161 | * done is done by the interrupt return path. | |
162 | */ | |
163 | break; | |
164 | ||
165 | case IPI_CALL_FUNC: | |
5492a0f0 | 166 | smp_debug(100, KERN_DEBUG "CPU%d IPI_CALL_FUNC\n", this_cpu); |
dbcf4787 JA |
167 | generic_smp_call_function_interrupt(); |
168 | break; | |
169 | ||
170 | case IPI_CALL_FUNC_SINGLE: | |
171 | smp_debug(100, KERN_DEBUG "CPU%d IPI_CALL_FUNC_SINGLE\n", this_cpu); | |
172 | generic_smp_call_function_single_interrupt(); | |
1da177e4 LT |
173 | break; |
174 | ||
175 | case IPI_CPU_START: | |
5492a0f0 | 176 | smp_debug(100, KERN_DEBUG "CPU%d IPI_CPU_START\n", this_cpu); |
1da177e4 LT |
177 | break; |
178 | ||
179 | case IPI_CPU_STOP: | |
5492a0f0 | 180 | smp_debug(100, KERN_DEBUG "CPU%d IPI_CPU_STOP\n", this_cpu); |
1da177e4 | 181 | halt_processor(); |
1da177e4 LT |
182 | break; |
183 | ||
184 | case IPI_CPU_TEST: | |
5492a0f0 | 185 | smp_debug(100, KERN_DEBUG "CPU%d is alive!\n", this_cpu); |
1da177e4 LT |
186 | break; |
187 | ||
188 | default: | |
189 | printk(KERN_CRIT "Unknown IPI num on CPU%d: %lu\n", | |
190 | this_cpu, which); | |
1da177e4 LT |
191 | return IRQ_NONE; |
192 | } /* Switch */ | |
7085689e JB |
193 | /* let in any pending interrupts */ |
194 | local_irq_enable(); | |
195 | local_irq_disable(); | |
1da177e4 LT |
196 | } /* while (ops) */ |
197 | } | |
198 | return IRQ_HANDLED; | |
199 | } | |
200 | ||
201 | ||
202 | static inline void | |
203 | ipi_send(int cpu, enum ipi_message_type op) | |
204 | { | |
205 | struct cpuinfo_parisc *p = &cpu_data[cpu]; | |
3c97b5e9 | 206 | spinlock_t *lock = &per_cpu(ipi_lock, cpu); |
1da177e4 LT |
207 | unsigned long flags; |
208 | ||
3c97b5e9 | 209 | spin_lock_irqsave(lock, flags); |
1da177e4 LT |
210 | p->pending_ipi |= 1 << op; |
211 | gsc_writel(IPI_IRQ - CPU_IRQ_BASE, cpu_data[cpu].hpa); | |
3c97b5e9 | 212 | spin_unlock_irqrestore(lock, flags); |
1da177e4 LT |
213 | } |
214 | ||
dbcf4787 JA |
215 | static void |
216 | send_IPI_mask(cpumask_t mask, enum ipi_message_type op) | |
217 | { | |
218 | int cpu; | |
219 | ||
220 | for_each_cpu_mask(cpu, mask) | |
221 | ipi_send(cpu, op); | |
222 | } | |
1da177e4 LT |
223 | |
224 | static inline void | |
225 | send_IPI_single(int dest_cpu, enum ipi_message_type op) | |
226 | { | |
227 | if (dest_cpu == NO_PROC_ID) { | |
228 | BUG(); | |
229 | return; | |
230 | } | |
231 | ||
232 | ipi_send(dest_cpu, op); | |
233 | } | |
234 | ||
235 | static inline void | |
236 | send_IPI_allbutself(enum ipi_message_type op) | |
237 | { | |
238 | int i; | |
239 | ||
394e3902 AM |
240 | for_each_online_cpu(i) { |
241 | if (i != smp_processor_id()) | |
1da177e4 LT |
242 | send_IPI_single(i, op); |
243 | } | |
244 | } | |
245 | ||
246 | ||
247 | inline void | |
248 | smp_send_stop(void) { send_IPI_allbutself(IPI_CPU_STOP); } | |
249 | ||
250 | static inline void | |
251 | smp_send_start(void) { send_IPI_allbutself(IPI_CPU_START); } | |
252 | ||
253 | void | |
254 | smp_send_reschedule(int cpu) { send_IPI_single(cpu, IPI_RESCHEDULE); } | |
255 | ||
d911aed8 JB |
256 | void |
257 | smp_send_all_nop(void) | |
258 | { | |
259 | send_IPI_allbutself(IPI_NOP); | |
260 | } | |
261 | ||
dbcf4787 | 262 | void arch_send_call_function_ipi(cpumask_t mask) |
1da177e4 | 263 | { |
dbcf4787 | 264 | send_IPI_mask(mask, IPI_CALL_FUNC); |
1da177e4 LT |
265 | } |
266 | ||
dbcf4787 JA |
267 | void arch_send_call_function_single_ipi(int cpu) |
268 | { | |
269 | send_IPI_single(cpu, IPI_CALL_FUNC_SINGLE); | |
270 | } | |
1da177e4 LT |
271 | |
272 | /* | |
273 | * Flush all other CPU's tlb and then mine. Do this with on_each_cpu() | |
274 | * as we want to ensure all TLB's flushed before proceeding. | |
275 | */ | |
276 | ||
1da177e4 LT |
277 | void |
278 | smp_flush_tlb_all(void) | |
279 | { | |
15c8b6c1 | 280 | on_each_cpu(flush_tlb_all_local, NULL, 1); |
1da177e4 LT |
281 | } |
282 | ||
1da177e4 LT |
283 | /* |
284 | * Called by secondaries to update state and initialize CPU registers. | |
285 | */ | |
286 | static void __init | |
287 | smp_cpu_init(int cpunum) | |
288 | { | |
56f335c8 | 289 | extern int init_per_cpu(int); /* arch/parisc/kernel/processor.c */ |
1da177e4 | 290 | extern void init_IRQ(void); /* arch/parisc/kernel/irq.c */ |
56f335c8 | 291 | extern void start_cpu_itimer(void); /* arch/parisc/kernel/time.c */ |
1da177e4 LT |
292 | |
293 | /* Set modes and Enable floating point coprocessor */ | |
294 | (void) init_per_cpu(cpunum); | |
295 | ||
296 | disable_sr_hashing(); | |
297 | ||
298 | mb(); | |
299 | ||
300 | /* Well, support 2.4 linux scheme as well. */ | |
301 | if (cpu_test_and_set(cpunum, cpu_online_map)) | |
302 | { | |
303 | extern void machine_halt(void); /* arch/parisc.../process.c */ | |
304 | ||
305 | printk(KERN_CRIT "CPU#%d already initialized!\n", cpunum); | |
306 | machine_halt(); | |
307 | } | |
308 | ||
309 | /* Initialise the idle task for this CPU */ | |
310 | atomic_inc(&init_mm.mm_count); | |
311 | current->active_mm = &init_mm; | |
312 | if(current->mm) | |
313 | BUG(); | |
314 | enter_lazy_tlb(&init_mm, current); | |
315 | ||
7022672e | 316 | init_IRQ(); /* make sure no IRQs are enabled or pending */ |
56f335c8 | 317 | start_cpu_itimer(); |
1da177e4 LT |
318 | } |
319 | ||
320 | ||
321 | /* | |
322 | * Slaves start using C here. Indirectly called from smp_slave_stext. | |
323 | * Do what start_kernel() and main() do for boot strap processor (aka monarch) | |
324 | */ | |
325 | void __init smp_callin(void) | |
326 | { | |
327 | int slave_id = cpu_now_booting; | |
1da177e4 LT |
328 | |
329 | smp_cpu_init(slave_id); | |
5bfb5d69 | 330 | preempt_disable(); |
1da177e4 | 331 | |
1da177e4 | 332 | flush_cache_all_local(); /* start with known state */ |
1b2425e3 | 333 | flush_tlb_all_local(NULL); |
1da177e4 LT |
334 | |
335 | local_irq_enable(); /* Interrupts have been off until now */ | |
336 | ||
337 | cpu_idle(); /* Wait for timer to schedule some work */ | |
338 | ||
339 | /* NOTREACHED */ | |
340 | panic("smp_callin() AAAAaaaaahhhh....\n"); | |
341 | } | |
342 | ||
343 | /* | |
344 | * Bring one cpu online. | |
345 | */ | |
8dff980f | 346 | int __cpuinit smp_boot_one_cpu(int cpuid) |
1da177e4 LT |
347 | { |
348 | struct task_struct *idle; | |
349 | long timeout; | |
350 | ||
351 | /* | |
352 | * Create an idle task for this CPU. Note the address wed* give | |
353 | * to kernel_thread is irrelevant -- it's going to start | |
354 | * where OS_BOOT_RENDEVZ vector in SAL says to start. But | |
355 | * this gets all the other task-y sort of data structures set | |
356 | * up like we wish. We need to pull the just created idle task | |
357 | * off the run queue and stuff it into the init_tasks[] array. | |
358 | * Sheesh . . . | |
359 | */ | |
360 | ||
361 | idle = fork_idle(cpuid); | |
362 | if (IS_ERR(idle)) | |
363 | panic("SMP: fork failed for CPU:%d", cpuid); | |
364 | ||
40f1f0de | 365 | task_thread_info(idle)->cpu = cpuid; |
1da177e4 LT |
366 | |
367 | /* Let _start know what logical CPU we're booting | |
368 | ** (offset into init_tasks[],cpu_data[]) | |
369 | */ | |
370 | cpu_now_booting = cpuid; | |
371 | ||
372 | /* | |
373 | ** boot strap code needs to know the task address since | |
374 | ** it also contains the process stack. | |
375 | */ | |
376 | smp_init_current_idle_task = idle ; | |
377 | mb(); | |
378 | ||
379 | printk("Releasing cpu %d now, hpa=%lx\n", cpuid, cpu_data[cpuid].hpa); | |
380 | ||
381 | /* | |
382 | ** This gets PDC to release the CPU from a very tight loop. | |
383 | ** | |
384 | ** From the PA-RISC 2.0 Firmware Architecture Reference Specification: | |
385 | ** "The MEM_RENDEZ vector specifies the location of OS_RENDEZ which | |
386 | ** is executed after receiving the rendezvous signal (an interrupt to | |
387 | ** EIR{0}). MEM_RENDEZ is valid only when it is nonzero and the | |
388 | ** contents of memory are valid." | |
389 | */ | |
390 | gsc_writel(TIMER_IRQ - CPU_IRQ_BASE, cpu_data[cpuid].hpa); | |
391 | mb(); | |
392 | ||
393 | /* | |
394 | * OK, wait a bit for that CPU to finish staggering about. | |
395 | * Slave will set a bit when it reaches smp_cpu_init(). | |
396 | * Once the "monarch CPU" sees the bit change, it can move on. | |
397 | */ | |
398 | for (timeout = 0; timeout < 10000; timeout++) { | |
399 | if(cpu_online(cpuid)) { | |
400 | /* Which implies Slave has started up */ | |
401 | cpu_now_booting = 0; | |
402 | smp_init_current_idle_task = NULL; | |
403 | goto alive ; | |
404 | } | |
405 | udelay(100); | |
406 | barrier(); | |
407 | } | |
408 | ||
409 | put_task_struct(idle); | |
410 | idle = NULL; | |
411 | ||
412 | printk(KERN_CRIT "SMP: CPU:%d is stuck.\n", cpuid); | |
413 | return -1; | |
414 | ||
415 | alive: | |
416 | /* Remember the Slave data */ | |
5492a0f0 | 417 | smp_debug(100, KERN_DEBUG "SMP: CPU:%d came alive after %ld _us\n", |
1da177e4 | 418 | cpuid, timeout * 100); |
1da177e4 LT |
419 | return 0; |
420 | } | |
421 | ||
422 | void __devinit smp_prepare_boot_cpu(void) | |
423 | { | |
424 | int bootstrap_processor=cpu_data[0].cpuid; /* CPU ID of BSP */ | |
425 | ||
1da177e4 LT |
426 | /* Setup BSP mappings */ |
427 | printk("SMP: bootstrap CPU ID is %d\n",bootstrap_processor); | |
428 | ||
429 | cpu_set(bootstrap_processor, cpu_online_map); | |
430 | cpu_set(bootstrap_processor, cpu_present_map); | |
431 | } | |
432 | ||
433 | ||
434 | ||
435 | /* | |
436 | ** inventory.c:do_inventory() hasn't yet been run and thus we | |
7022672e | 437 | ** don't 'discover' the additional CPUs until later. |
1da177e4 LT |
438 | */ |
439 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
440 | { | |
441 | cpus_clear(cpu_present_map); | |
442 | cpu_set(0, cpu_present_map); | |
443 | ||
444 | parisc_max_cpus = max_cpus; | |
445 | if (!max_cpus) | |
446 | printk(KERN_INFO "SMP mode deactivated.\n"); | |
447 | } | |
448 | ||
449 | ||
450 | void smp_cpus_done(unsigned int cpu_max) | |
451 | { | |
452 | return; | |
453 | } | |
454 | ||
455 | ||
b282b6f8 | 456 | int __cpuinit __cpu_up(unsigned int cpu) |
1da177e4 LT |
457 | { |
458 | if (cpu != 0 && cpu < parisc_max_cpus) | |
459 | smp_boot_one_cpu(cpu); | |
460 | ||
461 | return cpu_online(cpu) ? 0 : -ENOSYS; | |
462 | } | |
463 | ||
1da177e4 LT |
464 | #ifdef CONFIG_PROC_FS |
465 | int __init | |
466 | setup_profiling_timer(unsigned int multiplier) | |
467 | { | |
468 | return -EINVAL; | |
469 | } | |
470 | #endif |