[linux-2.6-block.git] / arch / parisc / kernel / cache.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
 * Copyright (C) 1999 SuSE GmbH Nuernberg
 * Copyright (C) 2000 Philipp Rumpf (prumpf@tux.org)
 *
 * Cache and TLB management
 *
 */
 
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/seq_file.h>
#include <linux/pagemap.h>
#include <linux/sched.h>
#include <asm/pdc.h>
#include <asm/cache.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/page.h>
#include <asm/pgalloc.h>
#include <asm/processor.h>
#include <asm/sections.h>
#include <asm/shmparam.h>

int split_tlb __read_mostly;
int dcache_stride __read_mostly;
int icache_stride __read_mostly;
EXPORT_SYMBOL(dcache_stride);

void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
EXPORT_SYMBOL(flush_dcache_page_asm);
void flush_icache_page_asm(unsigned long phys_addr, unsigned long vaddr);


/* On some machines (e.g. ones with the Merced bus), there can be
 * only a single PxTLB broadcast at a time; this must be guaranteed
 * by software.  We put a spinlock around all TLB flushes  to
 * ensure this.
 */
DEFINE_SPINLOCK(pa_tlb_lock);

struct pdc_cache_info cache_info __read_mostly;
#ifndef CONFIG_PA20
static struct pdc_btlb_info btlb_info __read_mostly;
#endif

#ifdef CONFIG_SMP
void
flush_data_cache(void)
{
	on_each_cpu(flush_data_cache_local, NULL, 1);
}
void 
flush_instruction_cache(void)
{
	on_each_cpu(flush_instruction_cache_local, NULL, 1);
}
#endif

void
flush_cache_all_local(void)
{
	flush_instruction_cache_local(NULL);
	flush_data_cache_local(NULL);
}
EXPORT_SYMBOL(flush_cache_all_local);

/* Virtual address of pfn.  */
#define pfn_va(pfn)	__va(PFN_PHYS(pfn))

void
update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
{
	unsigned long pfn = pte_pfn(*ptep);
	struct page *page;

	/* We don't have pte special.  As a result, we can be called with
	   an invalid pfn and we don't need to flush the kernel dcache page.
	   This occurs with FireGL card in C8000.  */
	if (!pfn_valid(pfn))
		return;

	page = pfn_to_page(pfn);
	if (page_mapping(page) && test_bit(PG_dcache_dirty, &page->flags)) {
		flush_kernel_dcache_page_addr(pfn_va(pfn));
		clear_bit(PG_dcache_dirty, &page->flags);
	} else if (parisc_requires_coherency())
		flush_kernel_dcache_page_addr(pfn_va(pfn));
}

void
show_cache_info(struct seq_file *m)
{
	char buf[32];

	seq_printf(m, "I-cache\t\t: %ld KB\n", 
		cache_info.ic_size/1024 );
	if (cache_info.dc_loop != 1)
		snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop);
	seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n",
		cache_info.dc_size/1024,
		(cache_info.dc_conf.cc_wt ? "WT":"WB"),
		(cache_info.dc_conf.cc_sh ? ", shared I/D":""),
		((cache_info.dc_loop == 1) ? "direct mapped" : buf));
	seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
		cache_info.it_size,
		cache_info.dt_size,
		cache_info.dt_conf.tc_sh ? " - shared with ITLB":""
	);
		
#ifndef CONFIG_PA20
	/* BTLB - Block TLB */
	if (btlb_info.max_size==0) {
		seq_printf(m, "BTLB\t\t: not supported\n" );
	} else {
		seq_printf(m, 
		"BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
		"BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
		"BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
		btlb_info.max_size, (int)4096,
		btlb_info.max_size>>8,
		btlb_info.fixed_range_info.num_i,
		btlb_info.fixed_range_info.num_d,
		btlb_info.fixed_range_info.num_comb, 
		btlb_info.variable_range_info.num_i,
		btlb_info.variable_range_info.num_d,
		btlb_info.variable_range_info.num_comb
		);
	}
#endif
}

void __init 
parisc_cache_init(void)
{
	if (pdc_cache_info(&cache_info) < 0)
		panic("parisc_cache_init: pdc_cache_info failed");

#if 0
	printk("ic_size %lx dc_size %lx it_size %lx\n",
		cache_info.ic_size,
		cache_info.dc_size,
		cache_info.it_size);

	printk("DC  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
		cache_info.dc_base,
		cache_info.dc_stride,
		cache_info.dc_count,
		cache_info.dc_loop);

	printk("dc_conf = 0x%lx  alias %d blk %d line %d shift %d\n",
		*(unsigned long *) (&cache_info.dc_conf),
		cache_info.dc_conf.cc_alias,
		cache_info.dc_conf.cc_block,
		cache_info.dc_conf.cc_line,
		cache_info.dc_conf.cc_shift);
	printk("	wt %d sh %d cst %d hv %d\n",
		cache_info.dc_conf.cc_wt,
		cache_info.dc_conf.cc_sh,
		cache_info.dc_conf.cc_cst,
		cache_info.dc_conf.cc_hv);

	printk("IC  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
		cache_info.ic_base,
		cache_info.ic_stride,
		cache_info.ic_count,
		cache_info.ic_loop);

	printk("IT  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx off_base 0x%lx off_stride 0x%lx off_count 0x%lx\n",
		cache_info.it_sp_base,
		cache_info.it_sp_stride,
		cache_info.it_sp_count,
		cache_info.it_loop,
		cache_info.it_off_base,
		cache_info.it_off_stride,
		cache_info.it_off_count);

	printk("DT  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx off_base 0x%lx off_stride 0x%lx off_count 0x%lx\n",
		cache_info.dt_sp_base,
		cache_info.dt_sp_stride,
		cache_info.dt_sp_count,
		cache_info.dt_loop,
		cache_info.dt_off_base,
		cache_info.dt_off_stride,
		cache_info.dt_off_count);

	printk("ic_conf = 0x%lx  alias %d blk %d line %d shift %d\n",
		*(unsigned long *) (&cache_info.ic_conf),
		cache_info.ic_conf.cc_alias,
		cache_info.ic_conf.cc_block,
		cache_info.ic_conf.cc_line,
		cache_info.ic_conf.cc_shift);
	printk("	wt %d sh %d cst %d hv %d\n",
		cache_info.ic_conf.cc_wt,
		cache_info.ic_conf.cc_sh,
		cache_info.ic_conf.cc_cst,
		cache_info.ic_conf.cc_hv);

	printk("D-TLB conf: sh %d page %d cst %d aid %d sr %d\n",
		cache_info.dt_conf.tc_sh,
		cache_info.dt_conf.tc_page,
		cache_info.dt_conf.tc_cst,
		cache_info.dt_conf.tc_aid,
		cache_info.dt_conf.tc_sr);

	printk("I-TLB conf: sh %d page %d cst %d aid %d sr %d\n",
		cache_info.it_conf.tc_sh,
		cache_info.it_conf.tc_page,
		cache_info.it_conf.tc_cst,
		cache_info.it_conf.tc_aid,
		cache_info.it_conf.tc_sr);
#endif

	split_tlb = 0;
	if (cache_info.dt_conf.tc_sh == 0 || cache_info.dt_conf.tc_sh == 2) {
		if (cache_info.dt_conf.tc_sh == 2)
			printk(KERN_WARNING "Unexpected TLB configuration. "
			"Will flush I/D separately (could be optimized).\n");

		split_tlb = 1;
	}

	/* "New and Improved" version from Jim Hull 
	 *	(1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
	 * The following CAFL_STRIDE is an optimized version, see
	 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html
	 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html
	 */
#define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
	dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
	icache_stride = CAFL_STRIDE(cache_info.ic_conf);
#undef CAFL_STRIDE

#ifndef CONFIG_PA20
	if (pdc_btlb_info(&btlb_info) < 0) {
		memset(&btlb_info, 0, sizeof btlb_info);
	}
#endif

	if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
						PDC_MODEL_NVA_UNSUPPORTED) {
		printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n");
#if 0
		panic("SMP kernel required to avoid non-equivalent aliasing");
#endif
	}
}

void disable_sr_hashing(void)
{
	int srhash_type, retval;
	unsigned long space_bits;

	switch (boot_cpu_data.cpu_type) {
	case pcx: /* We shouldn't get this far.  setup.c should prevent it. */
		BUG();
		return;

	case pcxs:
	case pcxt:
	case pcxt_:
		srhash_type = SRHASH_PCXST;
		break;

	case pcxl:
		srhash_type = SRHASH_PCXL;
		break;

	case pcxl2: /* pcxl2 doesn't support space register hashing */
		return;

	default: /* Currently all PA2.0 machines use the same ins. sequence */
		srhash_type = SRHASH_PA20;
		break;
	}

	disable_sr_hashing_asm(srhash_type);

	retval = pdc_spaceid_bits(&space_bits);
	/* If this procedure isn't implemented, don't panic. */
	if (retval < 0 && retval != PDC_BAD_OPTION)
		panic("pdc_spaceid_bits call failed.\n");
	if (space_bits != 0)
		panic("SpaceID hashing is still on!\n");
}

static inline void
__flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
		   unsigned long physaddr)
{
	preempt_disable();
	flush_dcache_page_asm(physaddr, vmaddr);
	if (vma->vm_flags & VM_EXEC)
		flush_icache_page_asm(physaddr, vmaddr);
	preempt_enable();
}

void flush_dcache_page(struct page *page)
{
	struct address_space *mapping = page_mapping(page);
	struct vm_area_struct *mpnt;
	unsigned long offset;
	unsigned long addr, old_addr = 0;
	pgoff_t pgoff;

	if (mapping && !mapping_mapped(mapping)) {
		set_bit(PG_dcache_dirty, &page->flags);
		return;
	}

	flush_kernel_dcache_page(page);

	if (!mapping)
		return;

	pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);

	/* We have carefully arranged in arch_get_unmapped_area() that
	 * *any* mappings of a file are always congruently mapped (whether
	 * declared as MAP_PRIVATE or MAP_SHARED), so we only need
	 * to flush one address here for them all to become coherent */

	flush_dcache_mmap_lock(mapping);
	vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) {
		offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
		addr = mpnt->vm_start + offset;

		/* The TLB is the engine of coherence on parisc: The
		 * CPU is entitled to speculate any page with a TLB
		 * mapping, so here we kill the mapping then flush the
		 * page along a special flush only alias mapping.
		 * This guarantees that the page is no-longer in the
		 * cache for any process and nor may it be
		 * speculatively read in (until the user or kernel
		 * specifically accesses it, of course) */

		flush_tlb_page(mpnt, addr);
		if (old_addr == 0 || (old_addr & (SHM_COLOUR - 1))
				      != (addr & (SHM_COLOUR - 1))) {
			__flush_cache_page(mpnt, addr, page_to_phys(page));
			if (old_addr)
				printk(KERN_ERR "INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %s\n", old_addr, addr, mpnt->vm_file ? (char *)mpnt->vm_file->f_path.dentry->d_name.name : "(null)");
			old_addr = addr;
		}
	}
	flush_dcache_mmap_unlock(mapping);
}
EXPORT_SYMBOL(flush_dcache_page);

/* Defined in arch/parisc/kernel/pacache.S */
EXPORT_SYMBOL(flush_kernel_dcache_range_asm);
EXPORT_SYMBOL(flush_kernel_dcache_page_asm);
EXPORT_SYMBOL(flush_data_cache_local);
EXPORT_SYMBOL(flush_kernel_icache_range_asm);

#define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
static unsigned long parisc_cache_flush_threshold __read_mostly = FLUSH_THRESHOLD;

#define FLUSH_TLB_THRESHOLD (2*1024*1024) /* 2MB initial TLB threshold */
static unsigned long parisc_tlb_flush_threshold __read_mostly = FLUSH_TLB_THRESHOLD;

void __init parisc_setup_cache_timing(void)
{
	unsigned long rangetime, alltime;
	unsigned long size, start;

	alltime = mfctl(16);
	flush_data_cache();
	alltime = mfctl(16) - alltime;

	size = (unsigned long)(_end - _text);
	rangetime = mfctl(16);
	flush_kernel_dcache_range((unsigned long)_text, size);
	rangetime = mfctl(16) - rangetime;

	printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",
		alltime, size, rangetime);

	/* Racy, but if we see an intermediate value, it's ok too... */
	parisc_cache_flush_threshold = size * alltime / rangetime;

	parisc_cache_flush_threshold = L1_CACHE_ALIGN(parisc_cache_flush_threshold);
	if (!parisc_cache_flush_threshold)
		parisc_cache_flush_threshold = FLUSH_THRESHOLD;

	if (parisc_cache_flush_threshold > cache_info.dc_size)
		parisc_cache_flush_threshold = cache_info.dc_size;

	printk(KERN_INFO "Setting cache flush threshold to %lu kB\n",
		parisc_cache_flush_threshold/1024);

	/* calculate TLB flush threshold */

	alltime = mfctl(16);
	flush_tlb_all();
	alltime = mfctl(16) - alltime;

	size = PAGE_SIZE;
	start = (unsigned long) _text;
	rangetime = mfctl(16);
	while (start < (unsigned long) _end) {
		flush_tlb_kernel_range(start, start + PAGE_SIZE);
		start += PAGE_SIZE;
		size += PAGE_SIZE;
	}
	rangetime = mfctl(16) - rangetime;

	printk(KERN_DEBUG "Whole TLB flush %lu cycles, flushing %lu bytes %lu cycles\n",
		alltime, size, rangetime);

	parisc_tlb_flush_threshold = size * alltime / rangetime;
	parisc_tlb_flush_threshold *= num_online_cpus();
	parisc_tlb_flush_threshold = PAGE_ALIGN(parisc_tlb_flush_threshold);
	if (!parisc_tlb_flush_threshold)
		parisc_tlb_flush_threshold = FLUSH_TLB_THRESHOLD;

	printk(KERN_INFO "Setting TLB flush threshold to %lu kB\n",
		parisc_tlb_flush_threshold/1024);
}

extern void purge_kernel_dcache_page_asm(unsigned long);
extern void clear_user_page_asm(void *, unsigned long);
extern void copy_user_page_asm(void *, void *, unsigned long);

void flush_kernel_dcache_page_addr(void *addr)
{
	unsigned long flags;

	flush_kernel_dcache_page_asm(addr);
	purge_tlb_start(flags);
	pdtlb_kernel(addr);
	purge_tlb_end(flags);
}
EXPORT_SYMBOL(flush_kernel_dcache_page_addr);

void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
	struct page *pg)
{
       /* Copy using kernel mapping.  No coherency is needed (all in
	  kunmap) for the `to' page.  However, the `from' page needs to
	  be flushed through a mapping equivalent to the user mapping
	  before it can be accessed through the kernel mapping. */
	preempt_disable();
	flush_dcache_page_asm(__pa(vfrom), vaddr);
	preempt_enable();
	copy_page_asm(vto, vfrom);
}
EXPORT_SYMBOL(copy_user_page);

/* __flush_tlb_range()
 *
 * returns 1 if all TLBs were flushed.
 */
int __flush_tlb_range(unsigned long sid, unsigned long start,
		      unsigned long end)
{
	unsigned long flags, size;

	size = (end - start);
	if (size >= parisc_tlb_flush_threshold) {
		flush_tlb_all();
		return 1;
	}

	/* Purge TLB entries for small ranges using the pdtlb and
	   pitlb instructions.  These instructions execute locally
	   but cause a purge request to be broadcast to other TLBs.  */
	if (likely(!split_tlb)) {
		while (start < end) {
			purge_tlb_start(flags);
			mtsp(sid, 1);
			pdtlb(start);
			purge_tlb_end(flags);
			start += PAGE_SIZE;
		}
		return 0;
	}

	/* split TLB case */
	while (start < end) {
		purge_tlb_start(flags);
		mtsp(sid, 1);
		pdtlb(start);
		pitlb(start);
		purge_tlb_end(flags);
		start += PAGE_SIZE;
	}
	return 0;
}

static void cacheflush_h_tmp_function(void *dummy)
{
	flush_cache_all_local();
}

void flush_cache_all(void)
{
	on_each_cpu(cacheflush_h_tmp_function, NULL, 1);
}

static inline unsigned long mm_total_size(struct mm_struct *mm)
{
	struct vm_area_struct *vma;
	unsigned long usize = 0;

	for (vma = mm->mmap; vma; vma = vma->vm_next)
		usize += vma->vm_end - vma->vm_start;
	return usize;
}

static inline pte_t *get_ptep(pgd_t *pgd, unsigned long addr)
{
	pte_t *ptep = NULL;

	if (!pgd_none(*pgd)) {
		pud_t *pud = pud_offset(pgd, addr);
		if (!pud_none(*pud)) {
			pmd_t *pmd = pmd_offset(pud, addr);
			if (!pmd_none(*pmd))
				ptep = pte_offset_map(pmd, addr);
		}
	}
	return ptep;
}

void flush_cache_mm(struct mm_struct *mm)
{
	struct vm_area_struct *vma;
	pgd_t *pgd;

	/* Flushing the whole cache on each cpu takes forever on
	   rp3440, etc.  So, avoid it if the mm isn't too big.  */
	if (mm_total_size(mm) >= parisc_cache_flush_threshold) {
		flush_cache_all();
		return;
	}

	if (mm->context == mfsp(3)) {
		for (vma = mm->mmap; vma; vma = vma->vm_next) {
			flush_user_dcache_range_asm(vma->vm_start, vma->vm_end);
			if ((vma->vm_flags & VM_EXEC) == 0)
				continue;
			flush_user_icache_range_asm(vma->vm_start, vma->vm_end);
		}
		return;
	}

	pgd = mm->pgd;
	for (vma = mm->mmap; vma; vma = vma->vm_next) {
		unsigned long addr;

		for (addr = vma->vm_start; addr < vma->vm_end;
		     addr += PAGE_SIZE) {
			unsigned long pfn;
			pte_t *ptep = get_ptep(pgd, addr);
			if (!ptep)
				continue;
			pfn = pte_pfn(*ptep);
			if (!pfn_valid(pfn))
				continue;
			__flush_cache_page(vma, addr, PFN_PHYS(pfn));
		}
	}
}

void
flush_user_dcache_range(unsigned long start, unsigned long end)
{
	if ((end - start) < parisc_cache_flush_threshold)
		flush_user_dcache_range_asm(start,end);
	else
		flush_data_cache();
}

void
flush_user_icache_range(unsigned long start, unsigned long end)
{
	if ((end - start) < parisc_cache_flush_threshold)
		flush_user_icache_range_asm(start,end);
	else
		flush_instruction_cache();
}

void flush_cache_range(struct vm_area_struct *vma,
		unsigned long start, unsigned long end)
{
	unsigned long addr;
	pgd_t *pgd;

	BUG_ON(!vma->vm_mm->context);

	if ((end - start) >= parisc_cache_flush_threshold) {
		flush_cache_all();
		return;
	}

	if (vma->vm_mm->context == mfsp(3)) {
		flush_user_dcache_range_asm(start, end);
		if (vma->vm_flags & VM_EXEC)
			flush_user_icache_range_asm(start, end);
		return;
	}

	pgd = vma->vm_mm->pgd;
	for (addr = start & PAGE_MASK; addr < end; addr += PAGE_SIZE) {
		unsigned long pfn;
		pte_t *ptep = get_ptep(pgd, addr);
		if (!ptep)
			continue;
		pfn = pte_pfn(*ptep);
		if (pfn_valid(pfn))
			__flush_cache_page(vma, addr, PFN_PHYS(pfn));
	}
}

void
flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
{
	BUG_ON(!vma->vm_mm->context);

	if (pfn_valid(pfn)) {
		flush_tlb_page(vma, vmaddr);
		__flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));
	}
}
Commit	Line	Data
071327ec	1	/*
1da177e4 LT	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
67a5a59d	6	* Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
1da177e4 LT	7	* Copyright (C) 1999 SuSE GmbH Nuernberg
	8	* Copyright (C) 2000 Philipp Rumpf (prumpf@tux.org)
	9	*
	10	* Cache and TLB management
	11	*
	12	*/
	13
	14	#include <linux/init.h>
	15	#include <linux/kernel.h>
	16	#include <linux/mm.h>
	17	#include <linux/module.h>
	18	#include <linux/seq_file.h>
	19	#include <linux/pagemap.h>
e8edc6e0	20	#include <linux/sched.h>
1da177e4 LT	21	#include <asm/pdc.h>
	22	#include <asm/cache.h>
	23	#include <asm/cacheflush.h>
	24	#include <asm/tlbflush.h>
1da177e4 LT	25	#include <asm/page.h>
	26	#include <asm/pgalloc.h>
	27	#include <asm/processor.h>
2464212f	28	#include <asm/sections.h>
f311847c	29	#include <asm/shmparam.h>
1da177e4	30
8039de10 HD	31	int split_tlb __read_mostly;
	32	int dcache_stride __read_mostly;
	33	int icache_stride __read_mostly;
1da177e4 LT	34	EXPORT_SYMBOL(dcache_stride);
1da177e4 LT	35
f311847c JB	36	void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
	37	EXPORT_SYMBOL(flush_dcache_page_asm);
	38	void flush_icache_page_asm(unsigned long phys_addr, unsigned long vaddr);
	39
1da177e4	40
1da177e4 LT	41	/* On some machines (e.g. ones with the Merced bus), there can be
	42	* only a single PxTLB broadcast at a time; this must be guaranteed
	43	* by software. We put a spinlock around all TLB flushes to
	44	* ensure this.
	45	*/
	46	DEFINE_SPINLOCK(pa_tlb_lock);
1da177e4	47
8039de10	48	struct pdc_cache_info cache_info __read_mostly;
1da177e4	49	#ifndef CONFIG_PA20
8039de10	50	static struct pdc_btlb_info btlb_info __read_mostly;
1da177e4 LT	51	#endif
	52
	53	#ifdef CONFIG_SMP
	54	void
	55	flush_data_cache(void)
	56	{
15c8b6c1	57	on_each_cpu(flush_data_cache_local, NULL, 1);
1da177e4 LT	58	}
	59	void
	60	flush_instruction_cache(void)
	61	{
15c8b6c1	62	on_each_cpu(flush_instruction_cache_local, NULL, 1);
1da177e4 LT	63	}
	64	#endif
	65
	66	void
	67	flush_cache_all_local(void)
	68	{
1b2425e3 MW	69	flush_instruction_cache_local(NULL);
1b2425e3 MW	70	flush_data_cache_local(NULL);
1da177e4 LT	71	}
	72	EXPORT_SYMBOL(flush_cache_all_local);
	73
50861f5a JDA	74	/* Virtual address of pfn. */
	75	#define pfn_va(pfn) __va(PFN_PHYS(pfn))
	76
1da177e4	77	void
4b3073e1	78	update_mmu_cache(struct vm_area_struct vma, unsigned long address, pte_t ptep)
1da177e4	79	{
50861f5a JDA	80	unsigned long pfn = pte_pfn(*ptep);
50861f5a JDA	81	struct page *page;
1da177e4	82
50861f5a JDA	83	/* We don't have pte special. As a result, we can be called with
	84	an invalid pfn and we don't need to flush the kernel dcache page.
	85	This occurs with FireGL card in C8000. */
	86	if (!pfn_valid(pfn))
	87	return;
1da177e4	88
50861f5a JDA	89	page = pfn_to_page(pfn);
	90	if (page_mapping(page) && test_bit(PG_dcache_dirty, &page->flags)) {
	91	flush_kernel_dcache_page_addr(pfn_va(pfn));
1da177e4	92	clear_bit(PG_dcache_dirty, &page->flags);
20f4d3cb	93	} else if (parisc_requires_coherency())
50861f5a	94	flush_kernel_dcache_page_addr(pfn_va(pfn));
1da177e4 LT	95	}
	96
	97	void
	98	show_cache_info(struct seq_file *m)
	99	{
e5a2e7fd KM	100	char buf[32];
e5a2e7fd KM	101
1da177e4 LT	102	seq_printf(m, "I-cache\t\t: %ld KB\n",
1da177e4 LT	103	cache_info.ic_size/1024 );
2f75c12c	104	if (cache_info.dc_loop != 1)
e5a2e7fd KM	105	snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop);
e5a2e7fd KM	106	seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n",
1da177e4 LT	107	cache_info.dc_size/1024,
	108	(cache_info.dc_conf.cc_wt ? "WT":"WB"),
	109	(cache_info.dc_conf.cc_sh ? ", shared I/D":""),
e5a2e7fd	110	((cache_info.dc_loop == 1) ? "direct mapped" : buf));
1da177e4 LT	111	seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
	112	cache_info.it_size,
	113	cache_info.dt_size,
	114	cache_info.dt_conf.tc_sh ? " - shared with ITLB":""
	115	);
	116
	117	#ifndef CONFIG_PA20
	118	/* BTLB - Block TLB */
	119	if (btlb_info.max_size==0) {
	120	seq_printf(m, "BTLB\t\t: not supported\n" );
	121	} else {
	122	seq_printf(m,
	123	"BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
	124	"BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
	125	"BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
	126	btlb_info.max_size, (int)4096,
	127	btlb_info.max_size>>8,
	128	btlb_info.fixed_range_info.num_i,
	129	btlb_info.fixed_range_info.num_d,
	130	btlb_info.fixed_range_info.num_comb,
	131	btlb_info.variable_range_info.num_i,
	132	btlb_info.variable_range_info.num_d,
	133	btlb_info.variable_range_info.num_comb
	134	);
	135	}
	136	#endif
	137	}
	138
	139	void __init
	140	parisc_cache_init(void)
	141	{
	142	if (pdc_cache_info(&cache_info) < 0)
	143	panic("parisc_cache_init: pdc_cache_info failed");
	144
	145	#if 0
	146	printk("ic_size %lx dc_size %lx it_size %lx\n",
	147	cache_info.ic_size,
	148	cache_info.dc_size,
	149	cache_info.it_size);
	150
	151	printk("DC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
	152	cache_info.dc_base,
	153	cache_info.dc_stride,
	154	cache_info.dc_count,
	155	cache_info.dc_loop);
	156
	157	printk("dc_conf = 0x%lx alias %d blk %d line %d shift %d\n",
	158	(unsigned long ) (&cache_info.dc_conf),
	159	cache_info.dc_conf.cc_alias,
	160	cache_info.dc_conf.cc_block,
	161	cache_info.dc_conf.cc_line,
	162	cache_info.dc_conf.cc_shift);
e5a2e7fd	163	printk(" wt %d sh %d cst %d hv %d\n",
1da177e4 LT	164	cache_info.dc_conf.cc_wt,
	165	cache_info.dc_conf.cc_sh,
	166	cache_info.dc_conf.cc_cst,
e5a2e7fd	167	cache_info.dc_conf.cc_hv);
1da177e4 LT	168
	169	printk("IC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
	170	cache_info.ic_base,
	171	cache_info.ic_stride,
	172	cache_info.ic_count,
	173	cache_info.ic_loop);
	174
2c2277dc HD	175	printk("IT base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx off_base 0x%lx off_stride 0x%lx off_count 0x%lx\n",
	176	cache_info.it_sp_base,
	177	cache_info.it_sp_stride,
	178	cache_info.it_sp_count,
	179	cache_info.it_loop,
	180	cache_info.it_off_base,
	181	cache_info.it_off_stride,
	182	cache_info.it_off_count);
	183
	184	printk("DT base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx off_base 0x%lx off_stride 0x%lx off_count 0x%lx\n",
	185	cache_info.dt_sp_base,
	186	cache_info.dt_sp_stride,
	187	cache_info.dt_sp_count,
	188	cache_info.dt_loop,
	189	cache_info.dt_off_base,
	190	cache_info.dt_off_stride,
	191	cache_info.dt_off_count);
	192
1da177e4 LT	193	printk("ic_conf = 0x%lx alias %d blk %d line %d shift %d\n",
	194	(unsigned long ) (&cache_info.ic_conf),
	195	cache_info.ic_conf.cc_alias,
	196	cache_info.ic_conf.cc_block,
	197	cache_info.ic_conf.cc_line,
	198	cache_info.ic_conf.cc_shift);
e5a2e7fd	199	printk(" wt %d sh %d cst %d hv %d\n",
1da177e4 LT	200	cache_info.ic_conf.cc_wt,
	201	cache_info.ic_conf.cc_sh,
	202	cache_info.ic_conf.cc_cst,
e5a2e7fd	203	cache_info.ic_conf.cc_hv);
1da177e4	204
2c2277dc	205	printk("D-TLB conf: sh %d page %d cst %d aid %d sr %d\n",
1da177e4 LT	206	cache_info.dt_conf.tc_sh,
	207	cache_info.dt_conf.tc_page,
	208	cache_info.dt_conf.tc_cst,
	209	cache_info.dt_conf.tc_aid,
2c2277dc	210	cache_info.dt_conf.tc_sr);
1da177e4	211
2c2277dc	212	printk("I-TLB conf: sh %d page %d cst %d aid %d sr %d\n",
1da177e4 LT	213	cache_info.it_conf.tc_sh,
	214	cache_info.it_conf.tc_page,
	215	cache_info.it_conf.tc_cst,
	216	cache_info.it_conf.tc_aid,
2c2277dc	217	cache_info.it_conf.tc_sr);
1da177e4 LT	218	#endif
	219
	220	split_tlb = 0;
	221	if (cache_info.dt_conf.tc_sh == 0 \|\| cache_info.dt_conf.tc_sh == 2) {
	222	if (cache_info.dt_conf.tc_sh == 2)
	223	printk(KERN_WARNING "Unexpected TLB configuration. "
	224	"Will flush I/D separately (could be optimized).\n");
	225
	226	split_tlb = 1;
	227	}
	228
	229	/* "New and Improved" version from Jim Hull
	230	* (1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
2464212f SB	231	* The following CAFL_STRIDE is an optimized version, see
	232	* http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html
	233	* http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html
1da177e4 LT	234	*/
	235	#define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
	236	dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
	237	icache_stride = CAFL_STRIDE(cache_info.ic_conf);
	238	#undef CAFL_STRIDE
	239
	240	#ifndef CONFIG_PA20
	241	if (pdc_btlb_info(&btlb_info) < 0) {
	242	memset(&btlb_info, 0, sizeof btlb_info);
	243	}
	244	#endif
	245
	246	if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
	247	PDC_MODEL_NVA_UNSUPPORTED) {
	248	printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n");
	249	#if 0
	250	panic("SMP kernel required to avoid non-equivalent aliasing");
	251	#endif
	252	}
	253	}
	254
	255	void disable_sr_hashing(void)
	256	{
a9d2d386 KM	257	int srhash_type, retval;
a9d2d386 KM	258	unsigned long space_bits;
1da177e4 LT	259
	260	switch (boot_cpu_data.cpu_type) {
	261	case pcx: /* We shouldn't get this far. setup.c should prevent it. */
	262	BUG();
	263	return;
	264
	265	case pcxs:
	266	case pcxt:
	267	case pcxt_:
	268	srhash_type = SRHASH_PCXST;
	269	break;
	270
	271	case pcxl:
	272	srhash_type = SRHASH_PCXL;
	273	break;
	274
	275	case pcxl2: /* pcxl2 doesn't support space register hashing */
	276	return;
	277
	278	default: /* Currently all PA2.0 machines use the same ins. sequence */
	279	srhash_type = SRHASH_PA20;
	280	break;
	281	}
	282
	283	disable_sr_hashing_asm(srhash_type);
a9d2d386 KM	284
	285	retval = pdc_spaceid_bits(&space_bits);
	286	/* If this procedure isn't implemented, don't panic. */
	287	if (retval < 0 && retval != PDC_BAD_OPTION)
	288	panic("pdc_spaceid_bits call failed.\n");
	289	if (space_bits != 0)
	290	panic("SpaceID hashing is still on!\n");
1da177e4 LT	291	}
1da177e4 LT	292
d6ce8626	293	static inline void
f311847c JB	294	__flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
f311847c JB	295	unsigned long physaddr)
d6ce8626	296	{
027f27c4	297	preempt_disable();
f311847c JB	298	flush_dcache_page_asm(physaddr, vmaddr);
	299	if (vma->vm_flags & VM_EXEC)
	300	flush_icache_page_asm(physaddr, vmaddr);
027f27c4	301	preempt_enable();
d6ce8626 RC	302	}
d6ce8626 RC	303
1da177e4 LT	304	void flush_dcache_page(struct page *page)
	305	{
	306	struct address_space *mapping = page_mapping(page);
	307	struct vm_area_struct *mpnt;
1da177e4	308	unsigned long offset;
f311847c	309	unsigned long addr, old_addr = 0;
1da177e4	310	pgoff_t pgoff;
1da177e4 LT	311
	312	if (mapping && !mapping_mapped(mapping)) {
	313	set_bit(PG_dcache_dirty, &page->flags);
	314	return;
	315	}
	316
ba575833	317	flush_kernel_dcache_page(page);
1da177e4 LT	318
	319	if (!mapping)
	320	return;
	321
	322	pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);
	323
	324	/* We have carefully arranged in arch_get_unmapped_area() that
	325	* any mappings of a file are always congruently mapped (whether
	326	* declared as MAP_PRIVATE or MAP_SHARED), so we only need
	327	* to flush one address here for them all to become coherent */
	328
	329	flush_dcache_mmap_lock(mapping);
6b2dbba8	330	vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) {
1da177e4 LT	331	offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
	332	addr = mpnt->vm_start + offset;
	333
b7d45818 JB	334	/* The TLB is the engine of coherence on parisc: The
	335	* CPU is entitled to speculate any page with a TLB
	336	* mapping, so here we kill the mapping then flush the
	337	* page along a special flush only alias mapping.
	338	* This guarantees that the page is no-longer in the
	339	* cache for any process and nor may it be
	340	* speculatively read in (until the user or kernel
	341	* specifically accesses it, of course) */
	342
	343	flush_tlb_page(mpnt, addr);
0ef36bd2 HD	344	if (old_addr == 0 \|\| (old_addr & (SHM_COLOUR - 1))
0ef36bd2 HD	345	!= (addr & (SHM_COLOUR - 1))) {
f311847c JB	346	__flush_cache_page(mpnt, addr, page_to_phys(page));
f311847c JB	347	if (old_addr)
b7d45818	348	printk(KERN_ERR "INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %s\n", old_addr, addr, mpnt->vm_file ? (char *)mpnt->vm_file->f_path.dentry->d_name.name : "(null)");
f311847c	349	old_addr = addr;
92dc6fcc	350	}
1da177e4 LT	351	}
	352	flush_dcache_mmap_unlock(mapping);
	353	}
	354	EXPORT_SYMBOL(flush_dcache_page);
	355
	356	/* Defined in arch/parisc/kernel/pacache.S */
	357	EXPORT_SYMBOL(flush_kernel_dcache_range_asm);
ba575833	358	EXPORT_SYMBOL(flush_kernel_dcache_page_asm);
1da177e4 LT	359	EXPORT_SYMBOL(flush_data_cache_local);
	360	EXPORT_SYMBOL(flush_kernel_icache_range_asm);
	361
1da177e4	362	#define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
01ab6057 JDA	363	static unsigned long parisc_cache_flush_threshold __read_mostly = FLUSH_THRESHOLD;
	364
	365	#define FLUSH_TLB_THRESHOLD (210241024) /* 2MB initial TLB threshold */
	366	static unsigned long parisc_tlb_flush_threshold __read_mostly = FLUSH_TLB_THRESHOLD;
1da177e4	367
d6ce8626	368	void __init parisc_setup_cache_timing(void)
1da177e4 LT	369	{
1da177e4 LT	370	unsigned long rangetime, alltime;
01ab6057	371	unsigned long size, start;
1da177e4 LT	372
	373	alltime = mfctl(16);
	374	flush_data_cache();
	375	alltime = mfctl(16) - alltime;
	376
2464212f	377	size = (unsigned long)(_end - _text);
1da177e4	378	rangetime = mfctl(16);
2464212f	379	flush_kernel_dcache_range((unsigned long)_text, size);
1da177e4 LT	380	rangetime = mfctl(16) - rangetime;
	381
	382	printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",
	383	alltime, size, rangetime);
	384
	385	/* Racy, but if we see an intermediate value, it's ok too... */
	386	parisc_cache_flush_threshold = size * alltime / rangetime;
	387
01ab6057	388	parisc_cache_flush_threshold = L1_CACHE_ALIGN(parisc_cache_flush_threshold);
1da177e4 LT	389	if (!parisc_cache_flush_threshold)
	390	parisc_cache_flush_threshold = FLUSH_THRESHOLD;
	391
d6ce8626 RC	392	if (parisc_cache_flush_threshold > cache_info.dc_size)
	393	parisc_cache_flush_threshold = cache_info.dc_size;
	394
01ab6057 JDA	395	printk(KERN_INFO "Setting cache flush threshold to %lu kB\n",
	396	parisc_cache_flush_threshold/1024);
	397
	398	/* calculate TLB flush threshold */
	399
	400	alltime = mfctl(16);
	401	flush_tlb_all();
	402	alltime = mfctl(16) - alltime;
	403
	404	size = PAGE_SIZE;
	405	start = (unsigned long) _text;
	406	rangetime = mfctl(16);
	407	while (start < (unsigned long) _end) {
	408	flush_tlb_kernel_range(start, start + PAGE_SIZE);
	409	start += PAGE_SIZE;
	410	size += PAGE_SIZE;
	411	}
	412	rangetime = mfctl(16) - rangetime;
	413
	414	printk(KERN_DEBUG "Whole TLB flush %lu cycles, flushing %lu bytes %lu cycles\n",
	415	alltime, size, rangetime);
	416
	417	parisc_tlb_flush_threshold = size * alltime / rangetime;
	418	parisc_tlb_flush_threshold *= num_online_cpus();
	419	parisc_tlb_flush_threshold = PAGE_ALIGN(parisc_tlb_flush_threshold);
	420	if (!parisc_tlb_flush_threshold)
	421	parisc_tlb_flush_threshold = FLUSH_TLB_THRESHOLD;
	422
	423	printk(KERN_INFO "Setting TLB flush threshold to %lu kB\n",
	424	parisc_tlb_flush_threshold/1024);
1da177e4	425	}
20f4d3cb	426
76334539 JDA	427	extern void purge_kernel_dcache_page_asm(unsigned long);
	428	extern void clear_user_page_asm(void *, unsigned long);
	429	extern void copy_user_page_asm(void , void , unsigned long);
20f4d3cb JB	430
	431	void flush_kernel_dcache_page_addr(void *addr)
	432	{
e82a3b75 HD	433	unsigned long flags;
e82a3b75 HD	434
20f4d3cb	435	flush_kernel_dcache_page_asm(addr);
e82a3b75	436	purge_tlb_start(flags);
20f4d3cb	437	pdtlb_kernel(addr);
e82a3b75	438	purge_tlb_end(flags);
20f4d3cb JB	439	}
	440	EXPORT_SYMBOL(flush_kernel_dcache_page_addr);
	441
57737c49 HD	442	void copy_user_page(void vto, void vfrom, unsigned long vaddr,
	443	struct page *pg)
	444	{
	445	/* Copy using kernel mapping. No coherency is needed (all in
	446	kunmap) for the `to' page. However, the `from' page needs to
	447	be flushed through a mapping equivalent to the user mapping
	448	before it can be accessed through the kernel mapping. */
	449	preempt_disable();
	450	flush_dcache_page_asm(__pa(vfrom), vaddr);
	451	preempt_enable();
	452	copy_page_asm(vto, vfrom);
	453	}
	454	EXPORT_SYMBOL(copy_user_page);
	455
01ab6057 JDA	456	/* __flush_tlb_range()
	457	*
	458	* returns 1 if all TLBs were flushed.
	459	*/
	460	int __flush_tlb_range(unsigned long sid, unsigned long start,
	461	unsigned long end)
d6ce8626	462	{
01ab6057	463	unsigned long flags, size;
d6ce8626	464
01ab6057 JDA	465	size = (end - start);
01ab6057 JDA	466	if (size >= parisc_tlb_flush_threshold) {
d6ce8626	467	flush_tlb_all();
01ab6057 JDA	468	return 1;
01ab6057 JDA	469	}
e82a3b75	470
01ab6057 JDA	471	/* Purge TLB entries for small ranges using the pdtlb and
	472	pitlb instructions. These instructions execute locally
	473	but cause a purge request to be broadcast to other TLBs. */
	474	if (likely(!split_tlb)) {
	475	while (start < end) {
	476	purge_tlb_start(flags);
	477	mtsp(sid, 1);
	478	pdtlb(start);
	479	purge_tlb_end(flags);
	480	start += PAGE_SIZE;
	481	}
	482	return 0;
	483	}
	484
	485	/* split TLB case */
	486	while (start < end) {
e82a3b75	487	purge_tlb_start(flags);
e8d8fc21	488	mtsp(sid, 1);
01ab6057 JDA	489	pdtlb(start);
01ab6057 JDA	490	pitlb(start);
e82a3b75	491	purge_tlb_end(flags);
01ab6057	492	start += PAGE_SIZE;
d6ce8626	493	}
01ab6057	494	return 0;
d6ce8626 RC	495	}
	496
	497	static void cacheflush_h_tmp_function(void *dummy)
	498	{
	499	flush_cache_all_local();
	500	}
	501
	502	void flush_cache_all(void)
	503	{
15c8b6c1	504	on_each_cpu(cacheflush_h_tmp_function, NULL, 1);
d6ce8626 RC	505	}
d6ce8626 RC	506
6d2439d9 JDA	507	static inline unsigned long mm_total_size(struct mm_struct *mm)
	508	{
	509	struct vm_area_struct *vma;
	510	unsigned long usize = 0;
	511
	512	for (vma = mm->mmap; vma; vma = vma->vm_next)
	513	usize += vma->vm_end - vma->vm_start;
	514	return usize;
	515	}
	516
	517	static inline pte_t get_ptep(pgd_t pgd, unsigned long addr)
	518	{
	519	pte_t *ptep = NULL;
	520
	521	if (!pgd_none(*pgd)) {
	522	pud_t *pud = pud_offset(pgd, addr);
	523	if (!pud_none(*pud)) {
	524	pmd_t *pmd = pmd_offset(pud, addr);
	525	if (!pmd_none(*pmd))
	526	ptep = pte_offset_map(pmd, addr);
	527	}
	528	}
	529	return ptep;
	530	}
	531
d6ce8626 RC	532	void flush_cache_mm(struct mm_struct *mm)
d6ce8626 RC	533	{
50861f5a JDA	534	struct vm_area_struct *vma;
	535	pgd_t *pgd;
	536
6d2439d9 JDA	537	/* Flushing the whole cache on each cpu takes forever on
6d2439d9 JDA	538	rp3440, etc. So, avoid it if the mm isn't too big. */
50861f5a JDA	539	if (mm_total_size(mm) >= parisc_cache_flush_threshold) {
	540	flush_cache_all();
	541	return;
	542	}
	543
	544	if (mm->context == mfsp(3)) {
	545	for (vma = mm->mmap; vma; vma = vma->vm_next) {
	546	flush_user_dcache_range_asm(vma->vm_start, vma->vm_end);
	547	if ((vma->vm_flags & VM_EXEC) == 0)
	548	continue;
	549	flush_user_icache_range_asm(vma->vm_start, vma->vm_end);
6d2439d9 JDA	550	}
	551	return;
	552	}
	553
50861f5a JDA	554	pgd = mm->pgd;
	555	for (vma = mm->mmap; vma; vma = vma->vm_next) {
	556	unsigned long addr;
	557
	558	for (addr = vma->vm_start; addr < vma->vm_end;
	559	addr += PAGE_SIZE) {
	560	unsigned long pfn;
	561	pte_t *ptep = get_ptep(pgd, addr);
	562	if (!ptep)
	563	continue;
	564	pfn = pte_pfn(*ptep);
	565	if (!pfn_valid(pfn))
	566	continue;
	567	__flush_cache_page(vma, addr, PFN_PHYS(pfn));
	568	}
	569	}
d6ce8626 RC	570	}
	571
	572	void
	573	flush_user_dcache_range(unsigned long start, unsigned long end)
	574	{
	575	if ((end - start) < parisc_cache_flush_threshold)
	576	flush_user_dcache_range_asm(start,end);
	577	else
	578	flush_data_cache();
	579	}
	580
	581	void
	582	flush_user_icache_range(unsigned long start, unsigned long end)
	583	{
	584	if ((end - start) < parisc_cache_flush_threshold)
	585	flush_user_icache_range_asm(start,end);
	586	else
	587	flush_instruction_cache();
	588	}
	589
d6ce8626 RC	590	void flush_cache_range(struct vm_area_struct *vma,
	591	unsigned long start, unsigned long end)
	592	{
50861f5a JDA	593	unsigned long addr;
	594	pgd_t *pgd;
	595
8980a7ba	596	BUG_ON(!vma->vm_mm->context);
d6ce8626	597
50861f5a	598	if ((end - start) >= parisc_cache_flush_threshold) {
d6ce8626	599	flush_cache_all();
50861f5a JDA	600	return;
	601	}
	602
	603	if (vma->vm_mm->context == mfsp(3)) {
	604	flush_user_dcache_range_asm(start, end);
	605	if (vma->vm_flags & VM_EXEC)
	606	flush_user_icache_range_asm(start, end);
	607	return;
	608	}
	609
	610	pgd = vma->vm_mm->pgd;
	611	for (addr = start & PAGE_MASK; addr < end; addr += PAGE_SIZE) {
	612	unsigned long pfn;
	613	pte_t *ptep = get_ptep(pgd, addr);
	614	if (!ptep)
	615	continue;
	616	pfn = pte_pfn(*ptep);
	617	if (pfn_valid(pfn))
	618	__flush_cache_page(vma, addr, PFN_PHYS(pfn));
d6ce8626 RC	619	}
	620	}
	621
	622	void
	623	flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
	624	{
	625	BUG_ON(!vma->vm_mm->context);
	626
50861f5a JDA	627	if (pfn_valid(pfn)) {
	628	flush_tlb_page(vma, vmaddr);
	629	__flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));
	630	}
d6ce8626	631	}