[linux-2.6-block.git] / arch / mips / sgi-ip27 / ip27-nmi.c

// SPDX-License-Identifier: GPL-2.0
#include <linux/kernel.h>
#include <linux/mmzone.h>
#include <linux/nodemask.h>
#include <linux/spinlock.h>
#include <linux/smp.h>
#include <linux/atomic.h>
#include <asm/sn/types.h>
#include <asm/sn/addrs.h>
#include <asm/sn/nmi.h>
#include <asm/sn/arch.h>
#include <asm/sn/sn0/hub.h>

#if 0
#define NODE_NUM_CPUS(n)	CNODE_NUM_CPUS(n)
#else
#define NODE_NUM_CPUS(n)	CPUS_PER_NODE
#endif

typedef unsigned long machreg_t;

static arch_spinlock_t nmi_lock = __ARCH_SPIN_LOCK_UNLOCKED;

/*
 * Let's see what else we need to do here. Set up sp, gp?
 */
void nmi_dump(void)
{
	void cont_nmi_dump(void);

	cont_nmi_dump();
}

void install_cpu_nmi_handler(int slice)
{
	nmi_t *nmi_addr;

	nmi_addr = (nmi_t *)NMI_ADDR(get_nasid(), slice);
	if (nmi_addr->call_addr)
		return;
	nmi_addr->magic = NMI_MAGIC;
	nmi_addr->call_addr = (void *)nmi_dump;
	nmi_addr->call_addr_c =
		(void *)(~((unsigned long)(nmi_addr->call_addr)));
	nmi_addr->call_parm = 0;
}

/*
 * Copy the cpu registers which have been saved in the IP27prom format
 * into the eframe format for the node under consideration.
 */

void nmi_cpu_eframe_save(nasid_t nasid, int slice)
{
	struct reg_struct *nr;
	int		i;

	/* Get the pointer to the current cpu's register set. */
	nr = (struct reg_struct *)
		(TO_UNCAC(TO_NODE(nasid, IP27_NMI_KREGS_OFFSET)) +
		slice * IP27_NMI_KREGS_CPU_SIZE);

	pr_emerg("NMI nasid %d: slice %d\n", nasid, slice);

	/*
	 * Saved main processor registers
	 */
	for (i = 0; i < 32; ) {
		if ((i % 4) == 0)
			pr_emerg("$%2d   :", i);
		pr_cont(" %016lx", nr->gpr[i]);

		i++;
		if ((i % 4) == 0)
			pr_cont("\n");
	}

	pr_emerg("Hi    : (value lost)\n");
	pr_emerg("Lo    : (value lost)\n");

	/*
	 * Saved cp0 registers
	 */
	pr_emerg("epc   : %016lx %pS\n", nr->epc, (void *)nr->epc);
	pr_emerg("%s\n", print_tainted());
	pr_emerg("ErrEPC: %016lx %pS\n", nr->error_epc, (void *)nr->error_epc);
	pr_emerg("ra    : %016lx %pS\n", nr->gpr[31], (void *)nr->gpr[31]);
	pr_emerg("Status: %08lx	      ", nr->sr);

	if (nr->sr & ST0_KX)
		pr_cont("KX ");
	if (nr->sr & ST0_SX)
		pr_cont("SX ");
	if (nr->sr & ST0_UX)
		pr_cont("UX ");

	switch (nr->sr & ST0_KSU) {
	case KSU_USER:
		pr_cont("USER ");
		break;
	case KSU_SUPERVISOR:
		pr_cont("SUPERVISOR ");
		break;
	case KSU_KERNEL:
		pr_cont("KERNEL ");
		break;
	default:
		pr_cont("BAD_MODE ");
		break;
	}

	if (nr->sr & ST0_ERL)
		pr_cont("ERL ");
	if (nr->sr & ST0_EXL)
		pr_cont("EXL ");
	if (nr->sr & ST0_IE)
		pr_cont("IE ");
	pr_cont("\n");

	pr_emerg("Cause : %08lx\n", nr->cause);
	pr_emerg("PrId  : %08x\n", read_c0_prid());
	pr_emerg("BadVA : %016lx\n", nr->badva);
	pr_emerg("CErr  : %016lx\n", nr->cache_err);
	pr_emerg("NMI_SR: %016lx\n", nr->nmi_sr);

	pr_emerg("\n");
}

void nmi_dump_hub_irq(nasid_t nasid, int slice)
{
	u64 mask0, mask1, pend0, pend1;

	if (slice == 0) {				/* Slice A */
		mask0 = REMOTE_HUB_L(nasid, PI_INT_MASK0_A);
		mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_A);
	} else {					/* Slice B */
		mask0 = REMOTE_HUB_L(nasid, PI_INT_MASK0_B);
		mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_B);
	}

	pend0 = REMOTE_HUB_L(nasid, PI_INT_PEND0);
	pend1 = REMOTE_HUB_L(nasid, PI_INT_PEND1);

	pr_emerg("PI_INT_MASK0: %16llx PI_INT_MASK1: %16llx\n", mask0, mask1);
	pr_emerg("PI_INT_PEND0: %16llx PI_INT_PEND1: %16llx\n", pend0, pend1);
	pr_emerg("\n\n");
}

/*
 * Copy the cpu registers which have been saved in the IP27prom format
 * into the eframe format for the node under consideration.
 */
void nmi_node_eframe_save(nasid_t nasid)
{
	int slice;

	if (nasid == INVALID_NASID)
		return;

	/* Save the registers into eframe for each cpu */
	for (slice = 0; slice < NODE_NUM_CPUS(slice); slice++) {
		nmi_cpu_eframe_save(nasid, slice);
		nmi_dump_hub_irq(nasid, slice);
	}
}

/*
 * Save the nmi cpu registers for all cpus in the system.
 */
void
nmi_eframes_save(void)
{
	nasid_t nasid;

	for_each_online_node(nasid)
		nmi_node_eframe_save(nasid);
}

void
cont_nmi_dump(void)
{
#ifndef REAL_NMI_SIGNAL
	static atomic_t nmied_cpus = ATOMIC_INIT(0);

	atomic_inc(&nmied_cpus);
#endif
	/*
	 * Only allow 1 cpu to proceed
	 */
	arch_spin_lock(&nmi_lock);

#ifdef REAL_NMI_SIGNAL
	/*
	 * Wait up to 15 seconds for the other cpus to respond to the NMI.
	 * If a cpu has not responded after 10 sec, send it 1 additional NMI.
	 * This is for 2 reasons:
	 *	- sometimes a MMSC fail to NMI all cpus.
	 *	- on 512p SN0 system, the MMSC will only send NMIs to
	 *	  half the cpus. Unfortunately, we don't know which cpus may be
	 *	  NMIed - it depends on how the site chooses to configure.
	 *
	 * Note: it has been measure that it takes the MMSC up to 2.3 secs to
	 * send NMIs to all cpus on a 256p system.
	 */
	for (i=0; i < 1500; i++) {
		for_each_online_node(node)
			if (NODEPDA(node)->dump_count == 0)
				break;
		if (node == MAX_NUMNODES)
			break;
		if (i == 1000) {
			for_each_online_node(node)
				if (NODEPDA(node)->dump_count == 0) {
					cpu = cpumask_first(cpumask_of_node(node));
					for (n=0; n < CNODE_NUM_CPUS(node); cpu++, n++) {
						CPUMASK_SETB(nmied_cpus, cpu);
						/*
						 * cputonasid, cputoslice
						 * needs kernel cpuid
						 */
						SEND_NMI((cputonasid(cpu)), (cputoslice(cpu)));
					}
				}

		}
		udelay(10000);
	}
#else
	while (atomic_read(&nmied_cpus) != num_online_cpus());
#endif

	/*
	 * Save the nmi cpu registers for all cpu in the eframe format.
	 */
	nmi_eframes_save();
	LOCAL_HUB_S(NI_PORT_RESET, NPR_PORTRESET | NPR_LOCALRESET);
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4 LT	2	#include <linux/kernel.h>
	3	#include <linux/mmzone.h>
	4	#include <linux/nodemask.h>
	5	#include <linux/spinlock.h>
	6	#include <linux/smp.h>
60063497	7	#include <linux/atomic.h>
1da177e4 LT	8	#include <asm/sn/types.h>
	9	#include <asm/sn/addrs.h>
	10	#include <asm/sn/nmi.h>
	11	#include <asm/sn/arch.h>
	12	#include <asm/sn/sn0/hub.h>
	13
	14	#if 0
	15	#define NODE_NUM_CPUS(n) CNODE_NUM_CPUS(n)
	16	#else
	17	#define NODE_NUM_CPUS(n) CPUS_PER_NODE
	18	#endif
	19
1da177e4 LT	20	typedef unsigned long machreg_t;
1da177e4 LT	21
598c5aba	22	static arch_spinlock_t nmi_lock = __ARCH_SPIN_LOCK_UNLOCKED;
1da177e4 LT	23
1da177e4 LT	24	/*
4939788e	25	* Let's see what else we need to do here. Set up sp, gp?
1da177e4 LT	26	*/
	27	void nmi_dump(void)
	28	{
	29	void cont_nmi_dump(void);
	30
	31	cont_nmi_dump();
	32	}
	33
	34	void install_cpu_nmi_handler(int slice)
	35	{
	36	nmi_t *nmi_addr;
	37
	38	nmi_addr = (nmi_t *)NMI_ADDR(get_nasid(), slice);
	39	if (nmi_addr->call_addr)
	40	return;
	41	nmi_addr->magic = NMI_MAGIC;
	42	nmi_addr->call_addr = (void *)nmi_dump;
	43	nmi_addr->call_addr_c =
	44	(void *)(~((unsigned long)(nmi_addr->call_addr)));
	45	nmi_addr->call_parm = 0;
	46	}
	47
	48	/*
	49	* Copy the cpu registers which have been saved in the IP27prom format
	50	* into the eframe format for the node under consideration.
	51	*/
	52
	53	void nmi_cpu_eframe_save(nasid_t nasid, int slice)
	54	{
	55	struct reg_struct *nr;
70342287	56	int i;
1da177e4 LT	57
	58	/* Get the pointer to the current cpu's register set. */
	59	nr = (struct reg_struct *)
	60	(TO_UNCAC(TO_NODE(nasid, IP27_NMI_KREGS_OFFSET)) +
	61	slice * IP27_NMI_KREGS_CPU_SIZE);
	62
ab68280e	63	pr_emerg("NMI nasid %d: slice %d\n", nasid, slice);
1da177e4 LT	64
	65	/*
	66	* Saved main processor registers
	67	*/
	68	for (i = 0; i < 32; ) {
	69	if ((i % 4) == 0)
ab68280e TB	70	pr_emerg("$%2d :", i);
ab68280e TB	71	pr_cont(" %016lx", nr->gpr[i]);
1da177e4 LT	72
	73	i++;
	74	if ((i % 4) == 0)
ab68280e	75	pr_cont("\n");
1da177e4 LT	76	}
1da177e4 LT	77
ab68280e TB	78	pr_emerg("Hi : (value lost)\n");
ab68280e TB	79	pr_emerg("Lo : (value lost)\n");
1da177e4 LT	80
	81	/*
	82	* Saved cp0 registers
	83	*/
ab68280e TB	84	pr_emerg("epc : %016lx %pS\n", nr->epc, (void *)nr->epc);
	85	pr_emerg("%s\n", print_tainted());
	86	pr_emerg("ErrEPC: %016lx %pS\n", nr->error_epc, (void *)nr->error_epc);
	87	pr_emerg("ra : %016lx %pS\n", nr->gpr[31], (void *)nr->gpr[31]);
	88	pr_emerg("Status: %08lx ", nr->sr);
1da177e4 LT	89
1da177e4 LT	90	if (nr->sr & ST0_KX)
ab68280e	91	pr_cont("KX ");
1da177e4	92	if (nr->sr & ST0_SX)
ab68280e	93	pr_cont("SX ");
1da177e4	94	if (nr->sr & ST0_UX)
ab68280e	95	pr_cont("UX ");
1da177e4 LT	96
	97	switch (nr->sr & ST0_KSU) {
	98	case KSU_USER:
ab68280e	99	pr_cont("USER ");
1da177e4 LT	100	break;
1da177e4 LT	101	case KSU_SUPERVISOR:
ab68280e	102	pr_cont("SUPERVISOR ");
1da177e4 LT	103	break;
1da177e4 LT	104	case KSU_KERNEL:
ab68280e	105	pr_cont("KERNEL ");
1da177e4 LT	106	break;
1da177e4 LT	107	default:
ab68280e	108	pr_cont("BAD_MODE ");
1da177e4 LT	109	break;
	110	}
	111
	112	if (nr->sr & ST0_ERL)
ab68280e	113	pr_cont("ERL ");
1da177e4	114	if (nr->sr & ST0_EXL)
ab68280e	115	pr_cont("EXL ");
1da177e4	116	if (nr->sr & ST0_IE)
ab68280e TB	117	pr_cont("IE ");
ab68280e TB	118	pr_cont("\n");
1da177e4	119
ab68280e TB	120	pr_emerg("Cause : %08lx\n", nr->cause);
	121	pr_emerg("PrId : %08x\n", read_c0_prid());
	122	pr_emerg("BadVA : %016lx\n", nr->badva);
	123	pr_emerg("CErr : %016lx\n", nr->cache_err);
	124	pr_emerg("NMI_SR: %016lx\n", nr->nmi_sr);
1da177e4	125
ab68280e	126	pr_emerg("\n");
1da177e4 LT	127	}
	128
	129	void nmi_dump_hub_irq(nasid_t nasid, int slice)
	130	{
db0e7d4e	131	u64 mask0, mask1, pend0, pend1;
1da177e4 LT	132
	133	if (slice == 0) { /* Slice A */
	134	mask0 = REMOTE_HUB_L(nasid, PI_INT_MASK0_A);
	135	mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_A);
	136	} else { /* Slice B */
	137	mask0 = REMOTE_HUB_L(nasid, PI_INT_MASK0_B);
	138	mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_B);
	139	}
	140
	141	pend0 = REMOTE_HUB_L(nasid, PI_INT_PEND0);
	142	pend1 = REMOTE_HUB_L(nasid, PI_INT_PEND1);
	143
ab68280e TB	144	pr_emerg("PI_INT_MASK0: %16llx PI_INT_MASK1: %16llx\n", mask0, mask1);
	145	pr_emerg("PI_INT_PEND0: %16llx PI_INT_PEND1: %16llx\n", pend0, pend1);
	146	pr_emerg("\n\n");
1da177e4 LT	147	}
	148
	149	/*
	150	* Copy the cpu registers which have been saved in the IP27prom format
	151	* into the eframe format for the node under consideration.
	152	*/
4bf841eb	153	void nmi_node_eframe_save(nasid_t nasid)
1da177e4	154	{
1da177e4 LT	155	int slice;
1da177e4 LT	156
1da177e4 LT	157	if (nasid == INVALID_NASID)
	158	return;
	159
	160	/* Save the registers into eframe for each cpu */
	161	for (slice = 0; slice < NODE_NUM_CPUS(slice); slice++) {
	162	nmi_cpu_eframe_save(nasid, slice);
	163	nmi_dump_hub_irq(nasid, slice);
	164	}
	165	}
	166
	167	/*
	168	* Save the nmi cpu registers for all cpus in the system.
	169	*/
	170	void
	171	nmi_eframes_save(void)
	172	{
4bf841eb	173	nasid_t nasid;
1da177e4	174
4bf841eb TB	175	for_each_online_node(nasid)
4bf841eb TB	176	nmi_node_eframe_save(nasid);
1da177e4 LT	177	}
	178
	179	void
	180	cont_nmi_dump(void)
	181	{
	182	#ifndef REAL_NMI_SIGNAL
	183	static atomic_t nmied_cpus = ATOMIC_INIT(0);
	184
	185	atomic_inc(&nmied_cpus);
	186	#endif
	187	/*
2ba53e37	188	* Only allow 1 cpu to proceed
1da177e4	189	*/
598c5aba	190	arch_spin_lock(&nmi_lock);
1da177e4 LT	191
	192	#ifdef REAL_NMI_SIGNAL
	193	/*
	194	* Wait up to 15 seconds for the other cpus to respond to the NMI.
	195	* If a cpu has not responded after 10 sec, send it 1 additional NMI.
	196	* This is for 2 reasons:
	197	* - sometimes a MMSC fail to NMI all cpus.
	198	* - on 512p SN0 system, the MMSC will only send NMIs to
	199	* half the cpus. Unfortunately, we don't know which cpus may be
	200	* NMIed - it depends on how the site chooses to configure.
	201	*
	202	* Note: it has been measure that it takes the MMSC up to 2.3 secs to
	203	* send NMIs to all cpus on a 256p system.
	204	*/
	205	for (i=0; i < 1500; i++) {
	206	for_each_online_node(node)
	207	if (NODEPDA(node)->dump_count == 0)
	208	break;
	209	if (node == MAX_NUMNODES)
	210	break;
	211	if (i == 1000) {
	212	for_each_online_node(node)
	213	if (NODEPDA(node)->dump_count == 0) {
0451fb2e	214	cpu = cpumask_first(cpumask_of_node(node));
1da177e4 LT	215	for (n=0; n < CNODE_NUM_CPUS(node); cpu++, n++) {
	216	CPUMASK_SETB(nmied_cpus, cpu);
	217	/*
	218	* cputonasid, cputoslice
	219	* needs kernel cpuid
	220	*/
	221	SEND_NMI((cputonasid(cpu)), (cputoslice(cpu)));
	222	}
	223	}
	224
	225	}
	226	udelay(10000);
	227	}
	228	#else
	229	while (atomic_read(&nmied_cpus) != num_online_cpus());
	230	#endif
	231
	232	/*
	233	* Save the nmi cpu registers for all cpu in the eframe format.
	234	*/
	235	nmi_eframes_save();
	236	LOCAL_HUB_S(NI_PORT_RESET, NPR_PORTRESET \| NPR_LOCALRESET);
	237	}