[linux-2.6-block.git] / arch / mips / lantiq / irq.c

/*
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 *
 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
 */

#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/irqdomain.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#include <asm/bootinfo.h>
#include <asm/irq_cpu.h>

#include <lantiq_soc.h>
#include <irq.h>

/* register definitions - internal irqs */
#define LTQ_ICU_IM0_ISR		0x0000
#define LTQ_ICU_IM0_IER		0x0008
#define LTQ_ICU_IM0_IOSR	0x0010
#define LTQ_ICU_IM0_IRSR	0x0018
#define LTQ_ICU_IM0_IMR		0x0020
#define LTQ_ICU_IM1_ISR		0x0028
#define LTQ_ICU_OFFSET		(LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)

/* register definitions - external irqs */
#define LTQ_EIU_EXIN_C		0x0000
#define LTQ_EIU_EXIN_INIC	0x0004
#define LTQ_EIU_EXIN_INC	0x0008
#define LTQ_EIU_EXIN_INEN	0x000C

/* number of external interrupts */
#define MAX_EIU			6

/* the performance counter */
#define LTQ_PERF_IRQ		(INT_NUM_IM4_IRL0 + 31)

/*
 * irqs generated by devices attached to the EBU need to be acked in
 * a special manner
 */
#define LTQ_ICU_EBU_IRQ		22

#define ltq_icu_w32(m, x, y)	ltq_w32((x), ltq_icu_membase[m] + (y))
#define ltq_icu_r32(m, x)	ltq_r32(ltq_icu_membase[m] + (x))

#define ltq_eiu_w32(x, y)	ltq_w32((x), ltq_eiu_membase + (y))
#define ltq_eiu_r32(x)		ltq_r32(ltq_eiu_membase + (x))

/* our 2 ipi interrupts for VSMP */
#define MIPS_CPU_IPI_RESCHED_IRQ	0
#define MIPS_CPU_IPI_CALL_IRQ		1

/* we have a cascade of 8 irqs */
#define MIPS_CPU_IRQ_CASCADE		8

#ifdef CONFIG_MIPS_MT_SMP
int gic_present;
#endif

static int exin_avail;
static struct resource ltq_eiu_irq[MAX_EIU];
static void __iomem *ltq_icu_membase[MAX_IM];
static void __iomem *ltq_eiu_membase;
static struct irq_domain *ltq_domain;
static int ltq_perfcount_irq;

int ltq_eiu_get_irq(int exin)
{
	if (exin < exin_avail)
		return ltq_eiu_irq[exin].start;
	return -1;
}

void ltq_disable_irq(struct irq_data *d)
{
	u32 ier = LTQ_ICU_IM0_IER;
	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
	int im = offset / INT_NUM_IM_OFFSET;

	offset %= INT_NUM_IM_OFFSET;
	ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
}

void ltq_mask_and_ack_irq(struct irq_data *d)
{
	u32 ier = LTQ_ICU_IM0_IER;
	u32 isr = LTQ_ICU_IM0_ISR;
	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
	int im = offset / INT_NUM_IM_OFFSET;

	offset %= INT_NUM_IM_OFFSET;
	ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
	ltq_icu_w32(im, BIT(offset), isr);
}

static void ltq_ack_irq(struct irq_data *d)
{
	u32 isr = LTQ_ICU_IM0_ISR;
	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
	int im = offset / INT_NUM_IM_OFFSET;

	offset %= INT_NUM_IM_OFFSET;
	ltq_icu_w32(im, BIT(offset), isr);
}

void ltq_enable_irq(struct irq_data *d)
{
	u32 ier = LTQ_ICU_IM0_IER;
	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
	int im = offset / INT_NUM_IM_OFFSET;

	offset %= INT_NUM_IM_OFFSET;
	ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier);
}

static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
{
	int i;

	for (i = 0; i < MAX_EIU; i++) {
		if (d->hwirq == ltq_eiu_irq[i].start) {
			int val = 0;
			int edge = 0;

			switch (type) {
			case IRQF_TRIGGER_NONE:
				break;
			case IRQF_TRIGGER_RISING:
				val = 1;
				edge = 1;
				break;
			case IRQF_TRIGGER_FALLING:
				val = 2;
				edge = 1;
				break;
			case IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING:
				val = 3;
				edge = 1;
				break;
			case IRQF_TRIGGER_HIGH:
				val = 5;
				break;
			case IRQF_TRIGGER_LOW:
				val = 6;
				break;
			default:
				pr_err("invalid type %d for irq %ld\n",
					type, d->hwirq);
				return -EINVAL;
			}

			if (edge)
				irq_set_handler(d->hwirq, handle_edge_irq);

			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
				(val << (i * 4)), LTQ_EIU_EXIN_C);
		}
	}

	return 0;
}

static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
{
	int i;

	ltq_enable_irq(d);
	for (i = 0; i < MAX_EIU; i++) {
		if (d->hwirq == ltq_eiu_irq[i].start) {
			/* by default we are low level triggered */
			ltq_eiu_settype(d, IRQF_TRIGGER_LOW);
			/* clear all pending */
			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INC) & ~BIT(i),
				LTQ_EIU_EXIN_INC);
			/* enable */
			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i),
				LTQ_EIU_EXIN_INEN);
			break;
		}
	}

	return 0;
}

static void ltq_shutdown_eiu_irq(struct irq_data *d)
{
	int i;

	ltq_disable_irq(d);
	for (i = 0; i < MAX_EIU; i++) {
		if (d->hwirq == ltq_eiu_irq[i].start) {
			/* disable */
			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
				LTQ_EIU_EXIN_INEN);
			break;
		}
	}
}

static struct irq_chip ltq_irq_type = {
	"icu",
	.irq_enable = ltq_enable_irq,
	.irq_disable = ltq_disable_irq,
	.irq_unmask = ltq_enable_irq,
	.irq_ack = ltq_ack_irq,
	.irq_mask = ltq_disable_irq,
	.irq_mask_ack = ltq_mask_and_ack_irq,
};

static struct irq_chip ltq_eiu_type = {
	"eiu",
	.irq_startup = ltq_startup_eiu_irq,
	.irq_shutdown = ltq_shutdown_eiu_irq,
	.irq_enable = ltq_enable_irq,
	.irq_disable = ltq_disable_irq,
	.irq_unmask = ltq_enable_irq,
	.irq_ack = ltq_ack_irq,
	.irq_mask = ltq_disable_irq,
	.irq_mask_ack = ltq_mask_and_ack_irq,
	.irq_set_type = ltq_eiu_settype,
};

static void ltq_hw_irqdispatch(int module)
{
	u32 irq;

	irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
	if (irq == 0)
		return;

	/*
	 * silicon bug causes only the msb set to 1 to be valid. all
	 * other bits might be bogus
	 */
	irq = __fls(irq);
	do_IRQ((int)irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module));

	/* if this is a EBU irq, we need to ack it or get a deadlock */
	if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
		ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
			LTQ_EBU_PCC_ISTAT);
}

#define DEFINE_HWx_IRQDISPATCH(x)					\
	static void ltq_hw ## x ## _irqdispatch(void)			\
	{								\
		ltq_hw_irqdispatch(x);					\
	}
DEFINE_HWx_IRQDISPATCH(0)
DEFINE_HWx_IRQDISPATCH(1)
DEFINE_HWx_IRQDISPATCH(2)
DEFINE_HWx_IRQDISPATCH(3)
DEFINE_HWx_IRQDISPATCH(4)

#if MIPS_CPU_TIMER_IRQ == 7
static void ltq_hw5_irqdispatch(void)
{
	do_IRQ(MIPS_CPU_TIMER_IRQ);
}
#else
DEFINE_HWx_IRQDISPATCH(5)
#endif

#ifdef CONFIG_MIPS_MT_SMP
void __init arch_init_ipiirq(int irq, struct irqaction *action)
{
	setup_irq(irq, action);
	irq_set_handler(irq, handle_percpu_irq);
}

static void ltq_sw0_irqdispatch(void)
{
	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
}

static void ltq_sw1_irqdispatch(void)
{
	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
}
static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
{
	scheduler_ipi();
	return IRQ_HANDLED;
}

static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
{
	generic_smp_call_function_interrupt();
	return IRQ_HANDLED;
}

static struct irqaction irq_resched = {
	.handler	= ipi_resched_interrupt,
	.flags		= IRQF_PERCPU,
	.name		= "IPI_resched"
};

static struct irqaction irq_call = {
	.handler	= ipi_call_interrupt,
	.flags		= IRQF_PERCPU,
	.name		= "IPI_call"
};
#endif

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
	unsigned int i;

	if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) {
		do_IRQ(MIPS_CPU_TIMER_IRQ);
		goto out;
	} else {
		for (i = 0; i < MAX_IM; i++) {
			if (pending & (CAUSEF_IP2 << i)) {
				ltq_hw_irqdispatch(i);
				goto out;
			}
		}
	}
	pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());

out:
	return;
}

static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
{
	struct irq_chip *chip = &ltq_irq_type;
	int i;

	if (hw < MIPS_CPU_IRQ_CASCADE)
		return 0;

	for (i = 0; i < exin_avail; i++)
		if (hw == ltq_eiu_irq[i].start)
			chip = &ltq_eiu_type;

	irq_set_chip_and_handler(hw, chip, handle_level_irq);

	return 0;
}

static const struct irq_domain_ops irq_domain_ops = {
	.xlate = irq_domain_xlate_onetwocell,
	.map = icu_map,
};

static struct irqaction cascade = {
	.handler = no_action,
	.name = "cascade",
};

int __init icu_of_init(struct device_node *node, struct device_node *parent)
{
	struct device_node *eiu_node;
	struct resource res;
	int i, ret;

	for (i = 0; i < MAX_IM; i++) {
		if (of_address_to_resource(node, i, &res))
			panic("Failed to get icu memory range");

		if (!request_mem_region(res.start, resource_size(&res),
					res.name))
			pr_err("Failed to request icu memory");

		ltq_icu_membase[i] = ioremap_nocache(res.start,
					resource_size(&res));
		if (!ltq_icu_membase[i])
			panic("Failed to remap icu memory");
	}

	/* turn off all irqs by default */
	for (i = 0; i < MAX_IM; i++) {
		/* make sure all irqs are turned off by default */
		ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER);
		/* clear all possibly pending interrupts */
		ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR);
	}

	mips_cpu_irq_init();

	for (i = 0; i < MAX_IM; i++)
		setup_irq(i + 2, &cascade);

	if (cpu_has_vint) {
		pr_info("Setting up vectored interrupts\n");
		set_vi_handler(2, ltq_hw0_irqdispatch);
		set_vi_handler(3, ltq_hw1_irqdispatch);
		set_vi_handler(4, ltq_hw2_irqdispatch);
		set_vi_handler(5, ltq_hw3_irqdispatch);
		set_vi_handler(6, ltq_hw4_irqdispatch);
		set_vi_handler(7, ltq_hw5_irqdispatch);
	}

	ltq_domain = irq_domain_add_linear(node,
		(MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
		&irq_domain_ops, 0);

#if defined(CONFIG_MIPS_MT_SMP)
	if (cpu_has_vint) {
		pr_info("Setting up IPI vectored interrupts\n");
		set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ltq_sw0_irqdispatch);
		set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ltq_sw1_irqdispatch);
	}
	arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ,
		&irq_resched);
	arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ, &irq_call);
#endif

#ifndef CONFIG_MIPS_MT_SMP
	set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
		IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
#else
	set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
		IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
#endif

	/* tell oprofile which irq to use */
	ltq_perfcount_irq = irq_create_mapping(ltq_domain, LTQ_PERF_IRQ);

	/*
	 * if the timer irq is not one of the mips irqs we need to
	 * create a mapping
	 */
	if (MIPS_CPU_TIMER_IRQ != 7)
		irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ);

	/* the external interrupts are optional and xway only */
	eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
	if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
		/* find out how many external irq sources we have */
		exin_avail = of_irq_count(eiu_node);

		if (exin_avail > MAX_EIU)
			exin_avail = MAX_EIU;

		ret = of_irq_to_resource_table(eiu_node,
						ltq_eiu_irq, exin_avail);
		if (ret != exin_avail)
			panic("failed to load external irq resources");

		if (!request_mem_region(res.start, resource_size(&res),
							res.name))
			pr_err("Failed to request eiu memory");

		ltq_eiu_membase = ioremap_nocache(res.start,
							resource_size(&res));
		if (!ltq_eiu_membase)
			panic("Failed to remap eiu memory");
	}

	return 0;
}

int get_c0_perfcount_int(void)
{
	return ltq_perfcount_irq;
}
EXPORT_SYMBOL_GPL(get_c0_perfcount_int);

unsigned int get_c0_compare_int(void)
{
	return MIPS_CPU_TIMER_IRQ;
}

static struct of_device_id __initdata of_irq_ids[] = {
	{ .compatible = "lantiq,icu", .data = icu_of_init },
	{},
};

void __init arch_init_irq(void)
{
	of_irq_init(of_irq_ids);
}
Commit	Line	Data
171bb2f1 JC	1	/*
	2	* This program is free software; you can redistribute it and/or modify it
	3	* under the terms of the GNU General Public License version 2 as published
	4	* by the Free Software Foundation.
	5	*
	6	* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
	7	* Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
	8	*/
	9
	10	#include <linux/interrupt.h>
	11	#include <linux/ioport.h>
3645da02 JC	12	#include <linux/sched.h>
	13	#include <linux/irqdomain.h>
	14	#include <linux/of_platform.h>
	15	#include <linux/of_address.h>
	16	#include <linux/of_irq.h>
171bb2f1 JC	17
	18	#include <asm/bootinfo.h>
	19	#include <asm/irq_cpu.h>
	20
	21	#include <lantiq_soc.h>
	22	#include <irq.h>
	23
3645da02	24	/* register definitions - internal irqs */
171bb2f1 JC	25	#define LTQ_ICU_IM0_ISR 0x0000
	26	#define LTQ_ICU_IM0_IER 0x0008
	27	#define LTQ_ICU_IM0_IOSR 0x0010
	28	#define LTQ_ICU_IM0_IRSR 0x0018
	29	#define LTQ_ICU_IM0_IMR 0x0020
	30	#define LTQ_ICU_IM1_ISR 0x0028
	31	#define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
	32
3645da02	33	/* register definitions - external irqs */
171bb2f1 JC	34	#define LTQ_EIU_EXIN_C 0x0000
171bb2f1 JC	35	#define LTQ_EIU_EXIN_INIC 0x0004
26365625	36	#define LTQ_EIU_EXIN_INC 0x0008
171bb2f1 JC	37	#define LTQ_EIU_EXIN_INEN 0x000C
171bb2f1 JC	38
26365625	39	/* number of external interrupts */
171bb2f1 JC	40	#define MAX_EIU 6
171bb2f1 JC	41
59c11579 JC	42	/* the performance counter */
	43	#define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31)
	44
3645da02 JC	45	/*
3645da02 JC	46	* irqs generated by devices attached to the EBU need to be acked in
171bb2f1 JC	47	* a special manner
	48	*/
	49	#define LTQ_ICU_EBU_IRQ 22
	50
61fa969f JC	51	#define ltq_icu_w32(m, x, y) ltq_w32((x), ltq_icu_membase[m] + (y))
61fa969f JC	52	#define ltq_icu_r32(m, x) ltq_r32(ltq_icu_membase[m] + (x))
171bb2f1 JC	53
	54	#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
	55	#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
	56
a8d096ef JC	57	/* our 2 ipi interrupts for VSMP */
	58	#define MIPS_CPU_IPI_RESCHED_IRQ 0
	59	#define MIPS_CPU_IPI_CALL_IRQ 1
	60
3645da02 JC	61	/* we have a cascade of 8 irqs */
	62	#define MIPS_CPU_IRQ_CASCADE 8
	63
b633648c	64	#ifdef CONFIG_MIPS_MT_SMP
a8d096ef JC	65	int gic_present;
	66	#endif
	67
3645da02	68	static int exin_avail;
26365625	69	static struct resource ltq_eiu_irq[MAX_EIU];
61fa969f	70	static void __iomem *ltq_icu_membase[MAX_IM];
171bb2f1	71	static void __iomem *ltq_eiu_membase;
c2c9c788	72	static struct irq_domain *ltq_domain;
a669efc4	73	static int ltq_perfcount_irq;
171bb2f1	74
26365625 JC	75	int ltq_eiu_get_irq(int exin)
	76	{
	77	if (exin < exin_avail)
	78	return ltq_eiu_irq[exin].start;
	79	return -1;
	80	}
	81
171bb2f1 JC	82	void ltq_disable_irq(struct irq_data *d)
	83	{
	84	u32 ier = LTQ_ICU_IM0_IER;
3645da02	85	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
61fa969f	86	int im = offset / INT_NUM_IM_OFFSET;
171bb2f1	87
3645da02	88	offset %= INT_NUM_IM_OFFSET;
61fa969f	89	ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
171bb2f1 JC	90	}
	91
	92	void ltq_mask_and_ack_irq(struct irq_data *d)
	93	{
	94	u32 ier = LTQ_ICU_IM0_IER;
	95	u32 isr = LTQ_ICU_IM0_ISR;
3645da02	96	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
61fa969f	97	int im = offset / INT_NUM_IM_OFFSET;
171bb2f1	98
3645da02	99	offset %= INT_NUM_IM_OFFSET;
61fa969f JC	100	ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
61fa969f JC	101	ltq_icu_w32(im, BIT(offset), isr);
171bb2f1 JC	102	}
	103
	104	static void ltq_ack_irq(struct irq_data *d)
	105	{
	106	u32 isr = LTQ_ICU_IM0_ISR;
3645da02	107	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
61fa969f	108	int im = offset / INT_NUM_IM_OFFSET;
171bb2f1	109
3645da02	110	offset %= INT_NUM_IM_OFFSET;
61fa969f	111	ltq_icu_w32(im, BIT(offset), isr);
171bb2f1 JC	112	}
	113
	114	void ltq_enable_irq(struct irq_data *d)
	115	{
	116	u32 ier = LTQ_ICU_IM0_IER;
3645da02	117	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
61fa969f	118	int im = offset / INT_NUM_IM_OFFSET;
171bb2f1	119
3645da02	120	offset %= INT_NUM_IM_OFFSET;
61fa969f	121	ltq_icu_w32(im, ltq_icu_r32(im, ier) \| BIT(offset), ier);
171bb2f1 JC	122	}
171bb2f1 JC	123
26365625 JC	124	static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
	125	{
	126	int i;
	127
	128	for (i = 0; i < MAX_EIU; i++) {
	129	if (d->hwirq == ltq_eiu_irq[i].start) {
	130	int val = 0;
	131	int edge = 0;
	132
	133	switch (type) {
	134	case IRQF_TRIGGER_NONE:
	135	break;
	136	case IRQF_TRIGGER_RISING:
	137	val = 1;
	138	edge = 1;
	139	break;
	140	case IRQF_TRIGGER_FALLING:
	141	val = 2;
	142	edge = 1;
	143	break;
	144	case IRQF_TRIGGER_RISING \| IRQF_TRIGGER_FALLING:
	145	val = 3;
	146	edge = 1;
	147	break;
	148	case IRQF_TRIGGER_HIGH:
	149	val = 5;
	150	break;
	151	case IRQF_TRIGGER_LOW:
	152	val = 6;
	153	break;
	154	default:
	155	pr_err("invalid type %d for irq %ld\n",
	156	type, d->hwirq);
	157	return -EINVAL;
	158	}
	159
	160	if (edge)
	161	irq_set_handler(d->hwirq, handle_edge_irq);
	162
	163	ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) \|
	164	(val << (i * 4)), LTQ_EIU_EXIN_C);
	165	}
	166	}
	167
	168	return 0;
	169	}
	170
171bb2f1 JC	171	static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
	172	{
	173	int i;
171bb2f1 JC	174
	175	ltq_enable_irq(d);
	176	for (i = 0; i < MAX_EIU; i++) {
26365625 JC	177	if (d->hwirq == ltq_eiu_irq[i].start) {
	178	/* by default we are low level triggered */
	179	ltq_eiu_settype(d, IRQF_TRIGGER_LOW);
171bb2f1	180	/* clear all pending */
26365625 JC	181	ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INC) & ~BIT(i),
26365625 JC	182	LTQ_EIU_EXIN_INC);
171bb2f1	183	/* enable */
3645da02	184	ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) \| BIT(i),
171bb2f1 JC	185	LTQ_EIU_EXIN_INEN);
	186	break;
	187	}
	188	}
	189
	190	return 0;
	191	}
	192
	193	static void ltq_shutdown_eiu_irq(struct irq_data *d)
	194	{
	195	int i;
171bb2f1 JC	196
	197	ltq_disable_irq(d);
	198	for (i = 0; i < MAX_EIU; i++) {
26365625	199	if (d->hwirq == ltq_eiu_irq[i].start) {
171bb2f1	200	/* disable */
3645da02	201	ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
171bb2f1 JC	202	LTQ_EIU_EXIN_INEN);
	203	break;
	204	}
	205	}
	206	}
	207
	208	static struct irq_chip ltq_irq_type = {
	209	"icu",
	210	.irq_enable = ltq_enable_irq,
	211	.irq_disable = ltq_disable_irq,
	212	.irq_unmask = ltq_enable_irq,
	213	.irq_ack = ltq_ack_irq,
	214	.irq_mask = ltq_disable_irq,
	215	.irq_mask_ack = ltq_mask_and_ack_irq,
	216	};
	217
	218	static struct irq_chip ltq_eiu_type = {
	219	"eiu",
	220	.irq_startup = ltq_startup_eiu_irq,
	221	.irq_shutdown = ltq_shutdown_eiu_irq,
	222	.irq_enable = ltq_enable_irq,
	223	.irq_disable = ltq_disable_irq,
	224	.irq_unmask = ltq_enable_irq,
	225	.irq_ack = ltq_ack_irq,
	226	.irq_mask = ltq_disable_irq,
	227	.irq_mask_ack = ltq_mask_and_ack_irq,
26365625	228	.irq_set_type = ltq_eiu_settype,
171bb2f1 JC	229	};
	230
	231	static void ltq_hw_irqdispatch(int module)
	232	{
	233	u32 irq;
	234
61fa969f	235	irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
171bb2f1 JC	236	if (irq == 0)
	237	return;
	238
3645da02 JC	239	/*
3645da02 JC	240	* silicon bug causes only the msb set to 1 to be valid. all
171bb2f1 JC	241	* other bits might be bogus
	242	*/
	243	irq = __fls(irq);
3645da02	244	do_IRQ((int)irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module));
171bb2f1 JC	245
171bb2f1 JC	246	/* if this is a EBU irq, we need to ack it or get a deadlock */
3645da02	247	if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
171bb2f1 JC	248	ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) \| 0x10,
	249	LTQ_EBU_PCC_ISTAT);
	250	}
	251
	252	#define DEFINE_HWx_IRQDISPATCH(x) \
	253	static void ltq_hw ## x ## _irqdispatch(void) \
	254	{ \
	255	ltq_hw_irqdispatch(x); \
	256	}
	257	DEFINE_HWx_IRQDISPATCH(0)
	258	DEFINE_HWx_IRQDISPATCH(1)
	259	DEFINE_HWx_IRQDISPATCH(2)
	260	DEFINE_HWx_IRQDISPATCH(3)
	261	DEFINE_HWx_IRQDISPATCH(4)
	262
c2c9c788	263	#if MIPS_CPU_TIMER_IRQ == 7
171bb2f1 JC	264	static void ltq_hw5_irqdispatch(void)
	265	{
	266	do_IRQ(MIPS_CPU_TIMER_IRQ);
	267	}
c2c9c788 JC	268	#else
	269	DEFINE_HWx_IRQDISPATCH(5)
	270	#endif
171bb2f1	271
a8d096ef JC	272	#ifdef CONFIG_MIPS_MT_SMP
	273	void __init arch_init_ipiirq(int irq, struct irqaction *action)
	274	{
	275	setup_irq(irq, action);
	276	irq_set_handler(irq, handle_percpu_irq);
	277	}
	278
	279	static void ltq_sw0_irqdispatch(void)
	280	{
	281	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
	282	}
	283
	284	static void ltq_sw1_irqdispatch(void)
	285	{
	286	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
	287	}
	288	static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
	289	{
	290	scheduler_ipi();
	291	return IRQ_HANDLED;
	292	}
	293
	294	static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
	295	{
4ace6139	296	generic_smp_call_function_interrupt();
a8d096ef JC	297	return IRQ_HANDLED;
	298	}
	299
	300	static struct irqaction irq_resched = {
	301	.handler = ipi_resched_interrupt,
	302	.flags = IRQF_PERCPU,
	303	.name = "IPI_resched"
	304	};
	305
	306	static struct irqaction irq_call = {
	307	.handler = ipi_call_interrupt,
	308	.flags = IRQF_PERCPU,
	309	.name = "IPI_call"
	310	};
	311	#endif
	312
171bb2f1 JC	313	asmlinkage void plat_irq_dispatch(void)
	314	{
	315	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
	316	unsigned int i;
	317
c2c9c788	318	if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) {
171bb2f1 JC	319	do_IRQ(MIPS_CPU_TIMER_IRQ);
	320	goto out;
	321	} else {
61fa969f	322	for (i = 0; i < MAX_IM; i++) {
171bb2f1 JC	323	if (pending & (CAUSEF_IP2 << i)) {
	324	ltq_hw_irqdispatch(i);
	325	goto out;
	326	}
	327	}
	328	}
	329	pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
	330
	331	out:
	332	return;
	333	}
	334
3645da02 JC	335	static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
	336	{
	337	struct irq_chip *chip = &ltq_irq_type;
	338	int i;
	339
9c1628b6 JC	340	if (hw < MIPS_CPU_IRQ_CASCADE)
	341	return 0;
	342
3645da02	343	for (i = 0; i < exin_avail; i++)
26365625	344	if (hw == ltq_eiu_irq[i].start)
3645da02 JC	345	chip = &ltq_eiu_type;
	346
	347	irq_set_chip_and_handler(hw, chip, handle_level_irq);
	348
	349	return 0;
	350	}
	351
	352	static const struct irq_domain_ops irq_domain_ops = {
	353	.xlate = irq_domain_xlate_onetwocell,
	354	.map = icu_map,
	355	};
	356
171bb2f1 JC	357	static struct irqaction cascade = {
171bb2f1 JC	358	.handler = no_action,
171bb2f1 JC	359	.name = "cascade",
	360	};
	361
3645da02	362	int __init icu_of_init(struct device_node node, struct device_node parent)
171bb2f1	363	{
3645da02 JC	364	struct device_node *eiu_node;
3645da02 JC	365	struct resource res;
26365625	366	int i, ret;
171bb2f1	367
61fa969f JC	368	for (i = 0; i < MAX_IM; i++) {
	369	if (of_address_to_resource(node, i, &res))
	370	panic("Failed to get icu memory range");
171bb2f1	371
6e807852 HM	372	if (!request_mem_region(res.start, resource_size(&res),
6e807852 HM	373	res.name))
61fa969f	374	pr_err("Failed to request icu memory");
171bb2f1	375
61fa969f JC	376	ltq_icu_membase[i] = ioremap_nocache(res.start,
	377	resource_size(&res));
	378	if (!ltq_icu_membase[i])
	379	panic("Failed to remap icu memory");
	380	}
171bb2f1	381
16f70b56	382	/* turn off all irqs by default */
61fa969f	383	for (i = 0; i < MAX_IM; i++) {
16f70b56	384	/* make sure all irqs are turned off by default */
61fa969f	385	ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER);
16f70b56	386	/* clear all possibly pending interrupts */
61fa969f	387	ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR);
16f70b56	388	}
171bb2f1 JC	389
	390	mips_cpu_irq_init();
	391
61fa969f JC	392	for (i = 0; i < MAX_IM; i++)
61fa969f JC	393	setup_irq(i + 2, &cascade);
171bb2f1 JC	394
	395	if (cpu_has_vint) {
	396	pr_info("Setting up vectored interrupts\n");
	397	set_vi_handler(2, ltq_hw0_irqdispatch);
	398	set_vi_handler(3, ltq_hw1_irqdispatch);
	399	set_vi_handler(4, ltq_hw2_irqdispatch);
	400	set_vi_handler(5, ltq_hw3_irqdispatch);
	401	set_vi_handler(6, ltq_hw4_irqdispatch);
	402	set_vi_handler(7, ltq_hw5_irqdispatch);
	403	}
	404
c2c9c788	405	ltq_domain = irq_domain_add_linear(node,
61fa969f	406	(MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
3645da02	407	&irq_domain_ops, 0);
171bb2f1	408
a8d096ef JC	409	#if defined(CONFIG_MIPS_MT_SMP)
	410	if (cpu_has_vint) {
	411	pr_info("Setting up IPI vectored interrupts\n");
	412	set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ltq_sw0_irqdispatch);
	413	set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ltq_sw1_irqdispatch);
	414	}
	415	arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ,
	416	&irq_resched);
	417	arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ, &irq_call);
	418	#endif
	419
b633648c	420	#ifndef CONFIG_MIPS_MT_SMP
171bb2f1 JC	421	set_c0_status(IE_IRQ0 \| IE_IRQ1 \| IE_IRQ2 \|
	422	IE_IRQ3 \| IE_IRQ4 \| IE_IRQ5);
	423	#else
	424	set_c0_status(IE_SW0 \| IE_SW1 \| IE_IRQ0 \| IE_IRQ1 \|
	425	IE_IRQ2 \| IE_IRQ3 \| IE_IRQ4 \| IE_IRQ5);
	426	#endif
59c11579 JC	427
59c11579 JC	428	/* tell oprofile which irq to use */
a669efc4	429	ltq_perfcount_irq = irq_create_mapping(ltq_domain, LTQ_PERF_IRQ);
c2c9c788 JC	430
	431	/*
	432	* if the timer irq is not one of the mips irqs we need to
	433	* create a mapping
	434	*/
	435	if (MIPS_CPU_TIMER_IRQ != 7)
	436	irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ);
	437
d32caf94 JC	438	/* the external interrupts are optional and xway only */
	439	eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
	440	if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
	441	/* find out how many external irq sources we have */
	442	exin_avail = of_irq_count(eiu_node);
	443
	444	if (exin_avail > MAX_EIU)
	445	exin_avail = MAX_EIU;
	446
	447	ret = of_irq_to_resource_table(eiu_node,
	448	ltq_eiu_irq, exin_avail);
	449	if (ret != exin_avail)
	450	panic("failed to load external irq resources");
	451
6e807852 HM	452	if (!request_mem_region(res.start, resource_size(&res),
6e807852 HM	453	res.name))
d32caf94 JC	454	pr_err("Failed to request eiu memory");
	455
	456	ltq_eiu_membase = ioremap_nocache(res.start,
	457	resource_size(&res));
	458	if (!ltq_eiu_membase)
	459	panic("Failed to remap eiu memory");
	460	}
	461
3645da02	462	return 0;
171bb2f1 JC	463	}
171bb2f1 JC	464
a669efc4 AB	465	int get_c0_perfcount_int(void)
	466	{
	467	return ltq_perfcount_irq;
	468	}
0cb0985f	469	EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
a669efc4	470
078a55fc	471	unsigned int get_c0_compare_int(void)
171bb2f1	472	{
c2c9c788	473	return MIPS_CPU_TIMER_IRQ;
171bb2f1	474	}
3645da02 JC	475
	476	static struct of_device_id __initdata of_irq_ids[] = {
	477	{ .compatible = "lantiq,icu", .data = icu_of_init },
	478	{},
	479	};
	480
	481	void __init arch_init_irq(void)
	482	{
	483	of_irq_init(of_irq_ids);
	484	}