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[linux-2.6-block.git] / arch / mips / kernel / traps.c
CommitLineData
1da177e4
LT		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004 Maciej W. Rozycki
13 */
14#include <linux/config.h>
15#include <linux/init.h>
16#include <linux/mm.h>
17#include <linux/module.h>
18#include <linux/sched.h>
19#include <linux/smp.h>
20#include <linux/smp_lock.h>
21#include <linux/spinlock.h>
22#include <linux/kallsyms.h>
23
24#include <asm/bootinfo.h>
25#include <asm/branch.h>
26#include <asm/break.h>
27#include <asm/cpu.h>
e50c0a8f 28#include <asm/dsp.h>
1da177e4
LT		 29#include <asm/fpu.h>
30#include <asm/module.h>
31#include <asm/pgtable.h>
32#include <asm/ptrace.h>
33#include <asm/sections.h>
34#include <asm/system.h>
35#include <asm/tlbdebug.h>
36#include <asm/traps.h>
37#include <asm/uaccess.h>
38#include <asm/mmu_context.h>
39#include <asm/watch.h>
40#include <asm/types.h>
41
42extern asmlinkage void handle_tlbm(void);
43extern asmlinkage void handle_tlbl(void);
44extern asmlinkage void handle_tlbs(void);
45extern asmlinkage void handle_adel(void);
46extern asmlinkage void handle_ades(void);
47extern asmlinkage void handle_ibe(void);
48extern asmlinkage void handle_dbe(void);
49extern asmlinkage void handle_sys(void);
50extern asmlinkage void handle_bp(void);
51extern asmlinkage void handle_ri(void);
52extern asmlinkage void handle_cpu(void);
53extern asmlinkage void handle_ov(void);
54extern asmlinkage void handle_tr(void);
55extern asmlinkage void handle_fpe(void);
56extern asmlinkage void handle_mdmx(void);
57extern asmlinkage void handle_watch(void);
e50c0a8f 58extern asmlinkage void handle_dsp(void);
1da177e4
LT		 59extern asmlinkage void handle_mcheck(void);
60extern asmlinkage void handle_reserved(void);
61
62extern int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp,
63 struct mips_fpu_soft_struct *ctx);
64
65void (*board_be_init)(void);
66int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
67
68/*
69 * These constant is for searching for possible module text segments.
70 * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
71 */
72#define MODULE_RANGE (8*1024*1024)
73
74/*
75 * This routine abuses get_user()/put_user() to reference pointers
76 * with at least a bit of error checking ...
77 */
78void show_stack(struct task_struct *task, unsigned long *sp)
79{
80 const int field = 2 * sizeof(unsigned long);
81 long stackdata;
82 int i;
83
84 if (!sp) {
85 if (task && task != current)
86 sp = (unsigned long *) task->thread.reg29;
87 else
88 sp = (unsigned long *) &sp;
89 }
90
91 printk("Stack :");
92 i = 0;
93 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
94 if (i && ((i % (64 / field)) == 0))
95 printk("\n ");
96 if (i > 39) {
97 printk(" ...");
98 break;
99 }
100
101 if (__get_user(stackdata, sp++)) {
102 printk(" (Bad stack address)");
103 break;
104 }
105
106 printk(" %0*lx", field, stackdata);
107 i++;
108 }
109 printk("\n");
110}
111
112void show_trace(struct task_struct *task, unsigned long *stack)
113{
114 const int field = 2 * sizeof(unsigned long);
115 unsigned long addr;
116
117 if (!stack) {
118 if (task && task != current)
119 stack = (unsigned long *) task->thread.reg29;
120 else
121 stack = (unsigned long *) &stack;
122 }
123
124 printk("Call Trace:");
125#ifdef CONFIG_KALLSYMS
126 printk("\n");
127#endif
128 while (!kstack_end(stack)) {
129 addr = *stack++;
130 if (__kernel_text_address(addr)) {
131 printk(" [<%0*lx>] ", field, addr);
132 print_symbol("%s\n", addr);
133 }
134 }
135 printk("\n");
136}
137
138/*
139 * The architecture-independent dump_stack generator
140 */
141void dump_stack(void)
142{
143 unsigned long stack;
144
145 show_trace(current, &stack);
146}
147
148EXPORT_SYMBOL(dump_stack);
149
150void show_code(unsigned int *pc)
151{
152 long i;
153
154 printk("\nCode:");
155
156 for(i = -3 ; i < 6 ; i++) {
157 unsigned int insn;
158 if (__get_user(insn, pc + i)) {
159 printk(" (Bad address in epc)\n");
160 break;
161 }
162 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
163 }
164}
165
166void show_regs(struct pt_regs *regs)
167{
168 const int field = 2 * sizeof(unsigned long);
169 unsigned int cause = regs->cp0_cause;
170 int i;
171
172 printk("Cpu %d\n", smp_processor_id());
173
174 /*
175 * Saved main processor registers
176 */
177 for (i = 0; i < 32; ) {
178 if ((i % 4) == 0)
179 printk("$%2d :", i);
180 if (i == 0)
181 printk(" %0*lx", field, 0UL);
182 else if (i == 26 || i == 27)
183 printk(" %*s", field, "");
184 else
185 printk(" %0*lx", field, regs->regs[i]);
186
187 i++;
188 if ((i % 4) == 0)
189 printk("\n");
190 }
191
192 printk("Hi : %0*lx\n", field, regs->hi);
193 printk("Lo : %0*lx\n", field, regs->lo);
194
195 /*
196 * Saved cp0 registers
197 */
198 printk("epc : %0*lx ", field, regs->cp0_epc);
199 print_symbol("%s ", regs->cp0_epc);
200 printk(" %s\n", print_tainted());
201 printk("ra : %0*lx ", field, regs->regs[31]);
202 print_symbol("%s\n", regs->regs[31]);
203
204 printk("Status: %08x ", (uint32_t) regs->cp0_status);
205
206 if (regs->cp0_status & ST0_KX)
207 printk("KX ");
208 if (regs->cp0_status & ST0_SX)
209 printk("SX ");
210 if (regs->cp0_status & ST0_UX)
211 printk("UX ");
212 switch (regs->cp0_status & ST0_KSU) {
213 case KSU_USER:
214 printk("USER ");
215 break;
216 case KSU_SUPERVISOR:
217 printk("SUPERVISOR ");
218 break;
219 case KSU_KERNEL:
220 printk("KERNEL ");
221 break;
222 default:
223 printk("BAD_MODE ");
224 break;
225 }
226 if (regs->cp0_status & ST0_ERL)
227 printk("ERL ");
228 if (regs->cp0_status & ST0_EXL)
229 printk("EXL ");
230 if (regs->cp0_status & ST0_IE)
231 printk("IE ");
232 printk("\n");
233
234 printk("Cause : %08x\n", cause);
235
236 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
237 if (1 <= cause && cause <= 5)
238 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
239
240 printk("PrId : %08x\n", read_c0_prid());
241}
242
243void show_registers(struct pt_regs *regs)
244{
245 show_regs(regs);
246 print_modules();
247 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
248 current->comm, current->pid, current_thread_info(), current);
249 show_stack(current, (long *) regs->regs[29]);
250 show_trace(current, (long *) regs->regs[29]);
251 show_code((unsigned int *) regs->cp0_epc);
252 printk("\n");
253}
254
255static DEFINE_SPINLOCK(die_lock);
256
257NORET_TYPE void __die(const char * str, struct pt_regs * regs,
258 const char * file, const char * func, unsigned long line)
259{
260 static int die_counter;
261
262 console_verbose();
263 spin_lock_irq(&die_lock);
264 printk("%s", str);
265 if (file && func)
266 printk(" in %s:%s, line %ld", file, func, line);
267 printk("[#%d]:\n", ++die_counter);
268 show_registers(regs);
269 spin_unlock_irq(&die_lock);
270 do_exit(SIGSEGV);
271}
272
273void __die_if_kernel(const char * str, struct pt_regs * regs,
274 const char * file, const char * func, unsigned long line)
275{
276 if (!user_mode(regs))
277 __die(str, regs, file, func, line);
278}
279
280extern const struct exception_table_entry __start___dbe_table[];
281extern const struct exception_table_entry __stop___dbe_table[];
282
283void __declare_dbe_table(void)
284{
285 __asm__ __volatile__(
286 ".section\t__dbe_table,\"a\"\n\t"
287 ".previous"
288 );
289}
290
291/* Given an address, look for it in the exception tables. */
292static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
293{
294 const struct exception_table_entry *e;
295
296 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
297 if (!e)
298 e = search_module_dbetables(addr);
299 return e;
300}
301
302asmlinkage void do_be(struct pt_regs *regs)
303{
304 const int field = 2 * sizeof(unsigned long);
305 const struct exception_table_entry *fixup = NULL;
306 int data = regs->cp0_cause & 4;
307 int action = MIPS_BE_FATAL;
308
309 /* XXX For now. Fixme, this searches the wrong table ... */
310 if (data && !user_mode(regs))
311 fixup = search_dbe_tables(exception_epc(regs));
312
313 if (fixup)
314 action = MIPS_BE_FIXUP;
315
316 if (board_be_handler)
317 action = board_be_handler(regs, fixup != 0);
318
319 switch (action) {
320 case MIPS_BE_DISCARD:
321 return;
322 case MIPS_BE_FIXUP:
323 if (fixup) {
324 regs->cp0_epc = fixup->nextinsn;
325 return;
326 }
327 break;
328 default:
329 break;
330 }
331
332 /*
333 * Assume it would be too dangerous to continue ...
334 */
335 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
336 data ? "Data" : "Instruction",
337 field, regs->cp0_epc, field, regs->regs[31]);
338 die_if_kernel("Oops", regs);
339 force_sig(SIGBUS, current);
340}
341
342static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
343{
fe00f943 344 unsigned int __user *epc;
1da177e4 345
fe00f943 346 epc = (unsigned int __user *) regs->cp0_epc +
1da177e4
LT		 347 ((regs->cp0_cause & CAUSEF_BD) != 0);
348 if (!get_user(*opcode, epc))
349 return 0;
350
351 force_sig(SIGSEGV, current);
352 return 1;
353}
354
355/*
356 * ll/sc emulation
357 */
358
359#define OPCODE 0xfc000000
360#define BASE 0x03e00000
361#define RT 0x001f0000
362#define OFFSET 0x0000ffff
363#define LL 0xc0000000
364#define SC 0xe0000000
3c37026d
RB		 365#define SPEC3 0x7c000000
366#define RD 0x0000f800
367#define FUNC 0x0000003f
368#define RDHWR 0x0000003b
1da177e4
LT		 369
370/*
371 * The ll_bit is cleared by r*_switch.S
372 */
373
374unsigned long ll_bit;
375
376static struct task_struct *ll_task = NULL;
377
378static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
379{
fe00f943 380 unsigned long value, __user *vaddr;
1da177e4
LT		 381 long offset;
382 int signal = 0;
383
384 /*
385 * analyse the ll instruction that just caused a ri exception
386 * and put the referenced address to addr.
387 */
388
389 /* sign extend offset */
390 offset = opcode & OFFSET;
391 offset <<= 16;
392 offset >>= 16;
393
fe00f943
RB		 394 vaddr = (unsigned long __user *)
395 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
1da177e4
LT		 396
397 if ((unsigned long)vaddr & 3) {
398 signal = SIGBUS;
399 goto sig;
400 }
401 if (get_user(value, vaddr)) {
402 signal = SIGSEGV;
403 goto sig;
404 }
405
406 preempt_disable();
407
408 if (ll_task == NULL || ll_task == current) {
409 ll_bit = 1;
410 } else {
411 ll_bit = 0;
412 }
413 ll_task = current;
414
415 preempt_enable();
416
6dd04688
RB		 417 compute_return_epc(regs);
418
1da177e4
LT		 419 regs->regs[(opcode & RT) >> 16] = value;
420
1da177e4
LT		 421 return;
422
423sig:
424 force_sig(signal, current);
425}
426
427static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
428{
fe00f943
RB		 429 unsigned long __user *vaddr;
430 unsigned long reg;
1da177e4
LT		 431 long offset;
432 int signal = 0;
433
434 /*
435 * analyse the sc instruction that just caused a ri exception
436 * and put the referenced address to addr.
437 */
438
439 /* sign extend offset */
440 offset = opcode & OFFSET;
441 offset <<= 16;
442 offset >>= 16;
443
fe00f943
RB		 444 vaddr = (unsigned long __user *)
445 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
1da177e4
LT		 446 reg = (opcode & RT) >> 16;
447
448 if ((unsigned long)vaddr & 3) {
449 signal = SIGBUS;
450 goto sig;
451 }
452
453 preempt_disable();
454
455 if (ll_bit == 0 || ll_task != current) {
05b8042a 456 compute_return_epc(regs);
1da177e4
LT		 457 regs->regs[reg] = 0;
458 preempt_enable();
1da177e4
LT		 459 return;
460 }
461
462 preempt_enable();
463
464 if (put_user(regs->regs[reg], vaddr)) {
465 signal = SIGSEGV;
466 goto sig;
467 }
468
6dd04688 469 compute_return_epc(regs);
1da177e4
LT		 470 regs->regs[reg] = 1;
471
1da177e4
LT		 472 return;
473
474sig:
475 force_sig(signal, current);
476}
477
478/*
479 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
480 * opcodes are supposed to result in coprocessor unusable exceptions if
481 * executed on ll/sc-less processors. That's the theory. In practice a
482 * few processors such as NEC's VR4100 throw reserved instruction exceptions
483 * instead, so we're doing the emulation thing in both exception handlers.
484 */
485static inline int simulate_llsc(struct pt_regs *regs)
486{
487 unsigned int opcode;
488
489 if (unlikely(get_insn_opcode(regs, &opcode)))
490 return -EFAULT;
491
492 if ((opcode & OPCODE) == LL) {
493 simulate_ll(regs, opcode);
494 return 0;
495 }
496 if ((opcode & OPCODE) == SC) {
497 simulate_sc(regs, opcode);
498 return 0;
499 }
500
501 return -EFAULT; /* Strange things going on ... */
502}
503
3c37026d
RB		 504/*
505 * Simulate trapping 'rdhwr' instructions to provide user accessible
506 * registers not implemented in hardware. The only current use of this
507 * is the thread area pointer.
508 */
509static inline int simulate_rdhwr(struct pt_regs *regs)
510{
511 struct thread_info *ti = current->thread_info;
512 unsigned int opcode;
513
514 if (unlikely(get_insn_opcode(regs, &opcode)))
515 return -EFAULT;
516
517 if (unlikely(compute_return_epc(regs)))
518 return -EFAULT;
519
520 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
521 int rd = (opcode & RD) >> 11;
522 int rt = (opcode & RT) >> 16;
523 switch (rd) {
524 case 29:
525 regs->regs[rt] = ti->tp_value;
526 break;
527 default:
528 return -EFAULT;
529 }
530 }
531
532 return 0;
533}
534
1da177e4
LT		 535asmlinkage void do_ov(struct pt_regs *regs)
536{
537 siginfo_t info;
538
539 info.si_code = FPE_INTOVF;
540 info.si_signo = SIGFPE;
541 info.si_errno = 0;
fe00f943 542 info.si_addr = (void __user *) regs->cp0_epc;
1da177e4
LT		 543 force_sig_info(SIGFPE, &info, current);
544}
545
546/*
547 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
548 */
549asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
550{
551 if (fcr31 & FPU_CSR_UNI_X) {
552 int sig;
553
554 preempt_disable();
555
cd21dfcf
RB		 556#ifdef CONFIG_PREEMPT
557 if (!is_fpu_owner()) {
558 /* We might lose fpu before disabling preempt... */
559 own_fpu();
560 BUG_ON(!used_math());
561 restore_fp(current);
562 }
563#endif
1da177e4
LT		 564 /*
565 * Unimplemented operation exception. If we've got the full
566 * software emulator on-board, let's use it...
567 *
568 * Force FPU to dump state into task/thread context. We're
569 * moving a lot of data here for what is probably a single
570 * instruction, but the alternative is to pre-decode the FP
571 * register operands before invoking the emulator, which seems
572 * a bit extreme for what should be an infrequent event.
573 */
574 save_fp(current);
cd21dfcf
RB		 575 /* Ensure 'resume' not overwrite saved fp context again. */
576 lose_fpu();
577
578 preempt_enable();
1da177e4
LT		 579
580 /* Run the emulator */
581 sig = fpu_emulator_cop1Handler (0, regs,
582 &current->thread.fpu.soft);
583
cd21dfcf
RB		 584 preempt_disable();
585
586 own_fpu(); /* Using the FPU again. */
1da177e4
LT		 587 /*
588 * We can't allow the emulated instruction to leave any of
589 * the cause bit set in $fcr31.
590 */
591 current->thread.fpu.soft.fcr31 &= ~FPU_CSR_ALL_X;
592
593 /* Restore the hardware register state */
594 restore_fp(current);
595
596 preempt_enable();
597
598 /* If something went wrong, signal */
599 if (sig)
600 force_sig(sig, current);
601
602 return;
603 }
604
605 force_sig(SIGFPE, current);
606}
607
608asmlinkage void do_bp(struct pt_regs *regs)
609{
610 unsigned int opcode, bcode;
611 siginfo_t info;
612
613 die_if_kernel("Break instruction in kernel code", regs);
614
615 if (get_insn_opcode(regs, &opcode))
616 return;
617
618 /*
619 * There is the ancient bug in the MIPS assemblers that the break
620 * code starts left to bit 16 instead to bit 6 in the opcode.
621 * Gas is bug-compatible, but not always, grrr...
622 * We handle both cases with a simple heuristics. --macro
623 */
624 bcode = ((opcode >> 6) & ((1 << 20) - 1));
625 if (bcode < (1 << 10))
626 bcode <<= 10;
627
628 /*
629 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
630 * insns, even for break codes that indicate arithmetic failures.
631 * Weird ...)
632 * But should we continue the brokenness??? --macro
633 */
634 switch (bcode) {
635 case BRK_OVERFLOW << 10:
636 case BRK_DIVZERO << 10:
637 if (bcode == (BRK_DIVZERO << 10))
638 info.si_code = FPE_INTDIV;
639 else
640 info.si_code = FPE_INTOVF;
641 info.si_signo = SIGFPE;
642 info.si_errno = 0;
fe00f943 643 info.si_addr = (void __user *) regs->cp0_epc;
1da177e4
LT		 644 force_sig_info(SIGFPE, &info, current);
645 break;
646 default:
647 force_sig(SIGTRAP, current);
648 }
649}
650
651asmlinkage void do_tr(struct pt_regs *regs)
652{
653 unsigned int opcode, tcode = 0;
654 siginfo_t info;
655
656 die_if_kernel("Trap instruction in kernel code", regs);
657
658 if (get_insn_opcode(regs, &opcode))
659 return;
660
661 /* Immediate versions don't provide a code. */
662 if (!(opcode & OPCODE))
663 tcode = ((opcode >> 6) & ((1 << 10) - 1));
664
665 /*
666 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
667 * insns, even for trap codes that indicate arithmetic failures.
668 * Weird ...)
669 * But should we continue the brokenness??? --macro
670 */
671 switch (tcode) {
672 case BRK_OVERFLOW:
673 case BRK_DIVZERO:
674 if (tcode == BRK_DIVZERO)
675 info.si_code = FPE_INTDIV;
676 else
677 info.si_code = FPE_INTOVF;
678 info.si_signo = SIGFPE;
679 info.si_errno = 0;
fe00f943 680 info.si_addr = (void __user *) regs->cp0_epc;
1da177e4
LT		 681 force_sig_info(SIGFPE, &info, current);
682 break;
683 default:
684 force_sig(SIGTRAP, current);
685 }
686}
687
688asmlinkage void do_ri(struct pt_regs *regs)
689{
690 die_if_kernel("Reserved instruction in kernel code", regs);
691
692 if (!cpu_has_llsc)
693 if (!simulate_llsc(regs))
694 return;
695
3c37026d
RB		 696 if (!simulate_rdhwr(regs))
697 return;
698
1da177e4
LT		 699 force_sig(SIGILL, current);
700}
701
702asmlinkage void do_cpu(struct pt_regs *regs)
703{
704 unsigned int cpid;
705
706 die_if_kernel("do_cpu invoked from kernel context!", regs);
707
708 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
709
710 switch (cpid) {
711 case 0:
3c37026d
RB		 712 if (!cpu_has_llsc)
713 if (!simulate_llsc(regs))
714 return;
1da177e4 715
3c37026d 716 if (!simulate_rdhwr(regs))
1da177e4 717 return;
3c37026d 718
1da177e4
LT		 719 break;
720
721 case 1:
722 preempt_disable();
723
724 own_fpu();
725 if (used_math()) { /* Using the FPU again. */
726 restore_fp(current);
727 } else { /* First time FPU user. */
728 init_fpu();
729 set_used_math();
730 }
731
cd21dfcf
RB		 732 preempt_enable();
733
1da177e4
LT		 734 if (!cpu_has_fpu) {
735 int sig = fpu_emulator_cop1Handler(0, regs,
736 &current->thread.fpu.soft);
737 if (sig)
738 force_sig(sig, current);
739 }
740
1da177e4
LT		 741 return;
742
743 case 2:
744 case 3:
745 break;
746 }
747
748 force_sig(SIGILL, current);
749}
750
751asmlinkage void do_mdmx(struct pt_regs *regs)
752{
753 force_sig(SIGILL, current);
754}
755
756asmlinkage void do_watch(struct pt_regs *regs)
757{
758 /*
759 * We use the watch exception where available to detect stack
760 * overflows.
761 */
762 dump_tlb_all();
763 show_regs(regs);
764 panic("Caught WATCH exception - probably caused by stack overflow.");
765}
766
767asmlinkage void do_mcheck(struct pt_regs *regs)
768{
769 show_regs(regs);
770 dump_tlb_all();
771 /*
772 * Some chips may have other causes of machine check (e.g. SB1
773 * graduation timer)
774 */
775 panic("Caught Machine Check exception - %scaused by multiple "
776 "matching entries in the TLB.",
777 (regs->cp0_status & ST0_TS) ? "" : "not ");
778}
779
e50c0a8f
RB		 780asmlinkage void do_dsp(struct pt_regs *regs)
781{
782 if (cpu_has_dsp)
783 panic("Unexpected DSP exception\n");
784
785 force_sig(SIGILL, current);
786}
787
1da177e4
LT		 788asmlinkage void do_reserved(struct pt_regs *regs)
789{
790 /*
791 * Game over - no way to handle this if it ever occurs. Most probably
792 * caused by a new unknown cpu type or after another deadly
793 * hard/software error.
794 */
795 show_regs(regs);
796 panic("Caught reserved exception %ld - should not happen.",
797 (regs->cp0_cause & 0x7f) >> 2);
798}
799
800/*
801 * Some MIPS CPUs can enable/disable for cache parity detection, but do
802 * it different ways.
803 */
804static inline void parity_protection_init(void)
805{
806 switch (current_cpu_data.cputype) {
807 case CPU_24K:
1da177e4 808 case CPU_5KC:
14f18b7f
RB		 809 write_c0_ecc(0x80000000);
810 back_to_back_c0_hazard();
811 /* Set the PE bit (bit 31) in the c0_errctl register. */
812 printk(KERN_INFO "Cache parity protection %sabled\n",
813 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1da177e4
LT		 814 break;
815 case CPU_20KC:
816 case CPU_25KF:
817 /* Clear the DE bit (bit 16) in the c0_status register. */
818 printk(KERN_INFO "Enable cache parity protection for "
819 "MIPS 20KC/25KF CPUs.\n");
820 clear_c0_status(ST0_DE);
821 break;
822 default:
823 break;
824 }
825}
826
827asmlinkage void cache_parity_error(void)
828{
829 const int field = 2 * sizeof(unsigned long);
830 unsigned int reg_val;
831
832 /* For the moment, report the problem and hang. */
833 printk("Cache error exception:\n");
834 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
835 reg_val = read_c0_cacheerr();
836 printk("c0_cacheerr == %08x\n", reg_val);
837
838 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
839 reg_val & (1<<30) ? "secondary" : "primary",
840 reg_val & (1<<31) ? "data" : "insn");
841 printk("Error bits: %s%s%s%s%s%s%s\n",
842 reg_val & (1<<29) ? "ED " : "",
843 reg_val & (1<<28) ? "ET " : "",
844 reg_val & (1<<26) ? "EE " : "",
845 reg_val & (1<<25) ? "EB " : "",
846 reg_val & (1<<24) ? "EI " : "",
847 reg_val & (1<<23) ? "E1 " : "",
848 reg_val & (1<<22) ? "E0 " : "");
849 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
850
851#if defined(CONFIG_CPU_MIPS32) || defined (CONFIG_CPU_MIPS64)
852 if (reg_val & (1<<22))
853 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
854
855 if (reg_val & (1<<23))
856 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
857#endif
858
859 panic("Can't handle the cache error!");
860}
861
862/*
863 * SDBBP EJTAG debug exception handler.
864 * We skip the instruction and return to the next instruction.
865 */
866void ejtag_exception_handler(struct pt_regs *regs)
867{
868 const int field = 2 * sizeof(unsigned long);
869 unsigned long depc, old_epc;
870 unsigned int debug;
871
872 printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
873 depc = read_c0_depc();
874 debug = read_c0_debug();
875 printk("c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
876 if (debug & 0x80000000) {
877 /*
878 * In branch delay slot.
879 * We cheat a little bit here and use EPC to calculate the
880 * debug return address (DEPC). EPC is restored after the
881 * calculation.
882 */
883 old_epc = regs->cp0_epc;
884 regs->cp0_epc = depc;
885 __compute_return_epc(regs);
886 depc = regs->cp0_epc;
887 regs->cp0_epc = old_epc;
888 } else
889 depc += 4;
890 write_c0_depc(depc);
891
892#if 0
893 printk("\n\n----- Enable EJTAG single stepping ----\n\n");
894 write_c0_debug(debug | 0x100);
895#endif
896}
897
898/*
899 * NMI exception handler.
900 */
901void nmi_exception_handler(struct pt_regs *regs)
902{
903 printk("NMI taken!!!!\n");
904 die("NMI", regs);
905 while(1) ;
906}
907
908unsigned long exception_handlers[32];
909
910/*
911 * As a side effect of the way this is implemented we're limited
912 * to interrupt handlers in the address range from
913 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
914 */
915void *set_except_vector(int n, void *addr)
916{
917 unsigned long handler = (unsigned long) addr;
918 unsigned long old_handler = exception_handlers[n];
919
920 exception_handlers[n] = handler;
921 if (n == 0 && cpu_has_divec) {
922 *(volatile u32 *)(CAC_BASE + 0x200) = 0x08000000 |
923 (0x03ffffff & (handler >> 2));
924 flush_icache_range(CAC_BASE + 0x200, CAC_BASE + 0x204);
925 }
926 return (void *)old_handler;
927}
928
929/*
930 * This is used by native signal handling
931 */
932asmlinkage int (*save_fp_context)(struct sigcontext *sc);
933asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
934
935extern asmlinkage int _save_fp_context(struct sigcontext *sc);
936extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
937
938extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
939extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
940
941static inline void signal_init(void)
942{
943 if (cpu_has_fpu) {
944 save_fp_context = _save_fp_context;
945 restore_fp_context = _restore_fp_context;
946 } else {
947 save_fp_context = fpu_emulator_save_context;
948 restore_fp_context = fpu_emulator_restore_context;
949 }
950}
951
952#ifdef CONFIG_MIPS32_COMPAT
953
954/*
955 * This is used by 32-bit signal stuff on the 64-bit kernel
956 */
957asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
958asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
959
960extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
961extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
962
963extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
964extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
965
966static inline void signal32_init(void)
967{
968 if (cpu_has_fpu) {
969 save_fp_context32 = _save_fp_context32;
970 restore_fp_context32 = _restore_fp_context32;
971 } else {
972 save_fp_context32 = fpu_emulator_save_context32;
973 restore_fp_context32 = fpu_emulator_restore_context32;
974 }
975}
976#endif
977
978extern void cpu_cache_init(void);
979extern void tlb_init(void);
980
981void __init per_cpu_trap_init(void)
982{
983 unsigned int cpu = smp_processor_id();
984 unsigned int status_set = ST0_CU0;
985
986 /*
987 * Disable coprocessors and select 32-bit or 64-bit addressing
988 * and the 16/32 or 32/32 FPR register model. Reset the BEV
989 * flag that some firmware may have left set and the TS bit (for
990 * IP27). Set XX for ISA IV code to work.
991 */
875d43e7 992#ifdef CONFIG_64BIT
1da177e4
LT		 993 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
994#endif
995 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
996 status_set |= ST0_XX;
e50c0a8f 997 change_c0_status(ST0_CU|ST0_MX|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1da177e4
LT		 998 status_set);
999
e50c0a8f
RB		 1000 if (cpu_has_dsp)
1001 set_c0_status(ST0_MX);
1002
1da177e4
LT		 1003 /*
1004 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
1005 * interrupt processing overhead. Use it where available.
1006 */
1007 if (cpu_has_divec)
1008 set_c0_cause(CAUSEF_IV);
1009
1010 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1011 TLBMISS_HANDLER_SETUP();
1012
1013 atomic_inc(&init_mm.mm_count);
1014 current->active_mm = &init_mm;
1015 BUG_ON(current->mm);
1016 enter_lazy_tlb(&init_mm, current);
1017
1018 cpu_cache_init();
1019 tlb_init();
1020}
1021
1022void __init trap_init(void)
1023{
1024 extern char except_vec3_generic, except_vec3_r4000;
1025 extern char except_vec_ejtag_debug;
1026 extern char except_vec4;
1027 unsigned long i;
1028
1029 per_cpu_trap_init();
1030
1031 /*
1032 * Copy the generic exception handlers to their final destination.
1033 * This will be overriden later as suitable for a particular
1034 * configuration.
1035 */
1036 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1037
1038 /*
1039 * Setup default vectors
1040 */
1041 for (i = 0; i <= 31; i++)
1042 set_except_vector(i, handle_reserved);
1043
1044 /*
1045 * Copy the EJTAG debug exception vector handler code to it's final
1046 * destination.
1047 */
1048 if (cpu_has_ejtag)
1049 memcpy((void *)(CAC_BASE + 0x300), &except_vec_ejtag_debug, 0x80);
1050
1051 /*
1052 * Only some CPUs have the watch exceptions.
1053 */
1054 if (cpu_has_watch)
1055 set_except_vector(23, handle_watch);
1056
1057 /*
1058 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
1059 * interrupt processing overhead. Use it where available.
1060 */
1061 if (cpu_has_divec)
1062 memcpy((void *)(CAC_BASE + 0x200), &except_vec4, 0x8);
1063
1064 /*
1065 * Some CPUs can enable/disable for cache parity detection, but does
1066 * it different ways.
1067 */
1068 parity_protection_init();
1069
1070 /*
1071 * The Data Bus Errors / Instruction Bus Errors are signaled
1072 * by external hardware. Therefore these two exceptions
1073 * may have board specific handlers.
1074 */
1075 if (board_be_init)
1076 board_be_init();
1077
1078 set_except_vector(1, handle_tlbm);
1079 set_except_vector(2, handle_tlbl);
1080 set_except_vector(3, handle_tlbs);
1081
1082 set_except_vector(4, handle_adel);
1083 set_except_vector(5, handle_ades);
1084
1085 set_except_vector(6, handle_ibe);
1086 set_except_vector(7, handle_dbe);
1087
1088 set_except_vector(8, handle_sys);
1089 set_except_vector(9, handle_bp);
1090 set_except_vector(10, handle_ri);
1091 set_except_vector(11, handle_cpu);
1092 set_except_vector(12, handle_ov);
1093 set_except_vector(13, handle_tr);
1da177e4
LT		 1094
1095 if (current_cpu_data.cputype == CPU_R6000 ||
1096 current_cpu_data.cputype == CPU_R6000A) {
1097 /*
1098 * The R6000 is the only R-series CPU that features a machine
1099 * check exception (similar to the R4000 cache error) and
1100 * unaligned ldc1/sdc1 exception. The handlers have not been
1101 * written yet. Well, anyway there is no R6000 machine on the
1102 * current list of targets for Linux/MIPS.
1103 * (Duh, crap, there is someone with a triple R6k machine)
1104 */
1105 //set_except_vector(14, handle_mc);
1106 //set_except_vector(15, handle_ndc);
1107 }
1108
e50c0a8f
RB		 1109 if (cpu_has_fpu && !cpu_has_nofpuex)
1110 set_except_vector(15, handle_fpe);
1111
1112 set_except_vector(22, handle_mdmx);
1113
1114 if (cpu_has_mcheck)
1115 set_except_vector(24, handle_mcheck);
1116
1117 if (cpu_has_dsp)
1118 set_except_vector(26, handle_dsp);
1119
1120 if (cpu_has_vce)
1121 /* Special exception: R4[04]00 uses also the divec space. */
1122 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1123 else if (cpu_has_4kex)
1124 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1125 else
1126 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1127
1da177e4
LT		 1128 signal_init();
1129#ifdef CONFIG_MIPS32_COMPAT
1130 signal32_init();
1131#endif
1132
1133 flush_icache_range(CAC_BASE, CAC_BASE + 0x400);
1134}
Linux 6.x block layer and io_uring tree(s)