[linux-2.6-block.git] / arch / mips / kernel / sync-r4k.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Count register synchronisation.
 *
 * All CPUs will have their count registers synchronised to the CPU0 next time
 * value. This can cause a small timewarp for CPU0. All other CPU's should
 * not have done anything significant (but they may have had interrupts
 * enabled briefly - prom_smp_finish() should not be responsible for enabling
 * interrupts...)
 */

#include <linux/kernel.h>
#include <linux/irqflags.h>
#include <linux/cpumask.h>

#include <asm/r4k-timer.h>
#include <linux/atomic.h>
#include <asm/barrier.h>
#include <asm/mipsregs.h>

static unsigned int initcount = 0;
static atomic_t count_count_start = ATOMIC_INIT(0);
static atomic_t count_count_stop = ATOMIC_INIT(0);

#define COUNTON 100
#define NR_LOOPS 3

void synchronise_count_master(int cpu)
{
	int i;
	unsigned long flags;

	pr_info("Synchronize counters for CPU %u: ", cpu);

	local_irq_save(flags);

	/*
	 * We loop a few times to get a primed instruction cache,
	 * then the last pass is more or less synchronised and
	 * the master and slaves each set their cycle counters to a known
	 * value all at once. This reduces the chance of having random offsets
	 * between the processors, and guarantees that the maximum
	 * delay between the cycle counters is never bigger than
	 * the latency of information-passing (cachelines) between
	 * two CPUs.
	 */

	for (i = 0; i < NR_LOOPS; i++) {
		/* slaves loop on '!= 2' */
		while (atomic_read(&count_count_start) != 1)
			mb();
		atomic_set(&count_count_stop, 0);
		smp_wmb();

		/* Let the slave writes its count register */
		atomic_inc(&count_count_start);

		/* Count will be initialised to current timer */
		if (i == 1)
			initcount = read_c0_count();

		/*
		 * Everyone initialises count in the last loop:
		 */
		if (i == NR_LOOPS-1)
			write_c0_count(initcount);

		/*
		 * Wait for slave to leave the synchronization point:
		 */
		while (atomic_read(&count_count_stop) != 1)
			mb();
		atomic_set(&count_count_start, 0);
		smp_wmb();
		atomic_inc(&count_count_stop);
	}
	/* Arrange for an interrupt in a short while */
	write_c0_compare(read_c0_count() + COUNTON);

	local_irq_restore(flags);

	/*
	 * i386 code reported the skew here, but the
	 * count registers were almost certainly out of sync
	 * so no point in alarming people
	 */
	pr_cont("done.\n");
}

void synchronise_count_slave(int cpu)
{
	int i;

	/*
	 * Not every cpu is online at the time this gets called,
	 * so we first wait for the master to say everyone is ready
	 */

	for (i = 0; i < NR_LOOPS; i++) {
		atomic_inc(&count_count_start);
		while (atomic_read(&count_count_start) != 2)
			mb();

		/*
		 * Everyone initialises count in the last loop:
		 */
		if (i == NR_LOOPS-1)
			write_c0_count(initcount);

		atomic_inc(&count_count_stop);
		while (atomic_read(&count_count_stop) != 2)
			mb();
	}
	/* Arrange for an interrupt in a short while */
	write_c0_compare(read_c0_count() + COUNTON);
}
#undef NR_LOOPS
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
39b8d525 RB	2	/*
	3	* Count register synchronisation.
	4	*
eb9b5141	5	* All CPUs will have their count registers synchronised to the CPU0 next time
39b8d525 RB	6	* value. This can cause a small timewarp for CPU0. All other CPU's should
	7	* not have done anything significant (but they may have had interrupts
	8	* enabled briefly - prom_smp_finish() should not be responsible for enabling
	9	* interrupts...)
39b8d525 RB	10	*/
	11
	12	#include <linux/kernel.h>
39b8d525	13	#include <linux/irqflags.h>
eb9b5141	14	#include <linux/cpumask.h>
39b8d525	15
eb9b5141	16	#include <asm/r4k-timer.h>
60063497	17	#include <linux/atomic.h>
39b8d525	18	#include <asm/barrier.h>
39b8d525 RB	19	#include <asm/mipsregs.h>
39b8d525 RB	20
db0dbd57	21	static unsigned int initcount = 0;
078a55fc PG	22	static atomic_t count_count_start = ATOMIC_INIT(0);
078a55fc PG	23	static atomic_t count_count_stop = ATOMIC_INIT(0);
39b8d525	24
70342287	25	#define COUNTON 100
db0dbd57	26	#define NR_LOOPS 3
39b8d525	27
078a55fc	28	void synchronise_count_master(int cpu)
39b8d525 RB	29	{
	30	int i;
	31	unsigned long flags;
39b8d525	32
4fb69afa	33	pr_info("Synchronize counters for CPU %u: ", cpu);
39b8d525 RB	34
	35	local_irq_save(flags);
	36
39b8d525 RB	37	/*
	38	* We loop a few times to get a primed instruction cache,
	39	* then the last pass is more or less synchronised and
	40	* the master and slaves each set their cycle counters to a known
	41	* value all at once. This reduces the chance of having random offsets
	42	* between the processors, and guarantees that the maximum
	43	* delay between the cycle counters is never bigger than
	44	* the latency of information-passing (cachelines) between
	45	* two CPUs.
	46	*/
	47
39b8d525	48	for (i = 0; i < NR_LOOPS; i++) {
cf9bfe55 J	49	/* slaves loop on '!= 2' */
cf9bfe55 J	50	while (atomic_read(&count_count_start) != 1)
39b8d525 RB	51	mb();
	52	atomic_set(&count_count_stop, 0);
	53	smp_wmb();
	54
db0dbd57	55	/* Let the slave writes its count register */
39b8d525 RB	56	atomic_inc(&count_count_start);
39b8d525 RB	57
db0dbd57 HC	58	/* Count will be initialised to current timer */
	59	if (i == 1)
	60	initcount = read_c0_count();
	61
39b8d525 RB	62	/*
	63	* Everyone initialises count in the last loop:
	64	*/
	65	if (i == NR_LOOPS-1)
	66	write_c0_count(initcount);
	67
	68	/*
db0dbd57	69	* Wait for slave to leave the synchronization point:
39b8d525	70	*/
cf9bfe55	71	while (atomic_read(&count_count_stop) != 1)
39b8d525 RB	72	mb();
	73	atomic_set(&count_count_start, 0);
	74	smp_wmb();
	75	atomic_inc(&count_count_stop);
	76	}
	77	/* Arrange for an interrupt in a short while */
	78	write_c0_compare(read_c0_count() + COUNTON);
	79
	80	local_irq_restore(flags);
	81
	82	/*
	83	* i386 code reported the skew here, but the
	84	* count registers were almost certainly out of sync
	85	* so no point in alarming people
	86	*/
4fb69afa	87	pr_cont("done.\n");
39b8d525 RB	88	}
39b8d525 RB	89
078a55fc	90	void synchronise_count_slave(int cpu)
39b8d525 RB	91	{
39b8d525 RB	92	int i;
39b8d525	93
39b8d525 RB	94	/*
	95	* Not every cpu is online at the time this gets called,
	96	* so we first wait for the master to say everyone is ready
	97	*/
	98
39b8d525 RB	99	for (i = 0; i < NR_LOOPS; i++) {
39b8d525 RB	100	atomic_inc(&count_count_start);
cf9bfe55	101	while (atomic_read(&count_count_start) != 2)
39b8d525 RB	102	mb();
	103
	104	/*
	105	* Everyone initialises count in the last loop:
	106	*/
	107	if (i == NR_LOOPS-1)
	108	write_c0_count(initcount);
	109
	110	atomic_inc(&count_count_stop);
cf9bfe55	111	while (atomic_read(&count_count_stop) != 2)
39b8d525 RB	112	mb();
	113	}
	114	/* Arrange for an interrupt in a short while */
	115	write_c0_compare(read_c0_count() + COUNTON);
39b8d525 RB	116	}
39b8d525 RB	117	#undef NR_LOOPS