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0ee958e1 PB |
1 | /* |
2 | * Copyright (C) 2013 Imagination Technologies | |
3 | * Author: Paul Burton <paul.burton@imgtec.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2 of the License, or (at your | |
8 | * option) any later version. | |
9 | */ | |
10 | ||
11 | #include <linux/io.h> | |
12 | #include <linux/sched.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/smp.h> | |
15 | #include <linux/types.h> | |
16 | ||
17 | #include <asm/cacheflush.h> | |
18 | #include <asm/gic.h> | |
19 | #include <asm/mips-cm.h> | |
20 | #include <asm/mips-cpc.h> | |
21 | #include <asm/mips_mt.h> | |
22 | #include <asm/mipsregs.h> | |
1d8f1f5a | 23 | #include <asm/pm-cps.h> |
0ee958e1 PB |
24 | #include <asm/smp-cps.h> |
25 | #include <asm/time.h> | |
26 | #include <asm/uasm.h> | |
27 | ||
28 | static DECLARE_BITMAP(core_power, NR_CPUS); | |
29 | ||
245a7868 | 30 | struct core_boot_config *mips_cps_core_bootcfg; |
0ee958e1 | 31 | |
245a7868 | 32 | static unsigned core_vpe_count(unsigned core) |
0ee958e1 | 33 | { |
245a7868 | 34 | unsigned cfg; |
0ee958e1 | 35 | |
245a7868 PB |
36 | if (!config_enabled(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt) |
37 | return 1; | |
0ee958e1 | 38 | |
245a7868 PB |
39 | write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF); |
40 | cfg = read_gcr_co_config() & CM_GCR_Cx_CONFIG_PVPE_MSK; | |
41 | return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1; | |
0ee958e1 PB |
42 | } |
43 | ||
44 | static void __init cps_smp_setup(void) | |
45 | { | |
46 | unsigned int ncores, nvpes, core_vpes; | |
47 | int c, v; | |
0ee958e1 PB |
48 | |
49 | /* Detect & record VPE topology */ | |
50 | ncores = mips_cm_numcores(); | |
51 | pr_info("VPE topology "); | |
52 | for (c = nvpes = 0; c < ncores; c++) { | |
245a7868 | 53 | core_vpes = core_vpe_count(c); |
0ee958e1 PB |
54 | pr_cont("%c%u", c ? ',' : '{', core_vpes); |
55 | ||
245a7868 PB |
56 | /* Use the number of VPEs in core 0 for smp_num_siblings */ |
57 | if (!c) | |
58 | smp_num_siblings = core_vpes; | |
59 | ||
0ee958e1 PB |
60 | for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) { |
61 | cpu_data[nvpes + v].core = c; | |
62 | #ifdef CONFIG_MIPS_MT_SMP | |
63 | cpu_data[nvpes + v].vpe_id = v; | |
64 | #endif | |
65 | } | |
66 | ||
67 | nvpes += core_vpes; | |
68 | } | |
69 | pr_cont("} total %u\n", nvpes); | |
70 | ||
71 | /* Indicate present CPUs (CPU being synonymous with VPE) */ | |
72 | for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) { | |
73 | set_cpu_possible(v, true); | |
74 | set_cpu_present(v, true); | |
75 | __cpu_number_map[v] = v; | |
76 | __cpu_logical_map[v] = v; | |
77 | } | |
78 | ||
79 | /* Core 0 is powered up (we're running on it) */ | |
80 | bitmap_set(core_power, 0, 1); | |
81 | ||
0ee958e1 | 82 | /* Initialise core 0 */ |
245a7868 | 83 | mips_cps_core_init(); |
0ee958e1 | 84 | |
0ee958e1 PB |
85 | /* Make core 0 coherent with everything */ |
86 | write_gcr_cl_coherence(0xff); | |
87 | } | |
88 | ||
89 | static void __init cps_prepare_cpus(unsigned int max_cpus) | |
90 | { | |
5c399f6e PB |
91 | unsigned ncores, core_vpes, c, cca; |
92 | bool cca_unsuitable; | |
0f4d3d11 | 93 | u32 *entry_code; |
245a7868 | 94 | |
0ee958e1 | 95 | mips_mt_set_cpuoptions(); |
245a7868 | 96 | |
5c399f6e PB |
97 | /* Detect whether the CCA is unsuited to multi-core SMP */ |
98 | cca = read_c0_config() & CONF_CM_CMASK; | |
99 | switch (cca) { | |
100 | case 0x4: /* CWBE */ | |
101 | case 0x5: /* CWB */ | |
102 | /* The CCA is coherent, multi-core is fine */ | |
103 | cca_unsuitable = false; | |
104 | break; | |
105 | ||
106 | default: | |
107 | /* CCA is not coherent, multi-core is not usable */ | |
108 | cca_unsuitable = true; | |
109 | } | |
110 | ||
111 | /* Warn the user if the CCA prevents multi-core */ | |
112 | ncores = mips_cm_numcores(); | |
113 | if (cca_unsuitable && ncores > 1) { | |
114 | pr_warn("Using only one core due to unsuitable CCA 0x%x\n", | |
115 | cca); | |
116 | ||
117 | for_each_present_cpu(c) { | |
118 | if (cpu_data[c].core) | |
119 | set_cpu_present(c, false); | |
120 | } | |
121 | } | |
122 | ||
0f4d3d11 PB |
123 | /* Patch the start of mips_cps_core_entry to provide the CM base */ |
124 | entry_code = (u32 *)&mips_cps_core_entry; | |
125 | UASM_i_LA(&entry_code, 3, (long)mips_cm_base); | |
126 | dma_cache_wback_inv((unsigned long)&mips_cps_core_entry, | |
127 | (void *)entry_code - (void *)&mips_cps_core_entry); | |
128 | ||
245a7868 | 129 | /* Allocate core boot configuration structs */ |
245a7868 PB |
130 | mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg), |
131 | GFP_KERNEL); | |
132 | if (!mips_cps_core_bootcfg) { | |
133 | pr_err("Failed to allocate boot config for %u cores\n", ncores); | |
134 | goto err_out; | |
135 | } | |
136 | ||
137 | /* Allocate VPE boot configuration structs */ | |
138 | for (c = 0; c < ncores; c++) { | |
139 | core_vpes = core_vpe_count(c); | |
140 | mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes, | |
141 | sizeof(*mips_cps_core_bootcfg[c].vpe_config), | |
142 | GFP_KERNEL); | |
143 | if (!mips_cps_core_bootcfg[c].vpe_config) { | |
144 | pr_err("Failed to allocate %u VPE boot configs\n", | |
145 | core_vpes); | |
146 | goto err_out; | |
147 | } | |
148 | } | |
149 | ||
150 | /* Mark this CPU as booted */ | |
151 | atomic_set(&mips_cps_core_bootcfg[current_cpu_data.core].vpe_mask, | |
152 | 1 << cpu_vpe_id(¤t_cpu_data)); | |
153 | ||
154 | return; | |
155 | err_out: | |
156 | /* Clean up allocations */ | |
157 | if (mips_cps_core_bootcfg) { | |
158 | for (c = 0; c < ncores; c++) | |
159 | kfree(mips_cps_core_bootcfg[c].vpe_config); | |
160 | kfree(mips_cps_core_bootcfg); | |
161 | mips_cps_core_bootcfg = NULL; | |
162 | } | |
163 | ||
164 | /* Effectively disable SMP by declaring CPUs not present */ | |
165 | for_each_possible_cpu(c) { | |
166 | if (c == 0) | |
167 | continue; | |
168 | set_cpu_present(c, false); | |
169 | } | |
0ee958e1 PB |
170 | } |
171 | ||
245a7868 | 172 | static void boot_core(unsigned core) |
0ee958e1 PB |
173 | { |
174 | u32 access; | |
175 | ||
176 | /* Select the appropriate core */ | |
245a7868 | 177 | write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF); |
0ee958e1 PB |
178 | |
179 | /* Set its reset vector */ | |
180 | write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry)); | |
181 | ||
182 | /* Ensure its coherency is disabled */ | |
183 | write_gcr_co_coherence(0); | |
184 | ||
185 | /* Ensure the core can access the GCRs */ | |
186 | access = read_gcr_access(); | |
245a7868 | 187 | access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + core); |
0ee958e1 PB |
188 | write_gcr_access(access); |
189 | ||
0ee958e1 | 190 | if (mips_cpc_present()) { |
0ee958e1 | 191 | /* Reset the core */ |
dd9233d0 | 192 | mips_cpc_lock_other(core); |
0ee958e1 | 193 | write_cpc_co_cmd(CPC_Cx_CMD_RESET); |
dd9233d0 | 194 | mips_cpc_unlock_other(); |
0ee958e1 PB |
195 | } else { |
196 | /* Take the core out of reset */ | |
197 | write_gcr_co_reset_release(0); | |
198 | } | |
199 | ||
200 | /* The core is now powered up */ | |
245a7868 | 201 | bitmap_set(core_power, core, 1); |
0ee958e1 PB |
202 | } |
203 | ||
245a7868 | 204 | static void remote_vpe_boot(void *dummy) |
0ee958e1 | 205 | { |
245a7868 | 206 | mips_cps_boot_vpes(); |
0ee958e1 PB |
207 | } |
208 | ||
209 | static void cps_boot_secondary(int cpu, struct task_struct *idle) | |
210 | { | |
245a7868 PB |
211 | unsigned core = cpu_data[cpu].core; |
212 | unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); | |
213 | struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core]; | |
214 | struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id]; | |
0ee958e1 PB |
215 | unsigned int remote; |
216 | int err; | |
217 | ||
245a7868 PB |
218 | vpe_cfg->pc = (unsigned long)&smp_bootstrap; |
219 | vpe_cfg->sp = __KSTK_TOS(idle); | |
220 | vpe_cfg->gp = (unsigned long)task_thread_info(idle); | |
0ee958e1 | 221 | |
245a7868 PB |
222 | atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask); |
223 | ||
1d8f1f5a PB |
224 | preempt_disable(); |
225 | ||
245a7868 | 226 | if (!test_bit(core, core_power)) { |
0ee958e1 | 227 | /* Boot a VPE on a powered down core */ |
245a7868 | 228 | boot_core(core); |
1d8f1f5a | 229 | goto out; |
0ee958e1 PB |
230 | } |
231 | ||
245a7868 | 232 | if (core != current_cpu_data.core) { |
0ee958e1 PB |
233 | /* Boot a VPE on another powered up core */ |
234 | for (remote = 0; remote < NR_CPUS; remote++) { | |
245a7868 | 235 | if (cpu_data[remote].core != core) |
0ee958e1 PB |
236 | continue; |
237 | if (cpu_online(remote)) | |
238 | break; | |
239 | } | |
240 | BUG_ON(remote >= NR_CPUS); | |
241 | ||
245a7868 PB |
242 | err = smp_call_function_single(remote, remote_vpe_boot, |
243 | NULL, 1); | |
0ee958e1 PB |
244 | if (err) |
245 | panic("Failed to call remote CPU\n"); | |
1d8f1f5a | 246 | goto out; |
0ee958e1 PB |
247 | } |
248 | ||
249 | BUG_ON(!cpu_has_mipsmt); | |
250 | ||
251 | /* Boot a VPE on this core */ | |
245a7868 | 252 | mips_cps_boot_vpes(); |
1d8f1f5a PB |
253 | out: |
254 | preempt_enable(); | |
0ee958e1 PB |
255 | } |
256 | ||
257 | static void cps_init_secondary(void) | |
258 | { | |
259 | /* Disable MT - we only want to run 1 TC per VPE */ | |
260 | if (cpu_has_mipsmt) | |
261 | dmt(); | |
262 | ||
0ee958e1 PB |
263 | change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | |
264 | STATUSF_IP6 | STATUSF_IP7); | |
265 | } | |
266 | ||
267 | static void cps_smp_finish(void) | |
268 | { | |
269 | write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ)); | |
270 | ||
271 | #ifdef CONFIG_MIPS_MT_FPAFF | |
272 | /* If we have an FPU, enroll ourselves in the FPU-full mask */ | |
273 | if (cpu_has_fpu) | |
274 | cpu_set(smp_processor_id(), mt_fpu_cpumask); | |
275 | #endif /* CONFIG_MIPS_MT_FPAFF */ | |
276 | ||
277 | local_irq_enable(); | |
278 | } | |
279 | ||
280 | static void cps_cpus_done(void) | |
281 | { | |
282 | } | |
283 | ||
1d8f1f5a PB |
284 | #ifdef CONFIG_HOTPLUG_CPU |
285 | ||
286 | static int cps_cpu_disable(void) | |
287 | { | |
288 | unsigned cpu = smp_processor_id(); | |
289 | struct core_boot_config *core_cfg; | |
290 | ||
291 | if (!cpu) | |
292 | return -EBUSY; | |
293 | ||
294 | if (!cps_pm_support_state(CPS_PM_POWER_GATED)) | |
295 | return -EINVAL; | |
296 | ||
297 | core_cfg = &mips_cps_core_bootcfg[current_cpu_data.core]; | |
298 | atomic_sub(1 << cpu_vpe_id(¤t_cpu_data), &core_cfg->vpe_mask); | |
299 | smp_mb__after_atomic_dec(); | |
300 | set_cpu_online(cpu, false); | |
301 | cpu_clear(cpu, cpu_callin_map); | |
302 | ||
303 | return 0; | |
304 | } | |
305 | ||
306 | static DECLARE_COMPLETION(cpu_death_chosen); | |
307 | static unsigned cpu_death_sibling; | |
308 | static enum { | |
309 | CPU_DEATH_HALT, | |
310 | CPU_DEATH_POWER, | |
311 | } cpu_death; | |
312 | ||
313 | void play_dead(void) | |
314 | { | |
315 | unsigned cpu, core; | |
316 | ||
317 | local_irq_disable(); | |
318 | idle_task_exit(); | |
319 | cpu = smp_processor_id(); | |
320 | cpu_death = CPU_DEATH_POWER; | |
321 | ||
322 | if (cpu_has_mipsmt) { | |
323 | core = cpu_data[cpu].core; | |
324 | ||
325 | /* Look for another online VPE within the core */ | |
326 | for_each_online_cpu(cpu_death_sibling) { | |
327 | if (cpu_data[cpu_death_sibling].core != core) | |
328 | continue; | |
329 | ||
330 | /* | |
331 | * There is an online VPE within the core. Just halt | |
332 | * this TC and leave the core alone. | |
333 | */ | |
334 | cpu_death = CPU_DEATH_HALT; | |
335 | break; | |
336 | } | |
337 | } | |
338 | ||
339 | /* This CPU has chosen its way out */ | |
340 | complete(&cpu_death_chosen); | |
341 | ||
342 | if (cpu_death == CPU_DEATH_HALT) { | |
343 | /* Halt this TC */ | |
344 | write_c0_tchalt(TCHALT_H); | |
345 | instruction_hazard(); | |
346 | } else { | |
347 | /* Power down the core */ | |
348 | cps_pm_enter_state(CPS_PM_POWER_GATED); | |
349 | } | |
350 | ||
351 | /* This should never be reached */ | |
352 | panic("Failed to offline CPU %u", cpu); | |
353 | } | |
354 | ||
355 | static void wait_for_sibling_halt(void *ptr_cpu) | |
356 | { | |
357 | unsigned cpu = (unsigned)ptr_cpu; | |
358 | unsigned vpe_id = cpu_data[cpu].vpe_id; | |
359 | unsigned halted; | |
360 | unsigned long flags; | |
361 | ||
362 | do { | |
363 | local_irq_save(flags); | |
364 | settc(vpe_id); | |
365 | halted = read_tc_c0_tchalt(); | |
366 | local_irq_restore(flags); | |
367 | } while (!(halted & TCHALT_H)); | |
368 | } | |
369 | ||
370 | static void cps_cpu_die(unsigned int cpu) | |
371 | { | |
372 | unsigned core = cpu_data[cpu].core; | |
373 | unsigned stat; | |
374 | int err; | |
375 | ||
376 | /* Wait for the cpu to choose its way out */ | |
377 | if (!wait_for_completion_timeout(&cpu_death_chosen, | |
378 | msecs_to_jiffies(5000))) { | |
379 | pr_err("CPU%u: didn't offline\n", cpu); | |
380 | return; | |
381 | } | |
382 | ||
383 | /* | |
384 | * Now wait for the CPU to actually offline. Without doing this that | |
385 | * offlining may race with one or more of: | |
386 | * | |
387 | * - Onlining the CPU again. | |
388 | * - Powering down the core if another VPE within it is offlined. | |
389 | * - A sibling VPE entering a non-coherent state. | |
390 | * | |
391 | * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing | |
392 | * with which we could race, so do nothing. | |
393 | */ | |
394 | if (cpu_death == CPU_DEATH_POWER) { | |
395 | /* | |
396 | * Wait for the core to enter a powered down or clock gated | |
397 | * state, the latter happening when a JTAG probe is connected | |
398 | * in which case the CPC will refuse to power down the core. | |
399 | */ | |
400 | do { | |
401 | mips_cpc_lock_other(core); | |
402 | stat = read_cpc_co_stat_conf(); | |
403 | stat &= CPC_Cx_STAT_CONF_SEQSTATE_MSK; | |
404 | mips_cpc_unlock_other(); | |
405 | } while (stat != CPC_Cx_STAT_CONF_SEQSTATE_D0 && | |
406 | stat != CPC_Cx_STAT_CONF_SEQSTATE_D2 && | |
407 | stat != CPC_Cx_STAT_CONF_SEQSTATE_U2); | |
408 | ||
409 | /* Indicate the core is powered off */ | |
410 | bitmap_clear(core_power, core, 1); | |
411 | } else if (cpu_has_mipsmt) { | |
412 | /* | |
413 | * Have a CPU with access to the offlined CPUs registers wait | |
414 | * for its TC to halt. | |
415 | */ | |
416 | err = smp_call_function_single(cpu_death_sibling, | |
417 | wait_for_sibling_halt, | |
418 | (void *)cpu, 1); | |
419 | if (err) | |
420 | panic("Failed to call remote sibling CPU\n"); | |
421 | } | |
422 | } | |
423 | ||
424 | #endif /* CONFIG_HOTPLUG_CPU */ | |
425 | ||
0ee958e1 PB |
426 | static struct plat_smp_ops cps_smp_ops = { |
427 | .smp_setup = cps_smp_setup, | |
428 | .prepare_cpus = cps_prepare_cpus, | |
429 | .boot_secondary = cps_boot_secondary, | |
430 | .init_secondary = cps_init_secondary, | |
431 | .smp_finish = cps_smp_finish, | |
432 | .send_ipi_single = gic_send_ipi_single, | |
433 | .send_ipi_mask = gic_send_ipi_mask, | |
434 | .cpus_done = cps_cpus_done, | |
1d8f1f5a PB |
435 | #ifdef CONFIG_HOTPLUG_CPU |
436 | .cpu_disable = cps_cpu_disable, | |
437 | .cpu_die = cps_cpu_die, | |
438 | #endif | |
0ee958e1 PB |
439 | }; |
440 | ||
68c1232f PB |
441 | bool mips_cps_smp_in_use(void) |
442 | { | |
443 | extern struct plat_smp_ops *mp_ops; | |
444 | return mp_ops == &cps_smp_ops; | |
445 | } | |
446 | ||
0ee958e1 PB |
447 | int register_cps_smp_ops(void) |
448 | { | |
449 | if (!mips_cm_present()) { | |
450 | pr_warn("MIPS CPS SMP unable to proceed without a CM\n"); | |
451 | return -ENODEV; | |
452 | } | |
453 | ||
454 | /* check we have a GIC - we need one for IPIs */ | |
455 | if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX_MSK)) { | |
456 | pr_warn("MIPS CPS SMP unable to proceed without a GIC\n"); | |
457 | return -ENODEV; | |
458 | } | |
459 | ||
460 | register_smp_ops(&cps_smp_ops); | |
461 | return 0; | |
462 | } |