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0ee958e1 PB |
1 | /* |
2 | * Copyright (C) 2013 Imagination Technologies | |
3 | * Author: Paul Burton <paul.burton@imgtec.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2 of the License, or (at your | |
8 | * option) any later version. | |
9 | */ | |
10 | ||
11 | #include <linux/io.h> | |
4060bbe9 | 12 | #include <linux/irqchip/mips-gic.h> |
0ee958e1 PB |
13 | #include <linux/sched.h> |
14 | #include <linux/slab.h> | |
15 | #include <linux/smp.h> | |
16 | #include <linux/types.h> | |
17 | ||
0fc0708a | 18 | #include <asm/bcache.h> |
0ee958e1 PB |
19 | #include <asm/mips-cm.h> |
20 | #include <asm/mips-cpc.h> | |
21 | #include <asm/mips_mt.h> | |
22 | #include <asm/mipsregs.h> | |
1d8f1f5a | 23 | #include <asm/pm-cps.h> |
0fc0708a | 24 | #include <asm/r4kcache.h> |
0ee958e1 PB |
25 | #include <asm/smp-cps.h> |
26 | #include <asm/time.h> | |
27 | #include <asm/uasm.h> | |
28 | ||
29 | static DECLARE_BITMAP(core_power, NR_CPUS); | |
30 | ||
245a7868 | 31 | struct core_boot_config *mips_cps_core_bootcfg; |
0ee958e1 | 32 | |
245a7868 | 33 | static unsigned core_vpe_count(unsigned core) |
0ee958e1 | 34 | { |
245a7868 | 35 | unsigned cfg; |
0ee958e1 | 36 | |
245a7868 PB |
37 | if (!config_enabled(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt) |
38 | return 1; | |
0ee958e1 | 39 | |
245a7868 PB |
40 | write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF); |
41 | cfg = read_gcr_co_config() & CM_GCR_Cx_CONFIG_PVPE_MSK; | |
42 | return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1; | |
0ee958e1 PB |
43 | } |
44 | ||
45 | static void __init cps_smp_setup(void) | |
46 | { | |
47 | unsigned int ncores, nvpes, core_vpes; | |
48 | int c, v; | |
0ee958e1 PB |
49 | |
50 | /* Detect & record VPE topology */ | |
51 | ncores = mips_cm_numcores(); | |
52 | pr_info("VPE topology "); | |
53 | for (c = nvpes = 0; c < ncores; c++) { | |
245a7868 | 54 | core_vpes = core_vpe_count(c); |
0ee958e1 PB |
55 | pr_cont("%c%u", c ? ',' : '{', core_vpes); |
56 | ||
245a7868 PB |
57 | /* Use the number of VPEs in core 0 for smp_num_siblings */ |
58 | if (!c) | |
59 | smp_num_siblings = core_vpes; | |
60 | ||
0ee958e1 PB |
61 | for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) { |
62 | cpu_data[nvpes + v].core = c; | |
63 | #ifdef CONFIG_MIPS_MT_SMP | |
64 | cpu_data[nvpes + v].vpe_id = v; | |
65 | #endif | |
66 | } | |
67 | ||
68 | nvpes += core_vpes; | |
69 | } | |
70 | pr_cont("} total %u\n", nvpes); | |
71 | ||
72 | /* Indicate present CPUs (CPU being synonymous with VPE) */ | |
73 | for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) { | |
74 | set_cpu_possible(v, true); | |
75 | set_cpu_present(v, true); | |
76 | __cpu_number_map[v] = v; | |
77 | __cpu_logical_map[v] = v; | |
78 | } | |
79 | ||
33b68665 PB |
80 | /* Set a coherent default CCA (CWB) */ |
81 | change_c0_config(CONF_CM_CMASK, 0x5); | |
82 | ||
0ee958e1 PB |
83 | /* Core 0 is powered up (we're running on it) */ |
84 | bitmap_set(core_power, 0, 1); | |
85 | ||
0ee958e1 | 86 | /* Initialise core 0 */ |
245a7868 | 87 | mips_cps_core_init(); |
0ee958e1 PB |
88 | |
89 | /* Make core 0 coherent with everything */ | |
90 | write_gcr_cl_coherence(0xff); | |
90db024f NC |
91 | |
92 | #ifdef CONFIG_MIPS_MT_FPAFF | |
93 | /* If we have an FPU, enroll ourselves in the FPU-full mask */ | |
94 | if (cpu_has_fpu) | |
7363cb7d | 95 | cpumask_set_cpu(0, &mt_fpu_cpumask); |
90db024f | 96 | #endif /* CONFIG_MIPS_MT_FPAFF */ |
0ee958e1 PB |
97 | } |
98 | ||
99 | static void __init cps_prepare_cpus(unsigned int max_cpus) | |
100 | { | |
5c399f6e PB |
101 | unsigned ncores, core_vpes, c, cca; |
102 | bool cca_unsuitable; | |
0f4d3d11 | 103 | u32 *entry_code; |
245a7868 | 104 | |
0ee958e1 | 105 | mips_mt_set_cpuoptions(); |
245a7868 | 106 | |
5c399f6e PB |
107 | /* Detect whether the CCA is unsuited to multi-core SMP */ |
108 | cca = read_c0_config() & CONF_CM_CMASK; | |
109 | switch (cca) { | |
110 | case 0x4: /* CWBE */ | |
111 | case 0x5: /* CWB */ | |
112 | /* The CCA is coherent, multi-core is fine */ | |
113 | cca_unsuitable = false; | |
114 | break; | |
115 | ||
116 | default: | |
117 | /* CCA is not coherent, multi-core is not usable */ | |
118 | cca_unsuitable = true; | |
119 | } | |
120 | ||
121 | /* Warn the user if the CCA prevents multi-core */ | |
122 | ncores = mips_cm_numcores(); | |
123 | if (cca_unsuitable && ncores > 1) { | |
124 | pr_warn("Using only one core due to unsuitable CCA 0x%x\n", | |
125 | cca); | |
126 | ||
127 | for_each_present_cpu(c) { | |
128 | if (cpu_data[c].core) | |
129 | set_cpu_present(c, false); | |
130 | } | |
131 | } | |
132 | ||
0155a065 PB |
133 | /* |
134 | * Patch the start of mips_cps_core_entry to provide: | |
135 | * | |
0155a065 PB |
136 | * s0 = kseg0 CCA |
137 | */ | |
0f4d3d11 | 138 | entry_code = (u32 *)&mips_cps_core_entry; |
0155a065 | 139 | uasm_i_addiu(&entry_code, 16, 0, cca); |
0fc0708a PB |
140 | blast_dcache_range((unsigned long)&mips_cps_core_entry, |
141 | (unsigned long)entry_code); | |
142 | bc_wback_inv((unsigned long)&mips_cps_core_entry, | |
143 | (void *)entry_code - (void *)&mips_cps_core_entry); | |
144 | __sync(); | |
0f4d3d11 | 145 | |
245a7868 | 146 | /* Allocate core boot configuration structs */ |
245a7868 PB |
147 | mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg), |
148 | GFP_KERNEL); | |
149 | if (!mips_cps_core_bootcfg) { | |
150 | pr_err("Failed to allocate boot config for %u cores\n", ncores); | |
151 | goto err_out; | |
152 | } | |
153 | ||
154 | /* Allocate VPE boot configuration structs */ | |
155 | for (c = 0; c < ncores; c++) { | |
156 | core_vpes = core_vpe_count(c); | |
157 | mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes, | |
158 | sizeof(*mips_cps_core_bootcfg[c].vpe_config), | |
159 | GFP_KERNEL); | |
160 | if (!mips_cps_core_bootcfg[c].vpe_config) { | |
161 | pr_err("Failed to allocate %u VPE boot configs\n", | |
162 | core_vpes); | |
163 | goto err_out; | |
164 | } | |
165 | } | |
166 | ||
167 | /* Mark this CPU as booted */ | |
168 | atomic_set(&mips_cps_core_bootcfg[current_cpu_data.core].vpe_mask, | |
169 | 1 << cpu_vpe_id(¤t_cpu_data)); | |
170 | ||
171 | return; | |
172 | err_out: | |
173 | /* Clean up allocations */ | |
174 | if (mips_cps_core_bootcfg) { | |
175 | for (c = 0; c < ncores; c++) | |
176 | kfree(mips_cps_core_bootcfg[c].vpe_config); | |
177 | kfree(mips_cps_core_bootcfg); | |
178 | mips_cps_core_bootcfg = NULL; | |
179 | } | |
180 | ||
181 | /* Effectively disable SMP by declaring CPUs not present */ | |
182 | for_each_possible_cpu(c) { | |
183 | if (c == 0) | |
184 | continue; | |
185 | set_cpu_present(c, false); | |
186 | } | |
0ee958e1 PB |
187 | } |
188 | ||
245a7868 | 189 | static void boot_core(unsigned core) |
0ee958e1 PB |
190 | { |
191 | u32 access; | |
192 | ||
193 | /* Select the appropriate core */ | |
245a7868 | 194 | write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF); |
0ee958e1 PB |
195 | |
196 | /* Set its reset vector */ | |
197 | write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry)); | |
198 | ||
199 | /* Ensure its coherency is disabled */ | |
200 | write_gcr_co_coherence(0); | |
201 | ||
202 | /* Ensure the core can access the GCRs */ | |
203 | access = read_gcr_access(); | |
245a7868 | 204 | access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + core); |
0ee958e1 PB |
205 | write_gcr_access(access); |
206 | ||
0ee958e1 | 207 | if (mips_cpc_present()) { |
0ee958e1 | 208 | /* Reset the core */ |
dd9233d0 | 209 | mips_cpc_lock_other(core); |
0ee958e1 | 210 | write_cpc_co_cmd(CPC_Cx_CMD_RESET); |
dd9233d0 | 211 | mips_cpc_unlock_other(); |
0ee958e1 PB |
212 | } else { |
213 | /* Take the core out of reset */ | |
214 | write_gcr_co_reset_release(0); | |
215 | } | |
216 | ||
217 | /* The core is now powered up */ | |
245a7868 | 218 | bitmap_set(core_power, core, 1); |
0ee958e1 PB |
219 | } |
220 | ||
245a7868 | 221 | static void remote_vpe_boot(void *dummy) |
0ee958e1 | 222 | { |
245a7868 | 223 | mips_cps_boot_vpes(); |
0ee958e1 PB |
224 | } |
225 | ||
226 | static void cps_boot_secondary(int cpu, struct task_struct *idle) | |
227 | { | |
245a7868 PB |
228 | unsigned core = cpu_data[cpu].core; |
229 | unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); | |
230 | struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core]; | |
231 | struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id]; | |
0ee958e1 PB |
232 | unsigned int remote; |
233 | int err; | |
234 | ||
245a7868 PB |
235 | vpe_cfg->pc = (unsigned long)&smp_bootstrap; |
236 | vpe_cfg->sp = __KSTK_TOS(idle); | |
237 | vpe_cfg->gp = (unsigned long)task_thread_info(idle); | |
0ee958e1 | 238 | |
245a7868 PB |
239 | atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask); |
240 | ||
1d8f1f5a | 241 | preempt_disable(); |
0ee958e1 | 242 | |
245a7868 | 243 | if (!test_bit(core, core_power)) { |
0ee958e1 | 244 | /* Boot a VPE on a powered down core */ |
245a7868 | 245 | boot_core(core); |
1d8f1f5a | 246 | goto out; |
0ee958e1 PB |
247 | } |
248 | ||
245a7868 | 249 | if (core != current_cpu_data.core) { |
0ee958e1 PB |
250 | /* Boot a VPE on another powered up core */ |
251 | for (remote = 0; remote < NR_CPUS; remote++) { | |
245a7868 | 252 | if (cpu_data[remote].core != core) |
0ee958e1 PB |
253 | continue; |
254 | if (cpu_online(remote)) | |
255 | break; | |
256 | } | |
257 | BUG_ON(remote >= NR_CPUS); | |
258 | ||
245a7868 PB |
259 | err = smp_call_function_single(remote, remote_vpe_boot, |
260 | NULL, 1); | |
0ee958e1 PB |
261 | if (err) |
262 | panic("Failed to call remote CPU\n"); | |
1d8f1f5a | 263 | goto out; |
0ee958e1 PB |
264 | } |
265 | ||
266 | BUG_ON(!cpu_has_mipsmt); | |
267 | ||
268 | /* Boot a VPE on this core */ | |
245a7868 | 269 | mips_cps_boot_vpes(); |
1d8f1f5a PB |
270 | out: |
271 | preempt_enable(); | |
0ee958e1 PB |
272 | } |
273 | ||
274 | static void cps_init_secondary(void) | |
275 | { | |
276 | /* Disable MT - we only want to run 1 TC per VPE */ | |
277 | if (cpu_has_mipsmt) | |
278 | dmt(); | |
279 | ||
ff1e29ad AB |
280 | change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 | |
281 | STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7); | |
0ee958e1 PB |
282 | } |
283 | ||
284 | static void cps_smp_finish(void) | |
285 | { | |
286 | write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ)); | |
287 | ||
288 | #ifdef CONFIG_MIPS_MT_FPAFF | |
289 | /* If we have an FPU, enroll ourselves in the FPU-full mask */ | |
290 | if (cpu_has_fpu) | |
8dd92891 | 291 | cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask); |
0ee958e1 PB |
292 | #endif /* CONFIG_MIPS_MT_FPAFF */ |
293 | ||
294 | local_irq_enable(); | |
295 | } | |
296 | ||
1d8f1f5a PB |
297 | #ifdef CONFIG_HOTPLUG_CPU |
298 | ||
299 | static int cps_cpu_disable(void) | |
300 | { | |
301 | unsigned cpu = smp_processor_id(); | |
302 | struct core_boot_config *core_cfg; | |
303 | ||
304 | if (!cpu) | |
305 | return -EBUSY; | |
306 | ||
307 | if (!cps_pm_support_state(CPS_PM_POWER_GATED)) | |
308 | return -EINVAL; | |
309 | ||
310 | core_cfg = &mips_cps_core_bootcfg[current_cpu_data.core]; | |
311 | atomic_sub(1 << cpu_vpe_id(¤t_cpu_data), &core_cfg->vpe_mask); | |
e114ba20 | 312 | smp_mb__after_atomic(); |
1d8f1f5a | 313 | set_cpu_online(cpu, false); |
8dd92891 | 314 | cpumask_clear_cpu(cpu, &cpu_callin_map); |
1d8f1f5a PB |
315 | |
316 | return 0; | |
317 | } | |
318 | ||
319 | static DECLARE_COMPLETION(cpu_death_chosen); | |
320 | static unsigned cpu_death_sibling; | |
321 | static enum { | |
322 | CPU_DEATH_HALT, | |
323 | CPU_DEATH_POWER, | |
324 | } cpu_death; | |
325 | ||
326 | void play_dead(void) | |
327 | { | |
328 | unsigned cpu, core; | |
329 | ||
330 | local_irq_disable(); | |
331 | idle_task_exit(); | |
332 | cpu = smp_processor_id(); | |
333 | cpu_death = CPU_DEATH_POWER; | |
334 | ||
335 | if (cpu_has_mipsmt) { | |
336 | core = cpu_data[cpu].core; | |
337 | ||
338 | /* Look for another online VPE within the core */ | |
339 | for_each_online_cpu(cpu_death_sibling) { | |
340 | if (cpu_data[cpu_death_sibling].core != core) | |
341 | continue; | |
342 | ||
343 | /* | |
344 | * There is an online VPE within the core. Just halt | |
345 | * this TC and leave the core alone. | |
346 | */ | |
347 | cpu_death = CPU_DEATH_HALT; | |
348 | break; | |
349 | } | |
350 | } | |
351 | ||
352 | /* This CPU has chosen its way out */ | |
353 | complete(&cpu_death_chosen); | |
354 | ||
355 | if (cpu_death == CPU_DEATH_HALT) { | |
356 | /* Halt this TC */ | |
357 | write_c0_tchalt(TCHALT_H); | |
358 | instruction_hazard(); | |
359 | } else { | |
360 | /* Power down the core */ | |
361 | cps_pm_enter_state(CPS_PM_POWER_GATED); | |
362 | } | |
363 | ||
364 | /* This should never be reached */ | |
365 | panic("Failed to offline CPU %u", cpu); | |
366 | } | |
367 | ||
368 | static void wait_for_sibling_halt(void *ptr_cpu) | |
369 | { | |
fd5ed306 | 370 | unsigned cpu = (unsigned long)ptr_cpu; |
c90e49f2 | 371 | unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); |
1d8f1f5a PB |
372 | unsigned halted; |
373 | unsigned long flags; | |
374 | ||
375 | do { | |
376 | local_irq_save(flags); | |
377 | settc(vpe_id); | |
378 | halted = read_tc_c0_tchalt(); | |
379 | local_irq_restore(flags); | |
380 | } while (!(halted & TCHALT_H)); | |
381 | } | |
382 | ||
383 | static void cps_cpu_die(unsigned int cpu) | |
384 | { | |
385 | unsigned core = cpu_data[cpu].core; | |
386 | unsigned stat; | |
387 | int err; | |
388 | ||
389 | /* Wait for the cpu to choose its way out */ | |
390 | if (!wait_for_completion_timeout(&cpu_death_chosen, | |
391 | msecs_to_jiffies(5000))) { | |
392 | pr_err("CPU%u: didn't offline\n", cpu); | |
393 | return; | |
394 | } | |
395 | ||
396 | /* | |
397 | * Now wait for the CPU to actually offline. Without doing this that | |
398 | * offlining may race with one or more of: | |
399 | * | |
400 | * - Onlining the CPU again. | |
401 | * - Powering down the core if another VPE within it is offlined. | |
402 | * - A sibling VPE entering a non-coherent state. | |
403 | * | |
404 | * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing | |
405 | * with which we could race, so do nothing. | |
406 | */ | |
407 | if (cpu_death == CPU_DEATH_POWER) { | |
408 | /* | |
409 | * Wait for the core to enter a powered down or clock gated | |
410 | * state, the latter happening when a JTAG probe is connected | |
411 | * in which case the CPC will refuse to power down the core. | |
412 | */ | |
413 | do { | |
414 | mips_cpc_lock_other(core); | |
415 | stat = read_cpc_co_stat_conf(); | |
416 | stat &= CPC_Cx_STAT_CONF_SEQSTATE_MSK; | |
417 | mips_cpc_unlock_other(); | |
418 | } while (stat != CPC_Cx_STAT_CONF_SEQSTATE_D0 && | |
419 | stat != CPC_Cx_STAT_CONF_SEQSTATE_D2 && | |
420 | stat != CPC_Cx_STAT_CONF_SEQSTATE_U2); | |
421 | ||
422 | /* Indicate the core is powered off */ | |
423 | bitmap_clear(core_power, core, 1); | |
424 | } else if (cpu_has_mipsmt) { | |
425 | /* | |
426 | * Have a CPU with access to the offlined CPUs registers wait | |
427 | * for its TC to halt. | |
428 | */ | |
429 | err = smp_call_function_single(cpu_death_sibling, | |
430 | wait_for_sibling_halt, | |
fd5ed306 | 431 | (void *)(unsigned long)cpu, 1); |
1d8f1f5a PB |
432 | if (err) |
433 | panic("Failed to call remote sibling CPU\n"); | |
434 | } | |
435 | } | |
436 | ||
437 | #endif /* CONFIG_HOTPLUG_CPU */ | |
438 | ||
0ee958e1 PB |
439 | static struct plat_smp_ops cps_smp_ops = { |
440 | .smp_setup = cps_smp_setup, | |
441 | .prepare_cpus = cps_prepare_cpus, | |
442 | .boot_secondary = cps_boot_secondary, | |
443 | .init_secondary = cps_init_secondary, | |
444 | .smp_finish = cps_smp_finish, | |
445 | .send_ipi_single = gic_send_ipi_single, | |
446 | .send_ipi_mask = gic_send_ipi_mask, | |
1d8f1f5a PB |
447 | #ifdef CONFIG_HOTPLUG_CPU |
448 | .cpu_disable = cps_cpu_disable, | |
449 | .cpu_die = cps_cpu_die, | |
450 | #endif | |
0ee958e1 PB |
451 | }; |
452 | ||
68c1232f PB |
453 | bool mips_cps_smp_in_use(void) |
454 | { | |
455 | extern struct plat_smp_ops *mp_ops; | |
456 | return mp_ops == &cps_smp_ops; | |
457 | } | |
458 | ||
0ee958e1 PB |
459 | int register_cps_smp_ops(void) |
460 | { | |
461 | if (!mips_cm_present()) { | |
462 | pr_warn("MIPS CPS SMP unable to proceed without a CM\n"); | |
463 | return -ENODEV; | |
464 | } | |
465 | ||
466 | /* check we have a GIC - we need one for IPIs */ | |
467 | if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX_MSK)) { | |
468 | pr_warn("MIPS CPS SMP unable to proceed without a GIC\n"); | |
469 | return -ENODEV; | |
470 | } | |
471 | ||
472 | register_smp_ops(&cps_smp_ops); | |
473 | return 0; | |
474 | } |