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MIPS: Add support for the M5150 processor
[linux-2.6-block.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
70342287 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4 22#include <asm/cpu.h>
69f24d17 23#include <asm/cpu-type.h>
1da177e4
LT		 24#include <asm/fpu.h>
25#include <asm/mipsregs.h>
a5e9a69e 26#include <asm/msa.h>
654f57bf 27#include <asm/watch.h>
06372a63 28#include <asm/elf.h>
a074f0e8 29#include <asm/spram.h>
949e51be
DD		 30#include <asm/uaccess.h>
31
078a55fc 32static int mips_fpu_disabled;
0103d23f
KC		 33
34static int __init fpu_disable(char *s)
35{
36 cpu_data[0].options &= ~MIPS_CPU_FPU;
37 mips_fpu_disabled = 1;
38
39 return 1;
40}
41
42__setup("nofpu", fpu_disable);
43
078a55fc 44int mips_dsp_disabled;
0103d23f
KC		 45
46static int __init dsp_disable(char *s)
47{
ee80f7c7 48 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f
KC		 49 mips_dsp_disabled = 1;
50
51 return 1;
52}
53
54__setup("nodsp", dsp_disable);
55
9267a30d
MSJ		 56static inline void check_errata(void)
57{
58 struct cpuinfo_mips *c = &current_cpu_data;
59
69f24d17 60 switch (current_cpu_type()) {
9267a30d
MSJ		 61 case CPU_34K:
62 /*
63 * Erratum "RPS May Cause Incorrect Instruction Execution"
64 * This code only handles VPE0, any SMP/SMTC/RTOS code
65 * making use of VPE1 will be responsable for that VPE.
66 */
67 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
68 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
69 break;
70 default:
71 break;
72 }
73}
74
1da177e4
LT		 75void __init check_bugs32(void)
76{
9267a30d 77 check_errata();
1da177e4
LT		 78}
79
80/*
81 * Probe whether cpu has config register by trying to play with
82 * alternate cache bit and see whether it matters.
83 * It's used by cpu_probe to distinguish between R3000A and R3081.
84 */
85static inline int cpu_has_confreg(void)
86{
87#ifdef CONFIG_CPU_R3000
88 extern unsigned long r3k_cache_size(unsigned long);
89 unsigned long size1, size2;
90 unsigned long cfg = read_c0_conf();
91
92 size1 = r3k_cache_size(ST0_ISC);
93 write_c0_conf(cfg ^ R30XX_CONF_AC);
94 size2 = r3k_cache_size(ST0_ISC);
95 write_c0_conf(cfg);
96 return size1 != size2;
97#else
98 return 0;
99#endif
100}
101
c094c99e
RM		 102static inline void set_elf_platform(int cpu, const char *plat)
103{
104 if (cpu == 0)
105 __elf_platform = plat;
106}
107
1da177e4
LT		 108/*
109 * Get the FPU Implementation/Revision.
110 */
111static inline unsigned long cpu_get_fpu_id(void)
112{
113 unsigned long tmp, fpu_id;
114
115 tmp = read_c0_status();
597ce172 116 __enable_fpu(FPU_AS_IS);
1da177e4
LT		 117 fpu_id = read_32bit_cp1_register(CP1_REVISION);
118 write_c0_status(tmp);
119 return fpu_id;
120}
121
122/*
123 * Check the CPU has an FPU the official way.
124 */
125static inline int __cpu_has_fpu(void)
126{
8ff374b9 127 return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
1da177e4
LT		 128}
129
a5e9a69e
PB		 130static inline unsigned long cpu_get_msa_id(void)
131{
132 unsigned long status, conf5, msa_id;
133
134 status = read_c0_status();
135 __enable_fpu(FPU_64BIT);
136 conf5 = read_c0_config5();
137 enable_msa();
138 msa_id = read_msa_ir();
139 write_c0_config5(conf5);
140 write_c0_status(status);
141 return msa_id;
142}
143
91dfc423
GR		 144static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
145{
146#ifdef __NEED_VMBITS_PROBE
5b7efa89 147 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 148 back_to_back_c0_hazard();
5b7efa89 149 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 150#endif
151}
152
078a55fc 153static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
a96102be
SH		 154{
155 switch (isa) {
156 case MIPS_CPU_ISA_M64R2:
157 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
158 case MIPS_CPU_ISA_M64R1:
159 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
160 case MIPS_CPU_ISA_V:
161 c->isa_level |= MIPS_CPU_ISA_V;
162 case MIPS_CPU_ISA_IV:
163 c->isa_level |= MIPS_CPU_ISA_IV;
164 case MIPS_CPU_ISA_III:
1990e542 165 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
a96102be
SH		 166 break;
167
168 case MIPS_CPU_ISA_M32R2:
169 c->isa_level |= MIPS_CPU_ISA_M32R2;
170 case MIPS_CPU_ISA_M32R1:
171 c->isa_level |= MIPS_CPU_ISA_M32R1;
172 case MIPS_CPU_ISA_II:
173 c->isa_level |= MIPS_CPU_ISA_II;
a96102be
SH		 174 break;
175 }
176}
177
078a55fc 178static char unknown_isa[] = KERN_ERR \
2fa36399
KC		 179 "Unsupported ISA type, c0.config0: %d.";
180
75b5b5e0
LY		 181static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
182{
183 unsigned int config6;
d83b0e82
JH		 184
185 /* It's implementation dependent how the FTLB can be enabled */
186 switch (c->cputype) {
187 case CPU_PROAPTIV:
188 case CPU_P5600:
189 /* proAptiv & related cores use Config6 to enable the FTLB */
75b5b5e0
LY		 190 config6 = read_c0_config6();
191 if (enable)
192 /* Enable FTLB */
193 write_c0_config6(config6 | MIPS_CONF6_FTLBEN);
194 else
195 /* Disable FTLB */
196 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
197 back_to_back_c0_hazard();
d83b0e82 198 break;
75b5b5e0
LY		 199 }
200}
201
2fa36399
KC		 202static inline unsigned int decode_config0(struct cpuinfo_mips *c)
203{
204 unsigned int config0;
205 int isa;
206
207 config0 = read_c0_config();
208
75b5b5e0
LY		 209 /*
210 * Look for Standard TLB or Dual VTLB and FTLB
211 */
212 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
213 (((config0 & MIPS_CONF_MT) >> 7) == 4))
2fa36399 214 c->options |= MIPS_CPU_TLB;
75b5b5e0 215
2fa36399
KC		 216 isa = (config0 & MIPS_CONF_AT) >> 13;
217 switch (isa) {
218 case 0:
219 switch ((config0 & MIPS_CONF_AR) >> 10) {
220 case 0:
a96102be 221 set_isa(c, MIPS_CPU_ISA_M32R1);
2fa36399
KC		 222 break;
223 case 1:
a96102be 224 set_isa(c, MIPS_CPU_ISA_M32R2);
2fa36399
KC		 225 break;
226 default:
227 goto unknown;
228 }
229 break;
230 case 2:
231 switch ((config0 & MIPS_CONF_AR) >> 10) {
232 case 0:
a96102be 233 set_isa(c, MIPS_CPU_ISA_M64R1);
2fa36399
KC		 234 break;
235 case 1:
a96102be 236 set_isa(c, MIPS_CPU_ISA_M64R2);
2fa36399
KC		 237 break;
238 default:
239 goto unknown;
240 }
241 break;
242 default:
243 goto unknown;
244 }
245
246 return config0 & MIPS_CONF_M;
247
248unknown:
249 panic(unknown_isa, config0);
250}
251
252static inline unsigned int decode_config1(struct cpuinfo_mips *c)
253{
254 unsigned int config1;
255
256 config1 = read_c0_config1();
257
258 if (config1 & MIPS_CONF1_MD)
259 c->ases |= MIPS_ASE_MDMX;
260 if (config1 & MIPS_CONF1_WR)
261 c->options |= MIPS_CPU_WATCH;
262 if (config1 & MIPS_CONF1_CA)
263 c->ases |= MIPS_ASE_MIPS16;
264 if (config1 & MIPS_CONF1_EP)
265 c->options |= MIPS_CPU_EJTAG;
266 if (config1 & MIPS_CONF1_FP) {
267 c->options |= MIPS_CPU_FPU;
268 c->options |= MIPS_CPU_32FPR;
269 }
75b5b5e0 270 if (cpu_has_tlb) {
2fa36399 271 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
75b5b5e0
LY		 272 c->tlbsizevtlb = c->tlbsize;
273 c->tlbsizeftlbsets = 0;
274 }
2fa36399
KC		 275
276 return config1 & MIPS_CONF_M;
277}
278
279static inline unsigned int decode_config2(struct cpuinfo_mips *c)
280{
281 unsigned int config2;
282
283 config2 = read_c0_config2();
284
285 if (config2 & MIPS_CONF2_SL)
286 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
287
288 return config2 & MIPS_CONF_M;
289}
290
291static inline unsigned int decode_config3(struct cpuinfo_mips *c)
292{
293 unsigned int config3;
294
295 config3 = read_c0_config3();
296
b2ab4f08 297 if (config3 & MIPS_CONF3_SM) {
2fa36399 298 c->ases |= MIPS_ASE_SMARTMIPS;
b2ab4f08
SH		 299 c->options |= MIPS_CPU_RIXI;
300 }
301 if (config3 & MIPS_CONF3_RXI)
302 c->options |= MIPS_CPU_RIXI;
2fa36399
KC		 303 if (config3 & MIPS_CONF3_DSP)
304 c->ases |= MIPS_ASE_DSP;
ee80f7c7
SH		 305 if (config3 & MIPS_CONF3_DSP2P)
306 c->ases |= MIPS_ASE_DSP2P;
2fa36399
KC		 307 if (config3 & MIPS_CONF3_VINT)
308 c->options |= MIPS_CPU_VINT;
309 if (config3 & MIPS_CONF3_VEIC)
310 c->options |= MIPS_CPU_VEIC;
311 if (config3 & MIPS_CONF3_MT)
312 c->ases |= MIPS_ASE_MIPSMT;
313 if (config3 & MIPS_CONF3_ULRI)
314 c->options |= MIPS_CPU_ULRI;
f8fa4811
SH		 315 if (config3 & MIPS_CONF3_ISA)
316 c->options |= MIPS_CPU_MICROMIPS;
1e7decdb
DD		 317 if (config3 & MIPS_CONF3_VZ)
318 c->ases |= MIPS_ASE_VZ;
4a0156fb
SH		 319 if (config3 & MIPS_CONF3_SC)
320 c->options |= MIPS_CPU_SEGMENTS;
a5e9a69e
PB		 321 if (config3 & MIPS_CONF3_MSA)
322 c->ases |= MIPS_ASE_MSA;
2fa36399
KC		 323
324 return config3 & MIPS_CONF_M;
325}
326
327static inline unsigned int decode_config4(struct cpuinfo_mips *c)
328{
329 unsigned int config4;
75b5b5e0
LY		 330 unsigned int newcf4;
331 unsigned int mmuextdef;
332 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
2fa36399
KC		 333
334 config4 = read_c0_config4();
335
1745c1ef
LY		 336 if (cpu_has_tlb) {
337 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
338 c->options |= MIPS_CPU_TLBINV;
75b5b5e0
LY		 339 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
340 switch (mmuextdef) {
341 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
342 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
343 c->tlbsizevtlb = c->tlbsize;
344 break;
345 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
346 c->tlbsizevtlb +=
347 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
348 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
349 c->tlbsize = c->tlbsizevtlb;
350 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
351 /* fall through */
352 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
353 newcf4 = (config4 & ~ftlb_page) |
354 (page_size_ftlb(mmuextdef) <<
355 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
356 write_c0_config4(newcf4);
357 back_to_back_c0_hazard();
358 config4 = read_c0_config4();
359 if (config4 != newcf4) {
360 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
361 PAGE_SIZE, config4);
362 /* Switch FTLB off */
363 set_ftlb_enable(c, 0);
364 break;
365 }
366 c->tlbsizeftlbsets = 1 <<
367 ((config4 & MIPS_CONF4_FTLBSETS) >>
368 MIPS_CONF4_FTLBSETS_SHIFT);
369 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
370 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
371 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
372 break;
373 }
1745c1ef
LY		 374 }
375
2fa36399
KC		 376 c->kscratch_mask = (config4 >> 16) & 0xff;
377
378 return config4 & MIPS_CONF_M;
379}
380
8b8a7634
RB		 381static inline unsigned int decode_config5(struct cpuinfo_mips *c)
382{
383 unsigned int config5;
384
385 config5 = read_c0_config5();
386 config5 &= ~MIPS_CONF5_UFR;
387 write_c0_config5(config5);
388
49016748
MC		 389 if (config5 & MIPS_CONF5_EVA)
390 c->options |= MIPS_CPU_EVA;
391
8b8a7634
RB		 392 return config5 & MIPS_CONF_M;
393}
394
078a55fc 395static void decode_configs(struct cpuinfo_mips *c)
2fa36399
KC		 396{
397 int ok;
398
399 /* MIPS32 or MIPS64 compliant CPU. */
400 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
401 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
402
403 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
404
75b5b5e0
LY		 405 /* Enable FTLB if present */
406 set_ftlb_enable(c, 1);
407
2fa36399 408 ok = decode_config0(c); /* Read Config registers. */
70342287 409 BUG_ON(!ok); /* Arch spec violation! */
2fa36399
KC		 410 if (ok)
411 ok = decode_config1(c);
412 if (ok)
413 ok = decode_config2(c);
414 if (ok)
415 ok = decode_config3(c);
416 if (ok)
417 ok = decode_config4(c);
8b8a7634
RB		 418 if (ok)
419 ok = decode_config5(c);
2fa36399
KC		 420
421 mips_probe_watch_registers(c);
422
0ee958e1 423#ifndef CONFIG_MIPS_CPS
2fa36399
KC		 424 if (cpu_has_mips_r2)
425 c->core = read_c0_ebase() & 0x3ff;
0ee958e1 426#endif
2fa36399
KC		 427}
428
02cf2119 429#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 430 | MIPS_CPU_COUNTER)
431
cea7e2df 432static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 433{
8ff374b9 434 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 435 case PRID_IMP_R2000:
436 c->cputype = CPU_R2000;
cea7e2df 437 __cpu_name[cpu] = "R2000";
02cf2119 438 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 439 MIPS_CPU_NOFPUEX;
1da177e4
LT		 440 if (__cpu_has_fpu())
441 c->options |= MIPS_CPU_FPU;
442 c->tlbsize = 64;
443 break;
444 case PRID_IMP_R3000:
8ff374b9 445 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
cea7e2df 446 if (cpu_has_confreg()) {
1da177e4 447 c->cputype = CPU_R3081E;
cea7e2df
RB		 448 __cpu_name[cpu] = "R3081";
449 } else {
1da177e4 450 c->cputype = CPU_R3000A;
cea7e2df
RB		 451 __cpu_name[cpu] = "R3000A";
452 }
cea7e2df 453 } else {
1da177e4 454 c->cputype = CPU_R3000;
cea7e2df
RB		 455 __cpu_name[cpu] = "R3000";
456 }
02cf2119 457 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 458 MIPS_CPU_NOFPUEX;
1da177e4
LT		 459 if (__cpu_has_fpu())
460 c->options |= MIPS_CPU_FPU;
461 c->tlbsize = 64;
462 break;
463 case PRID_IMP_R4000:
464 if (read_c0_config() & CONF_SC) {
8ff374b9
MR		 465 if ((c->processor_id & PRID_REV_MASK) >=
466 PRID_REV_R4400) {
1da177e4 467 c->cputype = CPU_R4400PC;
cea7e2df
RB		 468 __cpu_name[cpu] = "R4400PC";
469 } else {
1da177e4 470 c->cputype = CPU_R4000PC;
cea7e2df
RB		 471 __cpu_name[cpu] = "R4000PC";
472 }
1da177e4 473 } else {
7f177a52
MR		 474 int cca = read_c0_config() & CONF_CM_CMASK;
475 int mc;
476
477 /*
478 * SC and MC versions can't be reliably told apart,
479 * but only the latter support coherent caching
480 * modes so assume the firmware has set the KSEG0
481 * coherency attribute reasonably (if uncached, we
482 * assume SC).
483 */
484 switch (cca) {
485 case CONF_CM_CACHABLE_CE:
486 case CONF_CM_CACHABLE_COW:
487 case CONF_CM_CACHABLE_CUW:
488 mc = 1;
489 break;
490 default:
491 mc = 0;
492 break;
493 }
8ff374b9
MR		 494 if ((c->processor_id & PRID_REV_MASK) >=
495 PRID_REV_R4400) {
7f177a52
MR		 496 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
497 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
cea7e2df 498 } else {
7f177a52
MR		 499 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
500 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
cea7e2df 501 }
1da177e4
LT		 502 }
503
a96102be 504 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 505 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 506 MIPS_CPU_WATCH | MIPS_CPU_VCE |
507 MIPS_CPU_LLSC;
1da177e4
LT		 508 c->tlbsize = 48;
509 break;
510 case PRID_IMP_VR41XX:
9f91e506
YY		 511 set_isa(c, MIPS_CPU_ISA_III);
512 c->options = R4K_OPTS;
513 c->tlbsize = 32;
1da177e4 514 switch (c->processor_id & 0xf0) {
1da177e4
LT		 515 case PRID_REV_VR4111:
516 c->cputype = CPU_VR4111;
cea7e2df 517 __cpu_name[cpu] = "NEC VR4111";
1da177e4 518 break;
1da177e4
LT		 519 case PRID_REV_VR4121:
520 c->cputype = CPU_VR4121;
cea7e2df 521 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 522 break;
523 case PRID_REV_VR4122:
cea7e2df 524 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 525 c->cputype = CPU_VR4122;
cea7e2df
RB		 526 __cpu_name[cpu] = "NEC VR4122";
527 } else {
1da177e4 528 c->cputype = CPU_VR4181A;
cea7e2df
RB		 529 __cpu_name[cpu] = "NEC VR4181A";
530 }
1da177e4
LT		 531 break;
532 case PRID_REV_VR4130:
cea7e2df 533 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 534 c->cputype = CPU_VR4131;
cea7e2df
RB		 535 __cpu_name[cpu] = "NEC VR4131";
536 } else {
1da177e4 537 c->cputype = CPU_VR4133;
9f91e506 538 c->options |= MIPS_CPU_LLSC;
cea7e2df
RB		 539 __cpu_name[cpu] = "NEC VR4133";
540 }
1da177e4
LT		 541 break;
542 default:
543 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
544 c->cputype = CPU_VR41XX;
cea7e2df 545 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 546 break;
547 }
1da177e4
LT		 548 break;
549 case PRID_IMP_R4300:
550 c->cputype = CPU_R4300;
cea7e2df 551 __cpu_name[cpu] = "R4300";
a96102be 552 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 553 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 554 MIPS_CPU_LLSC;
1da177e4
LT		 555 c->tlbsize = 32;
556 break;
557 case PRID_IMP_R4600:
558 c->cputype = CPU_R4600;
cea7e2df 559 __cpu_name[cpu] = "R4600";
a96102be 560 set_isa(c, MIPS_CPU_ISA_III);
075e7502
TS		 561 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
562 MIPS_CPU_LLSC;
1da177e4
LT		 563 c->tlbsize = 48;
564 break;
565 #if 0
03751e79 566 case PRID_IMP_R4650:
1da177e4
LT		 567 /*
568 * This processor doesn't have an MMU, so it's not
569 * "real easy" to run Linux on it. It is left purely
570 * for documentation. Commented out because it shares
571 * it's c0_prid id number with the TX3900.
572 */
a3dddd56 573 c->cputype = CPU_R4650;
cea7e2df 574 __cpu_name[cpu] = "R4650";
a96102be 575 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 576 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 577 c->tlbsize = 48;
1da177e4
LT		 578 break;
579 #endif
580 case PRID_IMP_TX39:
02cf2119 581 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 582
583 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
584 c->cputype = CPU_TX3927;
cea7e2df 585 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 586 c->tlbsize = 64;
587 } else {
8ff374b9 588 switch (c->processor_id & PRID_REV_MASK) {
1da177e4
LT		 589 case PRID_REV_TX3912:
590 c->cputype = CPU_TX3912;
cea7e2df 591 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 592 c->tlbsize = 32;
593 break;
594 case PRID_REV_TX3922:
595 c->cputype = CPU_TX3922;
cea7e2df 596 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 597 c->tlbsize = 64;
598 break;
1da177e4
LT		 599 }
600 }
601 break;
602 case PRID_IMP_R4700:
603 c->cputype = CPU_R4700;
cea7e2df 604 __cpu_name[cpu] = "R4700";
a96102be 605 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 606 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 607 MIPS_CPU_LLSC;
1da177e4
LT		 608 c->tlbsize = 48;
609 break;
610 case PRID_IMP_TX49:
611 c->cputype = CPU_TX49XX;
cea7e2df 612 __cpu_name[cpu] = "R49XX";
a96102be 613 set_isa(c, MIPS_CPU_ISA_III);
1da177e4
LT		 614 c->options = R4K_OPTS | MIPS_CPU_LLSC;
615 if (!(c->processor_id & 0x08))
616 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
617 c->tlbsize = 48;
618 break;
619 case PRID_IMP_R5000:
620 c->cputype = CPU_R5000;
cea7e2df 621 __cpu_name[cpu] = "R5000";
a96102be 622 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 623 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 624 MIPS_CPU_LLSC;
1da177e4
LT		 625 c->tlbsize = 48;
626 break;
627 case PRID_IMP_R5432:
628 c->cputype = CPU_R5432;
cea7e2df 629 __cpu_name[cpu] = "R5432";
a96102be 630 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 631 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 632 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 633 c->tlbsize = 48;
634 break;
635 case PRID_IMP_R5500:
636 c->cputype = CPU_R5500;
cea7e2df 637 __cpu_name[cpu] = "R5500";
a96102be 638 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 639 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 640 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 641 c->tlbsize = 48;
642 break;
643 case PRID_IMP_NEVADA:
644 c->cputype = CPU_NEVADA;
cea7e2df 645 __cpu_name[cpu] = "Nevada";
a96102be 646 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 647 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 648 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 649 c->tlbsize = 48;
650 break;
651 case PRID_IMP_R6000:
652 c->cputype = CPU_R6000;
cea7e2df 653 __cpu_name[cpu] = "R6000";
a96102be 654 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 655 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 656 MIPS_CPU_LLSC;
1da177e4
LT		 657 c->tlbsize = 32;
658 break;
659 case PRID_IMP_R6000A:
660 c->cputype = CPU_R6000A;
cea7e2df 661 __cpu_name[cpu] = "R6000A";
a96102be 662 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 663 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 664 MIPS_CPU_LLSC;
1da177e4
LT		 665 c->tlbsize = 32;
666 break;
667 case PRID_IMP_RM7000:
668 c->cputype = CPU_RM7000;
cea7e2df 669 __cpu_name[cpu] = "RM7000";
a96102be 670 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 671 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 672 MIPS_CPU_LLSC;
1da177e4 673 /*
70342287 674 * Undocumented RM7000: Bit 29 in the info register of
1da177e4
LT		 675 * the RM7000 v2.0 indicates if the TLB has 48 or 64
676 * entries.
677 *
70342287
RB		 678 * 29 1 => 64 entry JTLB
679 * 0 => 48 entry JTLB
1da177e4
LT		 680 */
681 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
682 break;
683 case PRID_IMP_RM9000:
684 c->cputype = CPU_RM9000;
cea7e2df 685 __cpu_name[cpu] = "RM9000";
a96102be 686 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 687 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 688 MIPS_CPU_LLSC;
1da177e4
LT		 689 /*
690 * Bit 29 in the info register of the RM9000
691 * indicates if the TLB has 48 or 64 entries.
692 *
70342287
RB		 693 * 29 1 => 64 entry JTLB
694 * 0 => 48 entry JTLB
1da177e4
LT		 695 */
696 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
697 break;
698 case PRID_IMP_R8000:
699 c->cputype = CPU_R8000;
cea7e2df 700 __cpu_name[cpu] = "RM8000";
a96102be 701 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 702 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 703 MIPS_CPU_FPU | MIPS_CPU_32FPR |
704 MIPS_CPU_LLSC;
1da177e4
LT		 705 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
706 break;
707 case PRID_IMP_R10000:
708 c->cputype = CPU_R10000;
cea7e2df 709 __cpu_name[cpu] = "R10000";
a96102be 710 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 711 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 712 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 713 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 714 MIPS_CPU_LLSC;
1da177e4
LT		 715 c->tlbsize = 64;
716 break;
717 case PRID_IMP_R12000:
718 c->cputype = CPU_R12000;
cea7e2df 719 __cpu_name[cpu] = "R12000";
a96102be 720 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 721 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 722 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 723 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 724 MIPS_CPU_LLSC;
1da177e4
LT		 725 c->tlbsize = 64;
726 break;
44d921b2
K		 727 case PRID_IMP_R14000:
728 c->cputype = CPU_R14000;
cea7e2df 729 __cpu_name[cpu] = "R14000";
a96102be 730 set_isa(c, MIPS_CPU_ISA_IV);
44d921b2 731 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 732 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 733 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 734 MIPS_CPU_LLSC;
44d921b2
K		 735 c->tlbsize = 64;
736 break;
2a21c730
FZ		 737 case PRID_IMP_LOONGSON2:
738 c->cputype = CPU_LOONGSON2;
cea7e2df 739 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a
RM		 740
741 switch (c->processor_id & PRID_REV_MASK) {
742 case PRID_REV_LOONGSON2E:
743 set_elf_platform(cpu, "loongson2e");
744 break;
745 case PRID_REV_LOONGSON2F:
746 set_elf_platform(cpu, "loongson2f");
747 break;
748 }
749
a96102be 750 set_isa(c, MIPS_CPU_ISA_III);
2a21c730
FZ		 751 c->options = R4K_OPTS |
752 MIPS_CPU_FPU | MIPS_CPU_LLSC |
753 MIPS_CPU_32FPR;
754 c->tlbsize = 64;
755 break;
2fa36399
KC		 756 case PRID_IMP_LOONGSON1:
757 decode_configs(c);
b4672d37 758
2fa36399 759 c->cputype = CPU_LOONGSON1;
1da177e4 760
2fa36399
KC		 761 switch (c->processor_id & PRID_REV_MASK) {
762 case PRID_REV_LOONGSON1B:
763 __cpu_name[cpu] = "Loongson 1B";
b4672d37 764 break;
b4672d37 765 }
4194318c 766
2fa36399 767 break;
1da177e4 768 }
1da177e4
LT		 769}
770
cea7e2df 771static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 772{
8ff374b9 773 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 774 case PRID_IMP_4KC:
775 c->cputype = CPU_4KC;
cea7e2df 776 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 777 break;
778 case PRID_IMP_4KEC:
2b07bd02
RB		 779 case PRID_IMP_4KECR2:
780 c->cputype = CPU_4KEC;
cea7e2df 781 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 782 break;
1da177e4 783 case PRID_IMP_4KSC:
8afcb5d8 784 case PRID_IMP_4KSD:
1da177e4 785 c->cputype = CPU_4KSC;
cea7e2df 786 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 787 break;
788 case PRID_IMP_5KC:
789 c->cputype = CPU_5KC;
cea7e2df 790 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4 791 break;
78d4803f
LY		 792 case PRID_IMP_5KE:
793 c->cputype = CPU_5KE;
794 __cpu_name[cpu] = "MIPS 5KE";
795 break;
1da177e4
LT		 796 case PRID_IMP_20KC:
797 c->cputype = CPU_20KC;
cea7e2df 798 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 799 break;
800 case PRID_IMP_24K:
801 c->cputype = CPU_24K;
cea7e2df 802 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4 803 break;
42f3caef
JC		 804 case PRID_IMP_24KE:
805 c->cputype = CPU_24K;
806 __cpu_name[cpu] = "MIPS 24KEc";
807 break;
1da177e4
LT		 808 case PRID_IMP_25KF:
809 c->cputype = CPU_25KF;
cea7e2df 810 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 811 break;
bbc7f22f
RB		 812 case PRID_IMP_34K:
813 c->cputype = CPU_34K;
cea7e2df 814 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 815 break;
c620953c
CD		 816 case PRID_IMP_74K:
817 c->cputype = CPU_74K;
cea7e2df 818 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 819 break;
113c62d9
SH		 820 case PRID_IMP_M14KC:
821 c->cputype = CPU_M14KC;
822 __cpu_name[cpu] = "MIPS M14Kc";
823 break;
f8fa4811
SH		 824 case PRID_IMP_M14KEC:
825 c->cputype = CPU_M14KEC;
826 __cpu_name[cpu] = "MIPS M14KEc";
827 break;
39b8d525
RB		 828 case PRID_IMP_1004K:
829 c->cputype = CPU_1004K;
cea7e2df 830 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 831 break;
006a851b 832 case PRID_IMP_1074K:
442e14a2 833 c->cputype = CPU_1074K;
006a851b
SH		 834 __cpu_name[cpu] = "MIPS 1074Kc";
835 break;
b5f065e7
LY		 836 case PRID_IMP_INTERAPTIV_UP:
837 c->cputype = CPU_INTERAPTIV;
838 __cpu_name[cpu] = "MIPS interAptiv";
839 break;
840 case PRID_IMP_INTERAPTIV_MP:
841 c->cputype = CPU_INTERAPTIV;
842 __cpu_name[cpu] = "MIPS interAptiv (multi)";
843 break;
b0d4d300
LY		 844 case PRID_IMP_PROAPTIV_UP:
845 c->cputype = CPU_PROAPTIV;
846 __cpu_name[cpu] = "MIPS proAptiv";
847 break;
848 case PRID_IMP_PROAPTIV_MP:
849 c->cputype = CPU_PROAPTIV;
850 __cpu_name[cpu] = "MIPS proAptiv (multi)";
851 break;
829dcc0a
JH		 852 case PRID_IMP_P5600:
853 c->cputype = CPU_P5600;
854 __cpu_name[cpu] = "MIPS P5600";
855 break;
1da177e4 856 }
0b6d497f 857
75b5b5e0
LY		 858 decode_configs(c);
859
0b6d497f 860 spram_config();
1da177e4
LT		 861}
862
cea7e2df 863static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 864{
4194318c 865 decode_configs(c);
8ff374b9 866 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 867 case PRID_IMP_AU1_REV1:
868 case PRID_IMP_AU1_REV2:
270717a8 869 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 870 switch ((c->processor_id >> 24) & 0xff) {
871 case 0:
cea7e2df 872 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 873 break;
874 case 1:
cea7e2df 875 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 876 break;
877 case 2:
cea7e2df 878 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 879 break;
880 case 3:
cea7e2df 881 __cpu_name[cpu] = "Au1550";
1da177e4 882 break;
e3ad1c23 883 case 4:
cea7e2df 884 __cpu_name[cpu] = "Au1200";
8ff374b9 885 if ((c->processor_id & PRID_REV_MASK) == 2)
cea7e2df 886 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 887 break;
888 case 5:
cea7e2df 889 __cpu_name[cpu] = "Au1210";
e3ad1c23 890 break;
1da177e4 891 default:
270717a8 892 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 893 break;
894 }
1da177e4
LT		 895 break;
896 }
897}
898
cea7e2df 899static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 900{
4194318c 901 decode_configs(c);
02cf2119 902
8ff374b9 903 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 904 case PRID_IMP_SB1:
905 c->cputype = CPU_SB1;
cea7e2df 906 __cpu_name[cpu] = "SiByte SB1";
1da177e4 907 /* FPU in pass1 is known to have issues. */
8ff374b9 908 if ((c->processor_id & PRID_REV_MASK) < 0x02)
010b853b 909 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 910 break;
93ce2f52
AI		 911 case PRID_IMP_SB1A:
912 c->cputype = CPU_SB1A;
cea7e2df 913 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 914 break;
1da177e4
LT		 915 }
916}
917
cea7e2df 918static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 919{
4194318c 920 decode_configs(c);
8ff374b9 921 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 922 case PRID_IMP_SR71000:
923 c->cputype = CPU_SR71000;
cea7e2df 924 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 925 c->scache.ways = 8;
926 c->tlbsize = 64;
927 break;
928 }
929}
930
cea7e2df 931static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 932{
933 decode_configs(c);
8ff374b9 934 switch (c->processor_id & PRID_IMP_MASK) {
bdf21b18
PP		 935 case PRID_IMP_PR4450:
936 c->cputype = CPU_PR4450;
cea7e2df 937 __cpu_name[cpu] = "Philips PR4450";
a96102be 938 set_isa(c, MIPS_CPU_ISA_M32R1);
bdf21b18 939 break;
bdf21b18
PP		 940 }
941}
942
cea7e2df 943static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 944{
945 decode_configs(c);
8ff374b9 946 switch (c->processor_id & PRID_IMP_MASK) {
190fca3e
KC		 947 case PRID_IMP_BMIPS32_REV4:
948 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 949 c->cputype = CPU_BMIPS32;
950 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 951 set_elf_platform(cpu, "bmips32");
602977b0
KC		 952 break;
953 case PRID_IMP_BMIPS3300:
954 case PRID_IMP_BMIPS3300_ALT:
955 case PRID_IMP_BMIPS3300_BUG:
956 c->cputype = CPU_BMIPS3300;
957 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 958 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 959 break;
960 case PRID_IMP_BMIPS43XX: {
8ff374b9 961 int rev = c->processor_id & PRID_REV_MASK;
602977b0
KC		 962
963 if (rev >= PRID_REV_BMIPS4380_LO &&
964 rev <= PRID_REV_BMIPS4380_HI) {
965 c->cputype = CPU_BMIPS4380;
966 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 967 set_elf_platform(cpu, "bmips4380");
602977b0
KC		 968 } else {
969 c->cputype = CPU_BMIPS4350;
970 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 971 set_elf_platform(cpu, "bmips4350");
602977b0 972 }
0de663ef 973 break;
602977b0
KC		 974 }
975 case PRID_IMP_BMIPS5000:
976 c->cputype = CPU_BMIPS5000;
977 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 978 set_elf_platform(cpu, "bmips5000");
602977b0 979 c->options |= MIPS_CPU_ULRI;
0de663ef 980 break;
1c0c13eb
AJ		 981 }
982}
983
0dd4781b
DD		 984static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
985{
986 decode_configs(c);
8ff374b9 987 switch (c->processor_id & PRID_IMP_MASK) {
0dd4781b
DD		 988 case PRID_IMP_CAVIUM_CN38XX:
989 case PRID_IMP_CAVIUM_CN31XX:
990 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 991 c->cputype = CPU_CAVIUM_OCTEON;
992 __cpu_name[cpu] = "Cavium Octeon";
993 goto platform;
0dd4781b
DD		 994 case PRID_IMP_CAVIUM_CN58XX:
995 case PRID_IMP_CAVIUM_CN56XX:
996 case PRID_IMP_CAVIUM_CN50XX:
997 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 998 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
999 __cpu_name[cpu] = "Cavium Octeon+";
1000platform:
c094c99e 1001 set_elf_platform(cpu, "octeon");
0dd4781b 1002 break;
a1431b61 1003 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 1004 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 1005 case PRID_IMP_CAVIUM_CN66XX:
1006 case PRID_IMP_CAVIUM_CN68XX:
af04bb85 1007 case PRID_IMP_CAVIUM_CNF71XX:
0e56b385
DD		 1008 c->cputype = CPU_CAVIUM_OCTEON2;
1009 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 1010 set_elf_platform(cpu, "octeon2");
0e56b385 1011 break;
af04bb85
DD		 1012 case PRID_IMP_CAVIUM_CN70XX:
1013 case PRID_IMP_CAVIUM_CN78XX:
1014 c->cputype = CPU_CAVIUM_OCTEON3;
1015 __cpu_name[cpu] = "Cavium Octeon III";
1016 set_elf_platform(cpu, "octeon3");
1017 break;
0dd4781b
DD		 1018 default:
1019 printk(KERN_INFO "Unknown Octeon chip!\n");
1020 c->cputype = CPU_UNKNOWN;
1021 break;
1022 }
1023}
1024
83ccf69d
LPC		 1025static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1026{
1027 decode_configs(c);
1028 /* JZRISC does not implement the CP0 counter. */
1029 c->options &= ~MIPS_CPU_COUNTER;
8ff374b9 1030 switch (c->processor_id & PRID_IMP_MASK) {
83ccf69d
LPC		 1031 case PRID_IMP_JZRISC:
1032 c->cputype = CPU_JZRISC;
1033 __cpu_name[cpu] = "Ingenic JZRISC";
1034 break;
1035 default:
1036 panic("Unknown Ingenic Processor ID!");
1037 break;
1038 }
1039}
1040
a7117c6b
J		 1041static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1042{
1043 decode_configs(c);
1044
8ff374b9 1045 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
809f36c6
ML		 1046 c->cputype = CPU_ALCHEMY;
1047 __cpu_name[cpu] = "Au1300";
1048 /* following stuff is not for Alchemy */
1049 return;
1050 }
1051
70342287
RB		 1052 c->options = (MIPS_CPU_TLB |
1053 MIPS_CPU_4KEX |
a7117c6b 1054 MIPS_CPU_COUNTER |
70342287
RB		 1055 MIPS_CPU_DIVEC |
1056 MIPS_CPU_WATCH |
1057 MIPS_CPU_EJTAG |
a7117c6b
J		 1058 MIPS_CPU_LLSC);
1059
8ff374b9 1060 switch (c->processor_id & PRID_IMP_MASK) {
4ca86a2f 1061 case PRID_IMP_NETLOGIC_XLP2XX:
8907c55e 1062 case PRID_IMP_NETLOGIC_XLP9XX:
4ca86a2f
J		 1063 c->cputype = CPU_XLP;
1064 __cpu_name[cpu] = "Broadcom XLPII";
1065 break;
1066
2aa54b20
J		 1067 case PRID_IMP_NETLOGIC_XLP8XX:
1068 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 1069 c->cputype = CPU_XLP;
1070 __cpu_name[cpu] = "Netlogic XLP";
1071 break;
1072
a7117c6b
J		 1073 case PRID_IMP_NETLOGIC_XLR732:
1074 case PRID_IMP_NETLOGIC_XLR716:
1075 case PRID_IMP_NETLOGIC_XLR532:
1076 case PRID_IMP_NETLOGIC_XLR308:
1077 case PRID_IMP_NETLOGIC_XLR532C:
1078 case PRID_IMP_NETLOGIC_XLR516C:
1079 case PRID_IMP_NETLOGIC_XLR508C:
1080 case PRID_IMP_NETLOGIC_XLR308C:
1081 c->cputype = CPU_XLR;
1082 __cpu_name[cpu] = "Netlogic XLR";
1083 break;
1084
1085 case PRID_IMP_NETLOGIC_XLS608:
1086 case PRID_IMP_NETLOGIC_XLS408:
1087 case PRID_IMP_NETLOGIC_XLS404:
1088 case PRID_IMP_NETLOGIC_XLS208:
1089 case PRID_IMP_NETLOGIC_XLS204:
1090 case PRID_IMP_NETLOGIC_XLS108:
1091 case PRID_IMP_NETLOGIC_XLS104:
1092 case PRID_IMP_NETLOGIC_XLS616B:
1093 case PRID_IMP_NETLOGIC_XLS608B:
1094 case PRID_IMP_NETLOGIC_XLS416B:
1095 case PRID_IMP_NETLOGIC_XLS412B:
1096 case PRID_IMP_NETLOGIC_XLS408B:
1097 case PRID_IMP_NETLOGIC_XLS404B:
1098 c->cputype = CPU_XLR;
1099 __cpu_name[cpu] = "Netlogic XLS";
1100 break;
1101
1102 default:
a3d4fb2d 1103 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 1104 c->processor_id);
1105 c->cputype = CPU_XLR;
1106 break;
1107 }
1108
a3d4fb2d 1109 if (c->cputype == CPU_XLP) {
a96102be 1110 set_isa(c, MIPS_CPU_ISA_M64R2);
a3d4fb2d
J		 1111 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1112 /* This will be updated again after all threads are woken up */
1113 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1114 } else {
a96102be 1115 set_isa(c, MIPS_CPU_ISA_M64R1);
a3d4fb2d
J		 1116 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1117 }
7777b939 1118 c->kscratch_mask = 0xf;
a7117c6b
J		 1119}
1120
949e51be
DD		 1121#ifdef CONFIG_64BIT
1122/* For use by uaccess.h */
1123u64 __ua_limit;
1124EXPORT_SYMBOL(__ua_limit);
1125#endif
1126
9966db25 1127const char *__cpu_name[NR_CPUS];
874fd3b5 1128const char *__elf_platform;
9966db25 1129
078a55fc 1130void cpu_probe(void)
1da177e4
LT		 1131{
1132 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 1133 unsigned int cpu = smp_processor_id();
1da177e4 1134
70342287 1135 c->processor_id = PRID_IMP_UNKNOWN;
1da177e4
LT		 1136 c->fpu_id = FPIR_IMP_NONE;
1137 c->cputype = CPU_UNKNOWN;
1138
1139 c->processor_id = read_c0_prid();
8ff374b9 1140 switch (c->processor_id & PRID_COMP_MASK) {
1da177e4 1141 case PRID_COMP_LEGACY:
cea7e2df 1142 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1143 break;
1144 case PRID_COMP_MIPS:
cea7e2df 1145 cpu_probe_mips(c, cpu);
1da177e4
LT		 1146 break;
1147 case PRID_COMP_ALCHEMY:
cea7e2df 1148 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1149 break;
1150 case PRID_COMP_SIBYTE:
cea7e2df 1151 cpu_probe_sibyte(c, cpu);
1da177e4 1152 break;
1c0c13eb 1153 case PRID_COMP_BROADCOM:
cea7e2df 1154 cpu_probe_broadcom(c, cpu);
1c0c13eb 1155 break;
1da177e4 1156 case PRID_COMP_SANDCRAFT:
cea7e2df 1157 cpu_probe_sandcraft(c, cpu);
1da177e4 1158 break;
a92b0588 1159 case PRID_COMP_NXP:
cea7e2df 1160 cpu_probe_nxp(c, cpu);
a3dddd56 1161 break;
0dd4781b
DD		 1162 case PRID_COMP_CAVIUM:
1163 cpu_probe_cavium(c, cpu);
1164 break;
83ccf69d
LPC		 1165 case PRID_COMP_INGENIC:
1166 cpu_probe_ingenic(c, cpu);
1167 break;
a7117c6b
J		 1168 case PRID_COMP_NETLOGIC:
1169 cpu_probe_netlogic(c, cpu);
1170 break;
1da177e4 1171 }
dec8b1ca 1172
cea7e2df
RB		 1173 BUG_ON(!__cpu_name[cpu]);
1174 BUG_ON(c->cputype == CPU_UNKNOWN);
1175
dec8b1ca
FBH		 1176 /*
1177 * Platform code can force the cpu type to optimize code
1178 * generation. In that case be sure the cpu type is correctly
1179 * manually setup otherwise it could trigger some nasty bugs.
1180 */
1181 BUG_ON(current_cpu_type() != c->cputype);
1182
0103d23f
KC		 1183 if (mips_fpu_disabled)
1184 c->options &= ~MIPS_CPU_FPU;
1185
1186 if (mips_dsp_disabled)
ee80f7c7 1187 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f 1188
4194318c 1189 if (c->options & MIPS_CPU_FPU) {
1da177e4 1190 c->fpu_id = cpu_get_fpu_id();
4194318c 1191
adb37892
DCZ		 1192 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1193 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
4194318c
RB		 1194 if (c->fpu_id & MIPS_FPIR_3D)
1195 c->ases |= MIPS_ASE_MIPS3D;
1196 }
1197 }
9966db25 1198
da4b62cd 1199 if (cpu_has_mips_r2) {
f6771dbb 1200 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
da4b62cd
AC		 1201 /* R2 has Performance Counter Interrupt indicator */
1202 c->options |= MIPS_CPU_PCI;
1203 }
f6771dbb
RB		 1204 else
1205 c->srsets = 1;
91dfc423 1206
a8ad1367 1207 if (cpu_has_msa) {
a5e9a69e 1208 c->msa_id = cpu_get_msa_id();
a8ad1367
PB		 1209 WARN(c->msa_id & MSA_IR_WRPF,
1210 "Vector register partitioning unimplemented!");
1211 }
a5e9a69e 1212
91dfc423 1213 cpu_probe_vmbits(c);
949e51be
DD		 1214
1215#ifdef CONFIG_64BIT
1216 if (cpu == 0)
1217 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1218#endif
1da177e4
LT		 1219}
1220
078a55fc 1221void cpu_report(void)
1da177e4
LT		 1222{
1223 struct cpuinfo_mips *c = &current_cpu_data;
1224
d9f897c9
LY		 1225 pr_info("CPU%d revision is: %08x (%s)\n",
1226 smp_processor_id(), c->processor_id, cpu_name_string());
1da177e4 1227 if (c->options & MIPS_CPU_FPU)
9966db25 1228 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
a5e9a69e
PB		 1229 if (cpu_has_msa)
1230 pr_info("MSA revision is: %08x\n", c->msa_id);
1da177e4 1231}
Linux 6.x block layer and io_uring tree(s)