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MIPS: Separate MAAR V bit into VL and VH for XPA
[linux-2.6-block.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
70342287 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4 22#include <asm/cpu.h>
f6843626 23#include <asm/cpu-features.h>
69f24d17 24#include <asm/cpu-type.h>
1da177e4
LT		 25#include <asm/fpu.h>
26#include <asm/mipsregs.h>
30ee615b 27#include <asm/mipsmtregs.h>
a5e9a69e 28#include <asm/msa.h>
654f57bf 29#include <asm/watch.h>
06372a63 30#include <asm/elf.h>
4f12b91d 31#include <asm/pgtable-bits.h>
a074f0e8 32#include <asm/spram.h>
7c0f6ba6 33#include <linux/uaccess.h>
949e51be 34
e14f1db7
PB		 35/* Hardware capabilities */
36unsigned int elf_hwcap __read_mostly;
37
7aecd5ca
MR		 38/*
39 * Get the FPU Implementation/Revision.
40 */
41static inline unsigned long cpu_get_fpu_id(void)
42{
43 unsigned long tmp, fpu_id;
44
45 tmp = read_c0_status();
46 __enable_fpu(FPU_AS_IS);
47 fpu_id = read_32bit_cp1_register(CP1_REVISION);
48 write_c0_status(tmp);
49 return fpu_id;
50}
51
52/*
53 * Check if the CPU has an external FPU.
54 */
55static inline int __cpu_has_fpu(void)
56{
57 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
58}
59
60static inline unsigned long cpu_get_msa_id(void)
61{
62 unsigned long status, msa_id;
63
64 status = read_c0_status();
65 __enable_fpu(FPU_64BIT);
66 enable_msa();
67 msa_id = read_msa_ir();
68 disable_msa();
69 write_c0_status(status);
70 return msa_id;
71}
72
9b26616c
MR		 73/*
74 * Determine the FCSR mask for FPU hardware.
75 */
76static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
77{
78 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
79
90b712dd 80 fcsr = c->fpu_csr31;
9b26616c
MR		 81 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
82
83 sr = read_c0_status();
84 __enable_fpu(FPU_AS_IS);
85
9b26616c
MR		 86 fcsr0 = fcsr & mask;
87 write_32bit_cp1_register(CP1_STATUS, fcsr0);
88 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
89
90 fcsr1 = fcsr | ~mask;
91 write_32bit_cp1_register(CP1_STATUS, fcsr1);
92 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
93
94 write_32bit_cp1_register(CP1_STATUS, fcsr);
95
96 write_c0_status(sr);
97
98 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
99}
100
93adeaf6
MR		 101/*
102 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
103 * supported by FPU hardware.
104 */
105static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
106{
107 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
108 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
109 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
110 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
111
112 sr = read_c0_status();
113 __enable_fpu(FPU_AS_IS);
114
115 fir = read_32bit_cp1_register(CP1_REVISION);
116 if (fir & MIPS_FPIR_HAS2008) {
117 fcsr = read_32bit_cp1_register(CP1_STATUS);
118
119 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
120 write_32bit_cp1_register(CP1_STATUS, fcsr0);
121 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
122
123 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
124 write_32bit_cp1_register(CP1_STATUS, fcsr1);
125 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
126
127 write_32bit_cp1_register(CP1_STATUS, fcsr);
128
129 if (!(fcsr0 & FPU_CSR_NAN2008))
130 c->options |= MIPS_CPU_NAN_LEGACY;
131 if (fcsr1 & FPU_CSR_NAN2008)
132 c->options |= MIPS_CPU_NAN_2008;
133
134 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
135 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
136 else
137 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
138
139 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
140 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
141 else
142 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
143 } else {
144 c->options |= MIPS_CPU_NAN_LEGACY;
145 }
146
147 write_c0_status(sr);
148 } else {
149 c->options |= MIPS_CPU_NAN_LEGACY;
150 }
151}
152
153/*
503943e0
MR		 154 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
155 * ABS.fmt/NEG.fmt execution mode.
156 */
157static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
158
159/*
160 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
161 * to support by the FPU emulator according to the IEEE 754 conformance
162 * mode selected. Note that "relaxed" straps the emulator so that it
163 * allows 2008-NaN binaries even for legacy processors.
93adeaf6
MR		 164 */
165static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
166{
503943e0 167 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
93adeaf6 168 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
503943e0
MR		 169 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
170
171 switch (ieee754) {
172 case STRICT:
173 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
174 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
175 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
176 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
177 } else {
178 c->options |= MIPS_CPU_NAN_LEGACY;
179 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
180 }
181 break;
182 case LEGACY:
93adeaf6
MR		 183 c->options |= MIPS_CPU_NAN_LEGACY;
184 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
503943e0
MR		 185 break;
186 case STD2008:
187 c->options |= MIPS_CPU_NAN_2008;
188 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
189 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
190 break;
191 case RELAXED:
192 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
193 break;
93adeaf6
MR		 194 }
195}
196
503943e0
MR		 197/*
198 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
199 * according to the "ieee754=" parameter.
200 */
201static void cpu_set_nan_2008(struct cpuinfo_mips *c)
202{
203 switch (ieee754) {
204 case STRICT:
205 mips_use_nan_legacy = !!cpu_has_nan_legacy;
206 mips_use_nan_2008 = !!cpu_has_nan_2008;
207 break;
208 case LEGACY:
209 mips_use_nan_legacy = !!cpu_has_nan_legacy;
210 mips_use_nan_2008 = !cpu_has_nan_legacy;
211 break;
212 case STD2008:
213 mips_use_nan_legacy = !cpu_has_nan_2008;
214 mips_use_nan_2008 = !!cpu_has_nan_2008;
215 break;
216 case RELAXED:
217 mips_use_nan_legacy = true;
218 mips_use_nan_2008 = true;
219 break;
220 }
221}
222
223/*
224 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
225 * settings:
226 *
227 * strict: accept binaries that request a NaN encoding supported by the FPU
228 * legacy: only accept legacy-NaN binaries
229 * 2008: only accept 2008-NaN binaries
230 * relaxed: accept any binaries regardless of whether supported by the FPU
231 */
232static int __init ieee754_setup(char *s)
233{
234 if (!s)
235 return -1;
236 else if (!strcmp(s, "strict"))
237 ieee754 = STRICT;
238 else if (!strcmp(s, "legacy"))
239 ieee754 = LEGACY;
240 else if (!strcmp(s, "2008"))
241 ieee754 = STD2008;
242 else if (!strcmp(s, "relaxed"))
243 ieee754 = RELAXED;
244 else
245 return -1;
246
247 if (!(boot_cpu_data.options & MIPS_CPU_FPU))
248 cpu_set_nofpu_2008(&boot_cpu_data);
249 cpu_set_nan_2008(&boot_cpu_data);
250
251 return 0;
252}
253
254early_param("ieee754", ieee754_setup);
255
f6843626
MR		 256/*
257 * Set the FIR feature flags for the FPU emulator.
258 */
259static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
260{
261 u32 value;
262
263 value = 0;
264 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
265 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
266 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
267 value |= MIPS_FPIR_D | MIPS_FPIR_S;
268 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
269 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
270 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
90d53a91
MR		 271 if (c->options & MIPS_CPU_NAN_2008)
272 value |= MIPS_FPIR_HAS2008;
f6843626
MR		 273 c->fpu_id = value;
274}
275
9b26616c
MR		 276/* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
277static unsigned int mips_nofpu_msk31;
278
7aecd5ca
MR		 279/*
280 * Set options for FPU hardware.
281 */
282static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
283{
284 c->fpu_id = cpu_get_fpu_id();
285 mips_nofpu_msk31 = c->fpu_msk31;
286
287 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
288 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
289 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
290 if (c->fpu_id & MIPS_FPIR_3D)
291 c->ases |= MIPS_ASE_MIPS3D;
4e87580e
JH		 292 if (c->fpu_id & MIPS_FPIR_UFRP)
293 c->options |= MIPS_CPU_UFR;
7aecd5ca
MR		 294 if (c->fpu_id & MIPS_FPIR_FREP)
295 c->options |= MIPS_CPU_FRE;
296 }
297
298 cpu_set_fpu_fcsr_mask(c);
93adeaf6 299 cpu_set_fpu_2008(c);
503943e0 300 cpu_set_nan_2008(c);
7aecd5ca
MR		 301}
302
303/*
304 * Set options for the FPU emulator.
305 */
306static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
307{
308 c->options &= ~MIPS_CPU_FPU;
309 c->fpu_msk31 = mips_nofpu_msk31;
310
93adeaf6 311 cpu_set_nofpu_2008(c);
503943e0 312 cpu_set_nan_2008(c);
7aecd5ca
MR		 313 cpu_set_nofpu_id(c);
314}
315
078a55fc 316static int mips_fpu_disabled;
0103d23f
KC		 317
318static int __init fpu_disable(char *s)
319{
7aecd5ca 320 cpu_set_nofpu_opts(&boot_cpu_data);
0103d23f
KC		 321 mips_fpu_disabled = 1;
322
323 return 1;
324}
325
326__setup("nofpu", fpu_disable);
327
078a55fc 328int mips_dsp_disabled;
0103d23f
KC		 329
330static int __init dsp_disable(char *s)
331{
ee80f7c7 332 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f
KC		 333 mips_dsp_disabled = 1;
334
335 return 1;
336}
337
338__setup("nodsp", dsp_disable);
339
3d528b32
MC		 340static int mips_htw_disabled;
341
342static int __init htw_disable(char *s)
343{
344 mips_htw_disabled = 1;
345 cpu_data[0].options &= ~MIPS_CPU_HTW;
346 write_c0_pwctl(read_c0_pwctl() &
347 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
348
349 return 1;
350}
351
352__setup("nohtw", htw_disable);
353
97f4ad29
MC		 354static int mips_ftlb_disabled;
355static int mips_has_ftlb_configured;
356
ebd0e0f5
PB		 357enum ftlb_flags {
358 FTLB_EN = 1 << 0,
359 FTLB_SET_PROB = 1 << 1,
360};
361
362static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
97f4ad29
MC		 363
364static int __init ftlb_disable(char *s)
365{
366 unsigned int config4, mmuextdef;
367
368 /*
369 * If the core hasn't done any FTLB configuration, there is nothing
370 * for us to do here.
371 */
372 if (!mips_has_ftlb_configured)
373 return 1;
374
375 /* Disable it in the boot cpu */
912708c2
MC		 376 if (set_ftlb_enable(&cpu_data[0], 0)) {
377 pr_warn("Can't turn FTLB off\n");
378 return 1;
379 }
97f4ad29 380
97f4ad29
MC		 381 config4 = read_c0_config4();
382
383 /* Check that FTLB has been disabled */
384 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
385 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
386 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
387 /* This should never happen */
388 pr_warn("FTLB could not be disabled!\n");
389 return 1;
390 }
391
392 mips_ftlb_disabled = 1;
393 mips_has_ftlb_configured = 0;
394
395 /*
396 * noftlb is mainly used for debug purposes so print
397 * an informative message instead of using pr_debug()
398 */
399 pr_info("FTLB has been disabled\n");
400
401 /*
402 * Some of these bits are duplicated in the decode_config4.
403 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
404 * once FTLB has been disabled so undo what decode_config4 did.
405 */
406 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
407 cpu_data[0].tlbsizeftlbsets;
408 cpu_data[0].tlbsizeftlbsets = 0;
409 cpu_data[0].tlbsizeftlbways = 0;
410
411 return 1;
412}
413
414__setup("noftlb", ftlb_disable);
415
416
9267a30d
MSJ		 417static inline void check_errata(void)
418{
419 struct cpuinfo_mips *c = &current_cpu_data;
420
69f24d17 421 switch (current_cpu_type()) {
9267a30d
MSJ		 422 case CPU_34K:
423 /*
424 * Erratum "RPS May Cause Incorrect Instruction Execution"
b633648c 425 * This code only handles VPE0, any SMP/RTOS code
9267a30d
MSJ		 426 * making use of VPE1 will be responsable for that VPE.
427 */
428 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
429 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
430 break;
431 default:
432 break;
433 }
434}
435
1da177e4
LT		 436void __init check_bugs32(void)
437{
9267a30d 438 check_errata();
1da177e4
LT		 439}
440
441/*
442 * Probe whether cpu has config register by trying to play with
443 * alternate cache bit and see whether it matters.
444 * It's used by cpu_probe to distinguish between R3000A and R3081.
445 */
446static inline int cpu_has_confreg(void)
447{
448#ifdef CONFIG_CPU_R3000
449 extern unsigned long r3k_cache_size(unsigned long);
450 unsigned long size1, size2;
451 unsigned long cfg = read_c0_conf();
452
453 size1 = r3k_cache_size(ST0_ISC);
454 write_c0_conf(cfg ^ R30XX_CONF_AC);
455 size2 = r3k_cache_size(ST0_ISC);
456 write_c0_conf(cfg);
457 return size1 != size2;
458#else
459 return 0;
460#endif
461}
462
c094c99e
RM		 463static inline void set_elf_platform(int cpu, const char *plat)
464{
465 if (cpu == 0)
466 __elf_platform = plat;
467}
468
91dfc423
GR		 469static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
470{
471#ifdef __NEED_VMBITS_PROBE
5b7efa89 472 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 473 back_to_back_c0_hazard();
5b7efa89 474 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 475#endif
476}
477
078a55fc 478static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
a96102be
SH		 479{
480 switch (isa) {
481 case MIPS_CPU_ISA_M64R2:
482 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
483 case MIPS_CPU_ISA_M64R1:
484 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
485 case MIPS_CPU_ISA_V:
486 c->isa_level |= MIPS_CPU_ISA_V;
487 case MIPS_CPU_ISA_IV:
488 c->isa_level |= MIPS_CPU_ISA_IV;
489 case MIPS_CPU_ISA_III:
1990e542 490 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
a96102be
SH		 491 break;
492
8b8aa636
LY		 493 /* R6 incompatible with everything else */
494 case MIPS_CPU_ISA_M64R6:
495 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
496 case MIPS_CPU_ISA_M32R6:
497 c->isa_level |= MIPS_CPU_ISA_M32R6;
498 /* Break here so we don't add incompatible ISAs */
499 break;
a96102be
SH		 500 case MIPS_CPU_ISA_M32R2:
501 c->isa_level |= MIPS_CPU_ISA_M32R2;
502 case MIPS_CPU_ISA_M32R1:
503 c->isa_level |= MIPS_CPU_ISA_M32R1;
504 case MIPS_CPU_ISA_II:
505 c->isa_level |= MIPS_CPU_ISA_II;
a96102be
SH		 506 break;
507 }
508}
509
078a55fc 510static char unknown_isa[] = KERN_ERR \
2fa36399
KC		 511 "Unsupported ISA type, c0.config0: %d.";
512
cf0a8aa0
MC		 513static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
514{
515
516 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
517
518 /*
519 * 0 = All TLBWR instructions go to FTLB
520 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
521 * FTLB and 1 goes to the VTLB.
522 * 2 = 7:1: As above with 7:1 ratio.
523 * 3 = 3:1: As above with 3:1 ratio.
524 *
525 * Use the linear midpoint as the probability threshold.
526 */
527 if (probability >= 12)
528 return 1;
529 else if (probability >= 6)
530 return 2;
531 else
532 /*
533 * So FTLB is less than 4 times bigger than VTLB.
534 * A 3:1 ratio can still be useful though.
535 */
536 return 3;
537}
538
ebd0e0f5 539static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
75b5b5e0 540{
20a7f7e5 541 unsigned int config;
d83b0e82
JH		 542
543 /* It's implementation dependent how the FTLB can be enabled */
544 switch (c->cputype) {
545 case CPU_PROAPTIV:
546 case CPU_P5600:
1091bfa2 547 case CPU_P6600:
d83b0e82 548 /* proAptiv & related cores use Config6 to enable the FTLB */
20a7f7e5 549 config = read_c0_config6();
ebd0e0f5
PB		 550
551 if (flags & FTLB_EN)
552 config |= MIPS_CONF6_FTLBEN;
75b5b5e0 553 else
ebd0e0f5
PB		 554 config &= ~MIPS_CONF6_FTLBEN;
555
556 if (flags & FTLB_SET_PROB) {
557 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
558 config |= calculate_ftlb_probability(c)
559 << MIPS_CONF6_FTLBP_SHIFT;
560 }
561
562 write_c0_config6(config);
67acd8d5 563 back_to_back_c0_hazard();
20a7f7e5
MC		 564 break;
565 case CPU_I6400:
72c70f01 566 /* There's no way to disable the FTLB */
ebd0e0f5
PB		 567 if (!(flags & FTLB_EN))
568 return 1;
569 return 0;
b2edcfc8 570 case CPU_LOONGSON3:
06e4814e
HC		 571 /* Flush ITLB, DTLB, VTLB and FTLB */
572 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
573 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
b2edcfc8
HC		 574 /* Loongson-3 cores use Config6 to enable the FTLB */
575 config = read_c0_config6();
ebd0e0f5 576 if (flags & FTLB_EN)
b2edcfc8
HC		 577 /* Enable FTLB */
578 write_c0_config6(config & ~MIPS_CONF6_FTLBDIS);
579 else
580 /* Disable FTLB */
581 write_c0_config6(config | MIPS_CONF6_FTLBDIS);
582 break;
912708c2
MC		 583 default:
584 return 1;
75b5b5e0 585 }
912708c2
MC		 586
587 return 0;
75b5b5e0
LY		 588}
589
2fa36399
KC		 590static inline unsigned int decode_config0(struct cpuinfo_mips *c)
591{
592 unsigned int config0;
2f6f3136 593 int isa, mt;
2fa36399
KC		 594
595 config0 = read_c0_config();
596
75b5b5e0
LY		 597 /*
598 * Look for Standard TLB or Dual VTLB and FTLB
599 */
2f6f3136
JH		 600 mt = config0 & MIPS_CONF_MT;
601 if (mt == MIPS_CONF_MT_TLB)
2fa36399 602 c->options |= MIPS_CPU_TLB;
2f6f3136
JH		 603 else if (mt == MIPS_CONF_MT_FTLB)
604 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
75b5b5e0 605
2fa36399
KC		 606 isa = (config0 & MIPS_CONF_AT) >> 13;
607 switch (isa) {
608 case 0:
609 switch ((config0 & MIPS_CONF_AR) >> 10) {
610 case 0:
a96102be 611 set_isa(c, MIPS_CPU_ISA_M32R1);
2fa36399
KC		 612 break;
613 case 1:
a96102be 614 set_isa(c, MIPS_CPU_ISA_M32R2);
2fa36399 615 break;
8b8aa636
LY		 616 case 2:
617 set_isa(c, MIPS_CPU_ISA_M32R6);
618 break;
2fa36399
KC		 619 default:
620 goto unknown;
621 }
622 break;
623 case 2:
624 switch ((config0 & MIPS_CONF_AR) >> 10) {
625 case 0:
a96102be 626 set_isa(c, MIPS_CPU_ISA_M64R1);
2fa36399
KC		 627 break;
628 case 1:
a96102be 629 set_isa(c, MIPS_CPU_ISA_M64R2);
2fa36399 630 break;
8b8aa636
LY		 631 case 2:
632 set_isa(c, MIPS_CPU_ISA_M64R6);
633 break;
2fa36399
KC		 634 default:
635 goto unknown;
636 }
637 break;
638 default:
639 goto unknown;
640 }
641
642 return config0 & MIPS_CONF_M;
643
644unknown:
645 panic(unknown_isa, config0);
646}
647
648static inline unsigned int decode_config1(struct cpuinfo_mips *c)
649{
650 unsigned int config1;
651
652 config1 = read_c0_config1();
653
654 if (config1 & MIPS_CONF1_MD)
655 c->ases |= MIPS_ASE_MDMX;
30228c40
JH		 656 if (config1 & MIPS_CONF1_PC)
657 c->options |= MIPS_CPU_PERF;
2fa36399
KC		 658 if (config1 & MIPS_CONF1_WR)
659 c->options |= MIPS_CPU_WATCH;
660 if (config1 & MIPS_CONF1_CA)
661 c->ases |= MIPS_ASE_MIPS16;
662 if (config1 & MIPS_CONF1_EP)
663 c->options |= MIPS_CPU_EJTAG;
664 if (config1 & MIPS_CONF1_FP) {
665 c->options |= MIPS_CPU_FPU;
666 c->options |= MIPS_CPU_32FPR;
667 }
75b5b5e0 668 if (cpu_has_tlb) {
2fa36399 669 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
75b5b5e0
LY		 670 c->tlbsizevtlb = c->tlbsize;
671 c->tlbsizeftlbsets = 0;
672 }
2fa36399
KC		 673
674 return config1 & MIPS_CONF_M;
675}
676
677static inline unsigned int decode_config2(struct cpuinfo_mips *c)
678{
679 unsigned int config2;
680
681 config2 = read_c0_config2();
682
683 if (config2 & MIPS_CONF2_SL)
684 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
685
686 return config2 & MIPS_CONF_M;
687}
688
689static inline unsigned int decode_config3(struct cpuinfo_mips *c)
690{
691 unsigned int config3;
692
693 config3 = read_c0_config3();
694
b2ab4f08 695 if (config3 & MIPS_CONF3_SM) {
2fa36399 696 c->ases |= MIPS_ASE_SMARTMIPS;
f18bdfa1 697 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
b2ab4f08
SH		 698 }
699 if (config3 & MIPS_CONF3_RXI)
700 c->options |= MIPS_CPU_RIXI;
f18bdfa1
JH		 701 if (config3 & MIPS_CONF3_CTXTC)
702 c->options |= MIPS_CPU_CTXTC;
2fa36399
KC		 703 if (config3 & MIPS_CONF3_DSP)
704 c->ases |= MIPS_ASE_DSP;
b5a6455c 705 if (config3 & MIPS_CONF3_DSP2P) {
ee80f7c7 706 c->ases |= MIPS_ASE_DSP2P;
b5a6455c
ZLK		 707 if (cpu_has_mips_r6)
708 c->ases |= MIPS_ASE_DSP3;
709 }
2fa36399
KC		 710 if (config3 & MIPS_CONF3_VINT)
711 c->options |= MIPS_CPU_VINT;
712 if (config3 & MIPS_CONF3_VEIC)
713 c->options |= MIPS_CPU_VEIC;
12822570
JH		 714 if (config3 & MIPS_CONF3_LPA)
715 c->options |= MIPS_CPU_LPA;
2fa36399
KC		 716 if (config3 & MIPS_CONF3_MT)
717 c->ases |= MIPS_ASE_MIPSMT;
718 if (config3 & MIPS_CONF3_ULRI)
719 c->options |= MIPS_CPU_ULRI;
f8fa4811
SH		 720 if (config3 & MIPS_CONF3_ISA)
721 c->options |= MIPS_CPU_MICROMIPS;
1e7decdb
DD		 722 if (config3 & MIPS_CONF3_VZ)
723 c->ases |= MIPS_ASE_VZ;
4a0156fb
SH		 724 if (config3 & MIPS_CONF3_SC)
725 c->options |= MIPS_CPU_SEGMENTS;
e06a1548
JH		 726 if (config3 & MIPS_CONF3_BI)
727 c->options |= MIPS_CPU_BADINSTR;
728 if (config3 & MIPS_CONF3_BP)
729 c->options |= MIPS_CPU_BADINSTRP;
a5e9a69e
PB		 730 if (config3 & MIPS_CONF3_MSA)
731 c->ases |= MIPS_ASE_MSA;
cab25bc7 732 if (config3 & MIPS_CONF3_PW) {
ed4cbc81 733 c->htw_seq = 0;
3d528b32 734 c->options |= MIPS_CPU_HTW;
ed4cbc81 735 }
9b3274bd
JH		 736 if (config3 & MIPS_CONF3_CDMM)
737 c->options |= MIPS_CPU_CDMM;
aaa7be48
JH		 738 if (config3 & MIPS_CONF3_SP)
739 c->options |= MIPS_CPU_SP;
2fa36399
KC		 740
741 return config3 & MIPS_CONF_M;
742}
743
744static inline unsigned int decode_config4(struct cpuinfo_mips *c)
745{
746 unsigned int config4;
75b5b5e0
LY		 747 unsigned int newcf4;
748 unsigned int mmuextdef;
749 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
2db003a5 750 unsigned long asid_mask;
2fa36399
KC		 751
752 config4 = read_c0_config4();
753
1745c1ef
LY		 754 if (cpu_has_tlb) {
755 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
756 c->options |= MIPS_CPU_TLBINV;
43d104db 757
e87569cd 758 /*
43d104db
JH		 759 * R6 has dropped the MMUExtDef field from config4.
760 * On R6 the fields always describe the FTLB, and only if it is
761 * present according to Config.MT.
e87569cd 762 */
43d104db
JH		 763 if (!cpu_has_mips_r6)
764 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
765 else if (cpu_has_ftlb)
e87569cd
MC		 766 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
767 else
43d104db 768 mmuextdef = 0;
e87569cd 769
75b5b5e0
LY		 770 switch (mmuextdef) {
771 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
772 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
773 c->tlbsizevtlb = c->tlbsize;
774 break;
775 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
776 c->tlbsizevtlb +=
777 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
778 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
779 c->tlbsize = c->tlbsizevtlb;
780 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
781 /* fall through */
782 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
97f4ad29
MC		 783 if (mips_ftlb_disabled)
784 break;
75b5b5e0
LY		 785 newcf4 = (config4 & ~ftlb_page) |
786 (page_size_ftlb(mmuextdef) <<
787 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
788 write_c0_config4(newcf4);
789 back_to_back_c0_hazard();
790 config4 = read_c0_config4();
791 if (config4 != newcf4) {
792 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
793 PAGE_SIZE, config4);
794 /* Switch FTLB off */
795 set_ftlb_enable(c, 0);
ebd0e0f5 796 mips_ftlb_disabled = 1;
75b5b5e0
LY		 797 break;
798 }
799 c->tlbsizeftlbsets = 1 <<
800 ((config4 & MIPS_CONF4_FTLBSETS) >>
801 MIPS_CONF4_FTLBSETS_SHIFT);
802 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
803 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
804 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
97f4ad29 805 mips_has_ftlb_configured = 1;
75b5b5e0
LY		 806 break;
807 }
1745c1ef
LY		 808 }
809
9e575f75
JH		 810 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
811 >> MIPS_CONF4_KSCREXIST_SHIFT;
2fa36399 812
2db003a5
PB		 813 asid_mask = MIPS_ENTRYHI_ASID;
814 if (config4 & MIPS_CONF4_AE)
815 asid_mask |= MIPS_ENTRYHI_ASIDX;
816 set_cpu_asid_mask(c, asid_mask);
817
818 /*
819 * Warn if the computed ASID mask doesn't match the mask the kernel
820 * is built for. This may indicate either a serious problem or an
821 * easy optimisation opportunity, but either way should be addressed.
822 */
823 WARN_ON(asid_mask != cpu_asid_mask(c));
824
2fa36399
KC		 825 return config4 & MIPS_CONF_M;
826}
827
8b8a7634
RB		 828static inline unsigned int decode_config5(struct cpuinfo_mips *c)
829{
830 unsigned int config5;
831
832 config5 = read_c0_config5();
d175ed2b 833 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
8b8a7634
RB		 834 write_c0_config5(config5);
835
49016748
MC		 836 if (config5 & MIPS_CONF5_EVA)
837 c->options |= MIPS_CPU_EVA;
1f6c52ff
PB		 838 if (config5 & MIPS_CONF5_MRP)
839 c->options |= MIPS_CPU_MAAR;
5aed9da1
MC		 840 if (config5 & MIPS_CONF5_LLB)
841 c->options |= MIPS_CPU_RW_LLB;
c5b36783 842 if (config5 & MIPS_CONF5_MVH)
0f2d988d 843 c->options |= MIPS_CPU_MVH;
f270d881
PB		 844 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
845 c->options |= MIPS_CPU_VP;
49016748 846
8b8a7634
RB		 847 return config5 & MIPS_CONF_M;
848}
849
078a55fc 850static void decode_configs(struct cpuinfo_mips *c)
2fa36399
KC		 851{
852 int ok;
853
854 /* MIPS32 or MIPS64 compliant CPU. */
855 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
856 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
857
858 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
859
97f4ad29 860 /* Enable FTLB if present and not disabled */
ebd0e0f5 861 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN);
75b5b5e0 862
2fa36399 863 ok = decode_config0(c); /* Read Config registers. */
70342287 864 BUG_ON(!ok); /* Arch spec violation! */
2fa36399
KC		 865 if (ok)
866 ok = decode_config1(c);
867 if (ok)
868 ok = decode_config2(c);
869 if (ok)
870 ok = decode_config3(c);
871 if (ok)
872 ok = decode_config4(c);
8b8a7634
RB		 873 if (ok)
874 ok = decode_config5(c);
2fa36399 875
37fb60f8
JH		 876 /* Probe the EBase.WG bit */
877 if (cpu_has_mips_r2_r6) {
878 u64 ebase;
879 unsigned int status;
880
881 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
882 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
883 : (s32)read_c0_ebase();
884 if (ebase & MIPS_EBASE_WG) {
885 /* WG bit already set, we can avoid the clumsy probe */
886 c->options |= MIPS_CPU_EBASE_WG;
887 } else {
888 /* Its UNDEFINED to change EBase while BEV=0 */
889 status = read_c0_status();
890 write_c0_status(status | ST0_BEV);
891 irq_enable_hazard();
892 /*
893 * On pre-r6 cores, this may well clobber the upper bits
894 * of EBase. This is hard to avoid without potentially
895 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
896 */
897 if (cpu_has_mips64r6)
898 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
899 else
900 write_c0_ebase(ebase | MIPS_EBASE_WG);
901 back_to_back_c0_hazard();
902 /* Restore BEV */
903 write_c0_status(status);
904 if (read_c0_ebase() & MIPS_EBASE_WG) {
905 c->options |= MIPS_CPU_EBASE_WG;
906 write_c0_ebase(ebase);
907 }
908 }
909 }
910
ebd0e0f5
PB		 911 /* configure the FTLB write probability */
912 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
913
2fa36399
KC		 914 mips_probe_watch_registers(c);
915
0ee958e1 916#ifndef CONFIG_MIPS_CPS
8b8aa636 917 if (cpu_has_mips_r2_r6) {
45b585c8 918 c->core = get_ebase_cpunum();
30ee615b
PB		 919 if (cpu_has_mipsmt)
920 c->core >>= fls(core_nvpes()) - 1;
921 }
0ee958e1 922#endif
2fa36399
KC		 923}
924
6ad816e7
JH		 925/*
926 * Probe for certain guest capabilities by writing config bits and reading back.
927 * Finally write back the original value.
928 */
929#define probe_gc0_config(name, maxconf, bits) \
930do { \
931 unsigned int tmp; \
932 tmp = read_gc0_##name(); \
933 write_gc0_##name(tmp | (bits)); \
934 back_to_back_c0_hazard(); \
935 maxconf = read_gc0_##name(); \
936 write_gc0_##name(tmp); \
937} while (0)
938
939/*
940 * Probe for dynamic guest capabilities by changing certain config bits and
941 * reading back to see if they change. Finally write back the original value.
942 */
943#define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \
944do { \
945 maxconf = read_gc0_##name(); \
946 write_gc0_##name(maxconf ^ (bits)); \
947 back_to_back_c0_hazard(); \
948 dynconf = maxconf ^ read_gc0_##name(); \
949 write_gc0_##name(maxconf); \
950 maxconf |= dynconf; \
951} while (0)
952
953static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
954{
955 unsigned int config0;
956
957 probe_gc0_config(config, config0, MIPS_CONF_M);
958
959 if (config0 & MIPS_CONF_M)
960 c->guest.conf |= BIT(1);
961 return config0 & MIPS_CONF_M;
962}
963
964static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
965{
966 unsigned int config1, config1_dyn;
967
968 probe_gc0_config_dyn(config1, config1, config1_dyn,
969 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
970 MIPS_CONF1_FP);
971
972 if (config1 & MIPS_CONF1_FP)
973 c->guest.options |= MIPS_CPU_FPU;
974 if (config1_dyn & MIPS_CONF1_FP)
975 c->guest.options_dyn |= MIPS_CPU_FPU;
976
977 if (config1 & MIPS_CONF1_WR)
978 c->guest.options |= MIPS_CPU_WATCH;
979 if (config1_dyn & MIPS_CONF1_WR)
980 c->guest.options_dyn |= MIPS_CPU_WATCH;
981
982 if (config1 & MIPS_CONF1_PC)
983 c->guest.options |= MIPS_CPU_PERF;
984 if (config1_dyn & MIPS_CONF1_PC)
985 c->guest.options_dyn |= MIPS_CPU_PERF;
986
987 if (config1 & MIPS_CONF_M)
988 c->guest.conf |= BIT(2);
989 return config1 & MIPS_CONF_M;
990}
991
992static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
993{
994 unsigned int config2;
995
996 probe_gc0_config(config2, config2, MIPS_CONF_M);
997
998 if (config2 & MIPS_CONF_M)
999 c->guest.conf |= BIT(3);
1000 return config2 & MIPS_CONF_M;
1001}
1002
1003static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
1004{
1005 unsigned int config3, config3_dyn;
1006
1007 probe_gc0_config_dyn(config3, config3, config3_dyn,
1008 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_CTXTC);
1009
1010 if (config3 & MIPS_CONF3_CTXTC)
1011 c->guest.options |= MIPS_CPU_CTXTC;
1012 if (config3_dyn & MIPS_CONF3_CTXTC)
1013 c->guest.options_dyn |= MIPS_CPU_CTXTC;
1014
1015 if (config3 & MIPS_CONF3_PW)
1016 c->guest.options |= MIPS_CPU_HTW;
1017
1018 if (config3 & MIPS_CONF3_SC)
1019 c->guest.options |= MIPS_CPU_SEGMENTS;
1020
1021 if (config3 & MIPS_CONF3_BI)
1022 c->guest.options |= MIPS_CPU_BADINSTR;
1023 if (config3 & MIPS_CONF3_BP)
1024 c->guest.options |= MIPS_CPU_BADINSTRP;
1025
1026 if (config3 & MIPS_CONF3_MSA)
1027 c->guest.ases |= MIPS_ASE_MSA;
1028 if (config3_dyn & MIPS_CONF3_MSA)
1029 c->guest.ases_dyn |= MIPS_ASE_MSA;
1030
1031 if (config3 & MIPS_CONF_M)
1032 c->guest.conf |= BIT(4);
1033 return config3 & MIPS_CONF_M;
1034}
1035
1036static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
1037{
1038 unsigned int config4;
1039
1040 probe_gc0_config(config4, config4,
1041 MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
1042
1043 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
1044 >> MIPS_CONF4_KSCREXIST_SHIFT;
1045
1046 if (config4 & MIPS_CONF_M)
1047 c->guest.conf |= BIT(5);
1048 return config4 & MIPS_CONF_M;
1049}
1050
1051static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
1052{
1053 unsigned int config5, config5_dyn;
1054
1055 probe_gc0_config_dyn(config5, config5, config5_dyn,
1056 MIPS_CONF_M | MIPS_CONF5_MRP);
1057
1058 if (config5 & MIPS_CONF5_MRP)
1059 c->guest.options |= MIPS_CPU_MAAR;
1060 if (config5_dyn & MIPS_CONF5_MRP)
1061 c->guest.options_dyn |= MIPS_CPU_MAAR;
1062
1063 if (config5 & MIPS_CONF5_LLB)
1064 c->guest.options |= MIPS_CPU_RW_LLB;
1065
1066 if (config5 & MIPS_CONF_M)
1067 c->guest.conf |= BIT(6);
1068 return config5 & MIPS_CONF_M;
1069}
1070
1071static inline void decode_guest_configs(struct cpuinfo_mips *c)
1072{
1073 unsigned int ok;
1074
1075 ok = decode_guest_config0(c);
1076 if (ok)
1077 ok = decode_guest_config1(c);
1078 if (ok)
1079 ok = decode_guest_config2(c);
1080 if (ok)
1081 ok = decode_guest_config3(c);
1082 if (ok)
1083 ok = decode_guest_config4(c);
1084 if (ok)
1085 decode_guest_config5(c);
1086}
1087
1088static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
1089{
1090 unsigned int guestctl0, temp;
1091
1092 guestctl0 = read_c0_guestctl0();
1093
1094 if (guestctl0 & MIPS_GCTL0_G0E)
1095 c->options |= MIPS_CPU_GUESTCTL0EXT;
1096 if (guestctl0 & MIPS_GCTL0_G1)
1097 c->options |= MIPS_CPU_GUESTCTL1;
1098 if (guestctl0 & MIPS_GCTL0_G2)
1099 c->options |= MIPS_CPU_GUESTCTL2;
1100 if (!(guestctl0 & MIPS_GCTL0_RAD)) {
1101 c->options |= MIPS_CPU_GUESTID;
1102
1103 /*
1104 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
1105 * first, otherwise all data accesses will be fully virtualised
1106 * as if they were performed by guest mode.
1107 */
1108 write_c0_guestctl1(0);
1109 tlbw_use_hazard();
1110
1111 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
1112 back_to_back_c0_hazard();
1113 temp = read_c0_guestctl0();
1114
1115 if (temp & MIPS_GCTL0_DRG) {
1116 write_c0_guestctl0(guestctl0);
1117 c->options |= MIPS_CPU_DRG;
1118 }
1119 }
1120}
1121
1122static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
1123{
1124 if (cpu_has_guestid) {
1125 /* determine the number of bits of GuestID available */
1126 write_c0_guestctl1(MIPS_GCTL1_ID);
1127 back_to_back_c0_hazard();
1128 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
1129 >> MIPS_GCTL1_ID_SHIFT;
1130 write_c0_guestctl1(0);
1131 }
1132}
1133
1134static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
1135{
1136 /* determine the number of bits of GTOffset available */
1137 write_c0_gtoffset(0xffffffff);
1138 back_to_back_c0_hazard();
1139 c->gtoffset_mask = read_c0_gtoffset();
1140 write_c0_gtoffset(0);
1141}
1142
1143static inline void cpu_probe_vz(struct cpuinfo_mips *c)
1144{
1145 cpu_probe_guestctl0(c);
1146 if (cpu_has_guestctl1)
1147 cpu_probe_guestctl1(c);
1148
1149 cpu_probe_gtoffset(c);
1150
1151 decode_guest_configs(c);
1152}
1153
02cf2119 1154#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 1155 | MIPS_CPU_COUNTER)
1156
cea7e2df 1157static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1158{
8ff374b9 1159 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1160 case PRID_IMP_R2000:
1161 c->cputype = CPU_R2000;
cea7e2df 1162 __cpu_name[cpu] = "R2000";
9b26616c 1163 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 1164 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 1165 MIPS_CPU_NOFPUEX;
1da177e4
LT		 1166 if (__cpu_has_fpu())
1167 c->options |= MIPS_CPU_FPU;
1168 c->tlbsize = 64;
1169 break;
1170 case PRID_IMP_R3000:
8ff374b9 1171 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
cea7e2df 1172 if (cpu_has_confreg()) {
1da177e4 1173 c->cputype = CPU_R3081E;
cea7e2df
RB		 1174 __cpu_name[cpu] = "R3081";
1175 } else {
1da177e4 1176 c->cputype = CPU_R3000A;
cea7e2df
RB		 1177 __cpu_name[cpu] = "R3000A";
1178 }
cea7e2df 1179 } else {
1da177e4 1180 c->cputype = CPU_R3000;
cea7e2df
RB		 1181 __cpu_name[cpu] = "R3000";
1182 }
9b26616c 1183 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 1184 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 1185 MIPS_CPU_NOFPUEX;
1da177e4
LT		 1186 if (__cpu_has_fpu())
1187 c->options |= MIPS_CPU_FPU;
1188 c->tlbsize = 64;
1189 break;
1190 case PRID_IMP_R4000:
1191 if (read_c0_config() & CONF_SC) {
8ff374b9
MR		 1192 if ((c->processor_id & PRID_REV_MASK) >=
1193 PRID_REV_R4400) {
1da177e4 1194 c->cputype = CPU_R4400PC;
cea7e2df
RB		 1195 __cpu_name[cpu] = "R4400PC";
1196 } else {
1da177e4 1197 c->cputype = CPU_R4000PC;
cea7e2df
RB		 1198 __cpu_name[cpu] = "R4000PC";
1199 }
1da177e4 1200 } else {
7f177a52
MR		 1201 int cca = read_c0_config() & CONF_CM_CMASK;
1202 int mc;
1203
1204 /*
1205 * SC and MC versions can't be reliably told apart,
1206 * but only the latter support coherent caching
1207 * modes so assume the firmware has set the KSEG0
1208 * coherency attribute reasonably (if uncached, we
1209 * assume SC).
1210 */
1211 switch (cca) {
1212 case CONF_CM_CACHABLE_CE:
1213 case CONF_CM_CACHABLE_COW:
1214 case CONF_CM_CACHABLE_CUW:
1215 mc = 1;
1216 break;
1217 default:
1218 mc = 0;
1219 break;
1220 }
8ff374b9
MR		 1221 if ((c->processor_id & PRID_REV_MASK) >=
1222 PRID_REV_R4400) {
7f177a52
MR		 1223 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
1224 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
cea7e2df 1225 } else {
7f177a52
MR		 1226 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
1227 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
cea7e2df 1228 }
1da177e4
LT		 1229 }
1230
a96102be 1231 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1232 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 1233 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 1234 MIPS_CPU_WATCH | MIPS_CPU_VCE |
1235 MIPS_CPU_LLSC;
1da177e4
LT		 1236 c->tlbsize = 48;
1237 break;
1238 case PRID_IMP_VR41XX:
9f91e506 1239 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1240 c->fpu_msk31 |= FPU_CSR_CONDX;
9f91e506
YY		 1241 c->options = R4K_OPTS;
1242 c->tlbsize = 32;
1da177e4 1243 switch (c->processor_id & 0xf0) {
1da177e4
LT		 1244 case PRID_REV_VR4111:
1245 c->cputype = CPU_VR4111;
cea7e2df 1246 __cpu_name[cpu] = "NEC VR4111";
1da177e4 1247 break;
1da177e4
LT		 1248 case PRID_REV_VR4121:
1249 c->cputype = CPU_VR4121;
cea7e2df 1250 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 1251 break;
1252 case PRID_REV_VR4122:
cea7e2df 1253 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 1254 c->cputype = CPU_VR4122;
cea7e2df
RB		 1255 __cpu_name[cpu] = "NEC VR4122";
1256 } else {
1da177e4 1257 c->cputype = CPU_VR4181A;
cea7e2df
RB		 1258 __cpu_name[cpu] = "NEC VR4181A";
1259 }
1da177e4
LT		 1260 break;
1261 case PRID_REV_VR4130:
cea7e2df 1262 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 1263 c->cputype = CPU_VR4131;
cea7e2df
RB		 1264 __cpu_name[cpu] = "NEC VR4131";
1265 } else {
1da177e4 1266 c->cputype = CPU_VR4133;
9f91e506 1267 c->options |= MIPS_CPU_LLSC;
cea7e2df
RB		 1268 __cpu_name[cpu] = "NEC VR4133";
1269 }
1da177e4
LT		 1270 break;
1271 default:
1272 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
1273 c->cputype = CPU_VR41XX;
cea7e2df 1274 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 1275 break;
1276 }
1da177e4
LT		 1277 break;
1278 case PRID_IMP_R4300:
1279 c->cputype = CPU_R4300;
cea7e2df 1280 __cpu_name[cpu] = "R4300";
a96102be 1281 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1282 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 1283 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1284 MIPS_CPU_LLSC;
1da177e4
LT		 1285 c->tlbsize = 32;
1286 break;
1287 case PRID_IMP_R4600:
1288 c->cputype = CPU_R4600;
cea7e2df 1289 __cpu_name[cpu] = "R4600";
a96102be 1290 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1291 c->fpu_msk31 |= FPU_CSR_CONDX;
075e7502
TS		 1292 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1293 MIPS_CPU_LLSC;
1da177e4
LT		 1294 c->tlbsize = 48;
1295 break;
1296 #if 0
03751e79 1297 case PRID_IMP_R4650:
1da177e4
LT		 1298 /*
1299 * This processor doesn't have an MMU, so it's not
1300 * "real easy" to run Linux on it. It is left purely
1301 * for documentation. Commented out because it shares
1302 * it's c0_prid id number with the TX3900.
1303 */
a3dddd56 1304 c->cputype = CPU_R4650;
cea7e2df 1305 __cpu_name[cpu] = "R4650";
a96102be 1306 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1307 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 1308 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 1309 c->tlbsize = 48;
1da177e4
LT		 1310 break;
1311 #endif
1312 case PRID_IMP_TX39:
9b26616c 1313 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 1314 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 1315
1316 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1317 c->cputype = CPU_TX3927;
cea7e2df 1318 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 1319 c->tlbsize = 64;
1320 } else {
8ff374b9 1321 switch (c->processor_id & PRID_REV_MASK) {
1da177e4
LT		 1322 case PRID_REV_TX3912:
1323 c->cputype = CPU_TX3912;
cea7e2df 1324 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 1325 c->tlbsize = 32;
1326 break;
1327 case PRID_REV_TX3922:
1328 c->cputype = CPU_TX3922;
cea7e2df 1329 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 1330 c->tlbsize = 64;
1331 break;
1da177e4
LT		 1332 }
1333 }
1334 break;
1335 case PRID_IMP_R4700:
1336 c->cputype = CPU_R4700;
cea7e2df 1337 __cpu_name[cpu] = "R4700";
a96102be 1338 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1339 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 1340 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1341 MIPS_CPU_LLSC;
1da177e4
LT		 1342 c->tlbsize = 48;
1343 break;
1344 case PRID_IMP_TX49:
1345 c->cputype = CPU_TX49XX;
cea7e2df 1346 __cpu_name[cpu] = "R49XX";
a96102be 1347 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1348 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4
LT		 1349 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1350 if (!(c->processor_id & 0x08))
1351 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1352 c->tlbsize = 48;
1353 break;
1354 case PRID_IMP_R5000:
1355 c->cputype = CPU_R5000;
cea7e2df 1356 __cpu_name[cpu] = "R5000";
a96102be 1357 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1358 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1359 MIPS_CPU_LLSC;
1da177e4
LT		 1360 c->tlbsize = 48;
1361 break;
1362 case PRID_IMP_R5432:
1363 c->cputype = CPU_R5432;
cea7e2df 1364 __cpu_name[cpu] = "R5432";
a96102be 1365 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1366 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1367 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 1368 c->tlbsize = 48;
1369 break;
1370 case PRID_IMP_R5500:
1371 c->cputype = CPU_R5500;
cea7e2df 1372 __cpu_name[cpu] = "R5500";
a96102be 1373 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1374 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1375 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 1376 c->tlbsize = 48;
1377 break;
1378 case PRID_IMP_NEVADA:
1379 c->cputype = CPU_NEVADA;
cea7e2df 1380 __cpu_name[cpu] = "Nevada";
a96102be 1381 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1382 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1383 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 1384 c->tlbsize = 48;
1385 break;
1386 case PRID_IMP_R6000:
1387 c->cputype = CPU_R6000;
cea7e2df 1388 __cpu_name[cpu] = "R6000";
a96102be 1389 set_isa(c, MIPS_CPU_ISA_II);
9b26616c 1390 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1da177e4 1391 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 1392 MIPS_CPU_LLSC;
1da177e4
LT		 1393 c->tlbsize = 32;
1394 break;
1395 case PRID_IMP_R6000A:
1396 c->cputype = CPU_R6000A;
cea7e2df 1397 __cpu_name[cpu] = "R6000A";
a96102be 1398 set_isa(c, MIPS_CPU_ISA_II);
9b26616c 1399 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1da177e4 1400 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 1401 MIPS_CPU_LLSC;
1da177e4
LT		 1402 c->tlbsize = 32;
1403 break;
1404 case PRID_IMP_RM7000:
1405 c->cputype = CPU_RM7000;
cea7e2df 1406 __cpu_name[cpu] = "RM7000";
a96102be 1407 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1408 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1409 MIPS_CPU_LLSC;
1da177e4 1410 /*
70342287 1411 * Undocumented RM7000: Bit 29 in the info register of
1da177e4
LT		 1412 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1413 * entries.
1414 *
70342287
RB		 1415 * 29 1 => 64 entry JTLB
1416 * 0 => 48 entry JTLB
1da177e4
LT		 1417 */
1418 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1da177e4
LT		 1419 break;
1420 case PRID_IMP_R8000:
1421 c->cputype = CPU_R8000;
cea7e2df 1422 __cpu_name[cpu] = "RM8000";
a96102be 1423 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1424 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 1425 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1426 MIPS_CPU_LLSC;
1da177e4
LT		 1427 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
1428 break;
1429 case PRID_IMP_R10000:
1430 c->cputype = CPU_R10000;
cea7e2df 1431 __cpu_name[cpu] = "R10000";
a96102be 1432 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 1433 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 1434 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 1435 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 1436 MIPS_CPU_LLSC;
1da177e4
LT		 1437 c->tlbsize = 64;
1438 break;
1439 case PRID_IMP_R12000:
1440 c->cputype = CPU_R12000;
cea7e2df 1441 __cpu_name[cpu] = "R12000";
a96102be 1442 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 1443 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 1444 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 1445 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
8d5ded16 1446 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1da177e4
LT		 1447 c->tlbsize = 64;
1448 break;
44d921b2 1449 case PRID_IMP_R14000:
30577391
JK		 1450 if (((c->processor_id >> 4) & 0x0f) > 2) {
1451 c->cputype = CPU_R16000;
1452 __cpu_name[cpu] = "R16000";
1453 } else {
1454 c->cputype = CPU_R14000;
1455 __cpu_name[cpu] = "R14000";
1456 }
a96102be 1457 set_isa(c, MIPS_CPU_ISA_IV);
44d921b2 1458 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 1459 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 1460 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
8d5ded16 1461 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
44d921b2
K		 1462 c->tlbsize = 64;
1463 break;
26859198 1464 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
5aac1e8a
RM		 1465 switch (c->processor_id & PRID_REV_MASK) {
1466 case PRID_REV_LOONGSON2E:
c579d310
HC		 1467 c->cputype = CPU_LOONGSON2;
1468 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 1469 set_elf_platform(cpu, "loongson2e");
7352c8b1 1470 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1471 c->fpu_msk31 |= FPU_CSR_CONDX;
5aac1e8a
RM		 1472 break;
1473 case PRID_REV_LOONGSON2F:
c579d310
HC		 1474 c->cputype = CPU_LOONGSON2;
1475 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 1476 set_elf_platform(cpu, "loongson2f");
7352c8b1 1477 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1478 c->fpu_msk31 |= FPU_CSR_CONDX;
5aac1e8a 1479 break;
b2edcfc8 1480 case PRID_REV_LOONGSON3A_R1:
c579d310
HC		 1481 c->cputype = CPU_LOONGSON3;
1482 __cpu_name[cpu] = "ICT Loongson-3";
1483 set_elf_platform(cpu, "loongson3a");
7352c8b1 1484 set_isa(c, MIPS_CPU_ISA_M64R1);
c579d310 1485 break;
e7841be5
HC		 1486 case PRID_REV_LOONGSON3B_R1:
1487 case PRID_REV_LOONGSON3B_R2:
1488 c->cputype = CPU_LOONGSON3;
1489 __cpu_name[cpu] = "ICT Loongson-3";
1490 set_elf_platform(cpu, "loongson3b");
7352c8b1 1491 set_isa(c, MIPS_CPU_ISA_M64R1);
e7841be5 1492 break;
5aac1e8a
RM		 1493 }
1494
2a21c730
FZ		 1495 c->options = R4K_OPTS |
1496 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1497 MIPS_CPU_32FPR;
1498 c->tlbsize = 64;
cc94ea31 1499 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2a21c730 1500 break;
26859198 1501 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
2fa36399 1502 decode_configs(c);
b4672d37 1503
2fa36399 1504 c->cputype = CPU_LOONGSON1;
1da177e4 1505
2fa36399
KC		 1506 switch (c->processor_id & PRID_REV_MASK) {
1507 case PRID_REV_LOONGSON1B:
1508 __cpu_name[cpu] = "Loongson 1B";
b4672d37 1509 break;
b4672d37 1510 }
4194318c 1511
2fa36399 1512 break;
1da177e4 1513 }
1da177e4
LT		 1514}
1515
cea7e2df 1516static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1517{
4f12b91d 1518 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 1519 switch (c->processor_id & PRID_IMP_MASK) {
b2498af5
LY		 1520 case PRID_IMP_QEMU_GENERIC:
1521 c->writecombine = _CACHE_UNCACHED;
1522 c->cputype = CPU_QEMU_GENERIC;
1523 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1524 break;
1da177e4
LT		 1525 case PRID_IMP_4KC:
1526 c->cputype = CPU_4KC;
4f12b91d 1527 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1528 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 1529 break;
1530 case PRID_IMP_4KEC:
2b07bd02
RB		 1531 case PRID_IMP_4KECR2:
1532 c->cputype = CPU_4KEC;
4f12b91d 1533 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1534 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 1535 break;
1da177e4 1536 case PRID_IMP_4KSC:
8afcb5d8 1537 case PRID_IMP_4KSD:
1da177e4 1538 c->cputype = CPU_4KSC;
4f12b91d 1539 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1540 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 1541 break;
1542 case PRID_IMP_5KC:
1543 c->cputype = CPU_5KC;
4f12b91d 1544 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1545 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4 1546 break;
78d4803f
LY		 1547 case PRID_IMP_5KE:
1548 c->cputype = CPU_5KE;
4f12b91d 1549 c->writecombine = _CACHE_UNCACHED;
78d4803f
LY		 1550 __cpu_name[cpu] = "MIPS 5KE";
1551 break;
1da177e4
LT		 1552 case PRID_IMP_20KC:
1553 c->cputype = CPU_20KC;
4f12b91d 1554 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1555 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 1556 break;
1557 case PRID_IMP_24K:
1558 c->cputype = CPU_24K;
4f12b91d 1559 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1560 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4 1561 break;
42f3caef
JC		 1562 case PRID_IMP_24KE:
1563 c->cputype = CPU_24K;
4f12b91d 1564 c->writecombine = _CACHE_UNCACHED;
42f3caef
JC		 1565 __cpu_name[cpu] = "MIPS 24KEc";
1566 break;
1da177e4
LT		 1567 case PRID_IMP_25KF:
1568 c->cputype = CPU_25KF;
4f12b91d 1569 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1570 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 1571 break;
bbc7f22f
RB		 1572 case PRID_IMP_34K:
1573 c->cputype = CPU_34K;
4f12b91d 1574 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1575 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 1576 break;
c620953c
CD		 1577 case PRID_IMP_74K:
1578 c->cputype = CPU_74K;
4f12b91d 1579 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1580 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 1581 break;
113c62d9
SH		 1582 case PRID_IMP_M14KC:
1583 c->cputype = CPU_M14KC;
4f12b91d 1584 c->writecombine = _CACHE_UNCACHED;
113c62d9
SH		 1585 __cpu_name[cpu] = "MIPS M14Kc";
1586 break;
f8fa4811
SH		 1587 case PRID_IMP_M14KEC:
1588 c->cputype = CPU_M14KEC;
4f12b91d 1589 c->writecombine = _CACHE_UNCACHED;
f8fa4811
SH		 1590 __cpu_name[cpu] = "MIPS M14KEc";
1591 break;
39b8d525
RB		 1592 case PRID_IMP_1004K:
1593 c->cputype = CPU_1004K;
4f12b91d 1594 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1595 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 1596 break;
006a851b 1597 case PRID_IMP_1074K:
442e14a2 1598 c->cputype = CPU_1074K;
4f12b91d 1599 c->writecombine = _CACHE_UNCACHED;
006a851b
SH		 1600 __cpu_name[cpu] = "MIPS 1074Kc";
1601 break;
b5f065e7
LY		 1602 case PRID_IMP_INTERAPTIV_UP:
1603 c->cputype = CPU_INTERAPTIV;
1604 __cpu_name[cpu] = "MIPS interAptiv";
1605 break;
1606 case PRID_IMP_INTERAPTIV_MP:
1607 c->cputype = CPU_INTERAPTIV;
1608 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1609 break;
b0d4d300
LY		 1610 case PRID_IMP_PROAPTIV_UP:
1611 c->cputype = CPU_PROAPTIV;
1612 __cpu_name[cpu] = "MIPS proAptiv";
1613 break;
1614 case PRID_IMP_PROAPTIV_MP:
1615 c->cputype = CPU_PROAPTIV;
1616 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1617 break;
829dcc0a
JH		 1618 case PRID_IMP_P5600:
1619 c->cputype = CPU_P5600;
1620 __cpu_name[cpu] = "MIPS P5600";
1621 break;
eba20a3a
PB		 1622 case PRID_IMP_P6600:
1623 c->cputype = CPU_P6600;
1624 __cpu_name[cpu] = "MIPS P6600";
1625 break;
e57f9a2d
MC		 1626 case PRID_IMP_I6400:
1627 c->cputype = CPU_I6400;
1628 __cpu_name[cpu] = "MIPS I6400";
1629 break;
9943ed92
LY		 1630 case PRID_IMP_M5150:
1631 c->cputype = CPU_M5150;
1632 __cpu_name[cpu] = "MIPS M5150";
1633 break;
43aff742
PB		 1634 case PRID_IMP_M6250:
1635 c->cputype = CPU_M6250;
1636 __cpu_name[cpu] = "MIPS M6250";
1637 break;
1da177e4 1638 }
0b6d497f 1639
75b5b5e0
LY		 1640 decode_configs(c);
1641
0b6d497f 1642 spram_config();
1da177e4
LT		 1643}
1644
cea7e2df 1645static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1646{
4194318c 1647 decode_configs(c);
8ff374b9 1648 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1649 case PRID_IMP_AU1_REV1:
1650 case PRID_IMP_AU1_REV2:
270717a8 1651 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 1652 switch ((c->processor_id >> 24) & 0xff) {
1653 case 0:
cea7e2df 1654 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 1655 break;
1656 case 1:
cea7e2df 1657 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 1658 break;
1659 case 2:
cea7e2df 1660 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 1661 break;
1662 case 3:
cea7e2df 1663 __cpu_name[cpu] = "Au1550";
1da177e4 1664 break;
e3ad1c23 1665 case 4:
cea7e2df 1666 __cpu_name[cpu] = "Au1200";
8ff374b9 1667 if ((c->processor_id & PRID_REV_MASK) == 2)
cea7e2df 1668 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 1669 break;
1670 case 5:
cea7e2df 1671 __cpu_name[cpu] = "Au1210";
e3ad1c23 1672 break;
1da177e4 1673 default:
270717a8 1674 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 1675 break;
1676 }
1da177e4
LT		 1677 break;
1678 }
1679}
1680
cea7e2df 1681static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1682{
4194318c 1683 decode_configs(c);
02cf2119 1684
4f12b91d 1685 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 1686 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1687 case PRID_IMP_SB1:
1688 c->cputype = CPU_SB1;
cea7e2df 1689 __cpu_name[cpu] = "SiByte SB1";
1da177e4 1690 /* FPU in pass1 is known to have issues. */
8ff374b9 1691 if ((c->processor_id & PRID_REV_MASK) < 0x02)
010b853b 1692 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 1693 break;
93ce2f52
AI		 1694 case PRID_IMP_SB1A:
1695 c->cputype = CPU_SB1A;
cea7e2df 1696 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 1697 break;
1da177e4
LT		 1698 }
1699}
1700
cea7e2df 1701static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1702{
4194318c 1703 decode_configs(c);
8ff374b9 1704 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1705 case PRID_IMP_SR71000:
1706 c->cputype = CPU_SR71000;
cea7e2df 1707 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 1708 c->scache.ways = 8;
1709 c->tlbsize = 64;
1710 break;
1711 }
1712}
1713
cea7e2df 1714static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 1715{
1716 decode_configs(c);
8ff374b9 1717 switch (c->processor_id & PRID_IMP_MASK) {
bdf21b18
PP		 1718 case PRID_IMP_PR4450:
1719 c->cputype = CPU_PR4450;
cea7e2df 1720 __cpu_name[cpu] = "Philips PR4450";
a96102be 1721 set_isa(c, MIPS_CPU_ISA_M32R1);
bdf21b18 1722 break;
bdf21b18
PP		 1723 }
1724}
1725
cea7e2df 1726static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 1727{
1728 decode_configs(c);
8ff374b9 1729 switch (c->processor_id & PRID_IMP_MASK) {
190fca3e
KC		 1730 case PRID_IMP_BMIPS32_REV4:
1731 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 1732 c->cputype = CPU_BMIPS32;
1733 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 1734 set_elf_platform(cpu, "bmips32");
602977b0
KC		 1735 break;
1736 case PRID_IMP_BMIPS3300:
1737 case PRID_IMP_BMIPS3300_ALT:
1738 case PRID_IMP_BMIPS3300_BUG:
1739 c->cputype = CPU_BMIPS3300;
1740 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 1741 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 1742 break;
1743 case PRID_IMP_BMIPS43XX: {
8ff374b9 1744 int rev = c->processor_id & PRID_REV_MASK;
602977b0
KC		 1745
1746 if (rev >= PRID_REV_BMIPS4380_LO &&
1747 rev <= PRID_REV_BMIPS4380_HI) {
1748 c->cputype = CPU_BMIPS4380;
1749 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 1750 set_elf_platform(cpu, "bmips4380");
b4720809 1751 c->options |= MIPS_CPU_RIXI;
602977b0
KC		 1752 } else {
1753 c->cputype = CPU_BMIPS4350;
1754 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 1755 set_elf_platform(cpu, "bmips4350");
602977b0 1756 }
0de663ef 1757 break;
602977b0
KC		 1758 }
1759 case PRID_IMP_BMIPS5000:
68e6a783 1760 case PRID_IMP_BMIPS5200:
602977b0 1761 c->cputype = CPU_BMIPS5000;
37808d62
FF		 1762 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1763 __cpu_name[cpu] = "Broadcom BMIPS5200";
1764 else
1765 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 1766 set_elf_platform(cpu, "bmips5000");
b4720809 1767 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
0de663ef 1768 break;
1c0c13eb
AJ		 1769 }
1770}
1771
0dd4781b
DD		 1772static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1773{
1774 decode_configs(c);
8ff374b9 1775 switch (c->processor_id & PRID_IMP_MASK) {
0dd4781b
DD		 1776 case PRID_IMP_CAVIUM_CN38XX:
1777 case PRID_IMP_CAVIUM_CN31XX:
1778 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 1779 c->cputype = CPU_CAVIUM_OCTEON;
1780 __cpu_name[cpu] = "Cavium Octeon";
1781 goto platform;
0dd4781b
DD		 1782 case PRID_IMP_CAVIUM_CN58XX:
1783 case PRID_IMP_CAVIUM_CN56XX:
1784 case PRID_IMP_CAVIUM_CN50XX:
1785 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 1786 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1787 __cpu_name[cpu] = "Cavium Octeon+";
1788platform:
c094c99e 1789 set_elf_platform(cpu, "octeon");
0dd4781b 1790 break;
a1431b61 1791 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 1792 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 1793 case PRID_IMP_CAVIUM_CN66XX:
1794 case PRID_IMP_CAVIUM_CN68XX:
af04bb85 1795 case PRID_IMP_CAVIUM_CNF71XX:
0e56b385
DD		 1796 c->cputype = CPU_CAVIUM_OCTEON2;
1797 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 1798 set_elf_platform(cpu, "octeon2");
0e56b385 1799 break;
af04bb85 1800 case PRID_IMP_CAVIUM_CN70XX:
b8c8f665
DD		 1801 case PRID_IMP_CAVIUM_CN73XX:
1802 case PRID_IMP_CAVIUM_CNF75XX:
af04bb85
DD		 1803 case PRID_IMP_CAVIUM_CN78XX:
1804 c->cputype = CPU_CAVIUM_OCTEON3;
1805 __cpu_name[cpu] = "Cavium Octeon III";
1806 set_elf_platform(cpu, "octeon3");
1807 break;
0dd4781b
DD		 1808 default:
1809 printk(KERN_INFO "Unknown Octeon chip!\n");
1810 c->cputype = CPU_UNKNOWN;
1811 break;
1812 }
1813}
1814
b2edcfc8
HC		 1815static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
1816{
1817 switch (c->processor_id & PRID_IMP_MASK) {
1818 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1819 switch (c->processor_id & PRID_REV_MASK) {
1820 case PRID_REV_LOONGSON3A_R2:
1821 c->cputype = CPU_LOONGSON3;
1822 __cpu_name[cpu] = "ICT Loongson-3";
1823 set_elf_platform(cpu, "loongson3a");
1824 set_isa(c, MIPS_CPU_ISA_M64R2);
1825 break;
1826 }
1827
1828 decode_configs(c);
380cd582 1829 c->options |= MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
b2edcfc8
HC		 1830 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1831 break;
1832 default:
1833 panic("Unknown Loongson Processor ID!");
1834 break;
1835 }
1836}
1837
83ccf69d
LPC		 1838static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1839{
1840 decode_configs(c);
1841 /* JZRISC does not implement the CP0 counter. */
1842 c->options &= ~MIPS_CPU_COUNTER;
06947aaa 1843 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
8ff374b9 1844 switch (c->processor_id & PRID_IMP_MASK) {
83ccf69d
LPC		 1845 case PRID_IMP_JZRISC:
1846 c->cputype = CPU_JZRISC;
4f12b91d 1847 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
83ccf69d
LPC		 1848 __cpu_name[cpu] = "Ingenic JZRISC";
1849 break;
1850 default:
1851 panic("Unknown Ingenic Processor ID!");
1852 break;
1853 }
1854}
1855
a7117c6b
J		 1856static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1857{
1858 decode_configs(c);
1859
8ff374b9 1860 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
809f36c6
ML		 1861 c->cputype = CPU_ALCHEMY;
1862 __cpu_name[cpu] = "Au1300";
1863 /* following stuff is not for Alchemy */
1864 return;
1865 }
1866
70342287
RB		 1867 c->options = (MIPS_CPU_TLB |
1868 MIPS_CPU_4KEX |
a7117c6b 1869 MIPS_CPU_COUNTER |
70342287
RB		 1870 MIPS_CPU_DIVEC |
1871 MIPS_CPU_WATCH |
1872 MIPS_CPU_EJTAG |
a7117c6b
J		 1873 MIPS_CPU_LLSC);
1874
8ff374b9 1875 switch (c->processor_id & PRID_IMP_MASK) {
4ca86a2f 1876 case PRID_IMP_NETLOGIC_XLP2XX:
8907c55e 1877 case PRID_IMP_NETLOGIC_XLP9XX:
1c983986 1878 case PRID_IMP_NETLOGIC_XLP5XX:
4ca86a2f
J		 1879 c->cputype = CPU_XLP;
1880 __cpu_name[cpu] = "Broadcom XLPII";
1881 break;
1882
2aa54b20
J		 1883 case PRID_IMP_NETLOGIC_XLP8XX:
1884 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 1885 c->cputype = CPU_XLP;
1886 __cpu_name[cpu] = "Netlogic XLP";
1887 break;
1888
a7117c6b
J		 1889 case PRID_IMP_NETLOGIC_XLR732:
1890 case PRID_IMP_NETLOGIC_XLR716:
1891 case PRID_IMP_NETLOGIC_XLR532:
1892 case PRID_IMP_NETLOGIC_XLR308:
1893 case PRID_IMP_NETLOGIC_XLR532C:
1894 case PRID_IMP_NETLOGIC_XLR516C:
1895 case PRID_IMP_NETLOGIC_XLR508C:
1896 case PRID_IMP_NETLOGIC_XLR308C:
1897 c->cputype = CPU_XLR;
1898 __cpu_name[cpu] = "Netlogic XLR";
1899 break;
1900
1901 case PRID_IMP_NETLOGIC_XLS608:
1902 case PRID_IMP_NETLOGIC_XLS408:
1903 case PRID_IMP_NETLOGIC_XLS404:
1904 case PRID_IMP_NETLOGIC_XLS208:
1905 case PRID_IMP_NETLOGIC_XLS204:
1906 case PRID_IMP_NETLOGIC_XLS108:
1907 case PRID_IMP_NETLOGIC_XLS104:
1908 case PRID_IMP_NETLOGIC_XLS616B:
1909 case PRID_IMP_NETLOGIC_XLS608B:
1910 case PRID_IMP_NETLOGIC_XLS416B:
1911 case PRID_IMP_NETLOGIC_XLS412B:
1912 case PRID_IMP_NETLOGIC_XLS408B:
1913 case PRID_IMP_NETLOGIC_XLS404B:
1914 c->cputype = CPU_XLR;
1915 __cpu_name[cpu] = "Netlogic XLS";
1916 break;
1917
1918 default:
a3d4fb2d 1919 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 1920 c->processor_id);
1921 c->cputype = CPU_XLR;
1922 break;
1923 }
1924
a3d4fb2d 1925 if (c->cputype == CPU_XLP) {
a96102be 1926 set_isa(c, MIPS_CPU_ISA_M64R2);
a3d4fb2d
J		 1927 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1928 /* This will be updated again after all threads are woken up */
1929 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1930 } else {
a96102be 1931 set_isa(c, MIPS_CPU_ISA_M64R1);
a3d4fb2d
J		 1932 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1933 }
7777b939 1934 c->kscratch_mask = 0xf;
a7117c6b
J		 1935}
1936
949e51be
DD		 1937#ifdef CONFIG_64BIT
1938/* For use by uaccess.h */
1939u64 __ua_limit;
1940EXPORT_SYMBOL(__ua_limit);
1941#endif
1942
9966db25 1943const char *__cpu_name[NR_CPUS];
874fd3b5 1944const char *__elf_platform;
9966db25 1945
078a55fc 1946void cpu_probe(void)
1da177e4
LT		 1947{
1948 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 1949 unsigned int cpu = smp_processor_id();
1da177e4 1950
70342287 1951 c->processor_id = PRID_IMP_UNKNOWN;
1da177e4
LT		 1952 c->fpu_id = FPIR_IMP_NONE;
1953 c->cputype = CPU_UNKNOWN;
4f12b91d 1954 c->writecombine = _CACHE_UNCACHED;
1da177e4 1955
9b26616c
MR		 1956 c->fpu_csr31 = FPU_CSR_RN;
1957 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1958
1da177e4 1959 c->processor_id = read_c0_prid();
8ff374b9 1960 switch (c->processor_id & PRID_COMP_MASK) {
1da177e4 1961 case PRID_COMP_LEGACY:
cea7e2df 1962 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1963 break;
1964 case PRID_COMP_MIPS:
cea7e2df 1965 cpu_probe_mips(c, cpu);
1da177e4
LT		 1966 break;
1967 case PRID_COMP_ALCHEMY:
cea7e2df 1968 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1969 break;
1970 case PRID_COMP_SIBYTE:
cea7e2df 1971 cpu_probe_sibyte(c, cpu);
1da177e4 1972 break;
1c0c13eb 1973 case PRID_COMP_BROADCOM:
cea7e2df 1974 cpu_probe_broadcom(c, cpu);
1c0c13eb 1975 break;
1da177e4 1976 case PRID_COMP_SANDCRAFT:
cea7e2df 1977 cpu_probe_sandcraft(c, cpu);
1da177e4 1978 break;
a92b0588 1979 case PRID_COMP_NXP:
cea7e2df 1980 cpu_probe_nxp(c, cpu);
a3dddd56 1981 break;
0dd4781b
DD		 1982 case PRID_COMP_CAVIUM:
1983 cpu_probe_cavium(c, cpu);
1984 break;
b2edcfc8
HC		 1985 case PRID_COMP_LOONGSON:
1986 cpu_probe_loongson(c, cpu);
1987 break;
252617a4
PB		 1988 case PRID_COMP_INGENIC_D0:
1989 case PRID_COMP_INGENIC_D1:
1990 case PRID_COMP_INGENIC_E1:
83ccf69d
LPC		 1991 cpu_probe_ingenic(c, cpu);
1992 break;
a7117c6b
J		 1993 case PRID_COMP_NETLOGIC:
1994 cpu_probe_netlogic(c, cpu);
1995 break;
1da177e4 1996 }
dec8b1ca 1997
cea7e2df
RB		 1998 BUG_ON(!__cpu_name[cpu]);
1999 BUG_ON(c->cputype == CPU_UNKNOWN);
2000
dec8b1ca
FBH		 2001 /*
2002 * Platform code can force the cpu type to optimize code
2003 * generation. In that case be sure the cpu type is correctly
2004 * manually setup otherwise it could trigger some nasty bugs.
2005 */
2006 BUG_ON(current_cpu_type() != c->cputype);
2007
2e274768
FF		 2008 if (cpu_has_rixi) {
2009 /* Enable the RIXI exceptions */
2010 set_c0_pagegrain(PG_IEC);
2011 back_to_back_c0_hazard();
2012 /* Verify the IEC bit is set */
2013 if (read_c0_pagegrain() & PG_IEC)
2014 c->options |= MIPS_CPU_RIXIEX;
2015 }
2016
0103d23f
KC		 2017 if (mips_fpu_disabled)
2018 c->options &= ~MIPS_CPU_FPU;
2019
2020 if (mips_dsp_disabled)
ee80f7c7 2021 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f 2022
3d528b32
MC		 2023 if (mips_htw_disabled) {
2024 c->options &= ~MIPS_CPU_HTW;
2025 write_c0_pwctl(read_c0_pwctl() &
2026 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
2027 }
2028
7aecd5ca
MR		 2029 if (c->options & MIPS_CPU_FPU)
2030 cpu_set_fpu_opts(c);
2031 else
2032 cpu_set_nofpu_opts(c);
9966db25 2033
8d5ded16
JK		 2034 if (cpu_has_bp_ghist)
2035 write_c0_r10k_diag(read_c0_r10k_diag() |
2036 R10K_DIAG_E_GHIST);
2037
8b8aa636 2038 if (cpu_has_mips_r2_r6) {
f6771dbb 2039 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
da4b62cd
AC		 2040 /* R2 has Performance Counter Interrupt indicator */
2041 c->options |= MIPS_CPU_PCI;
2042 }
f6771dbb
RB		 2043 else
2044 c->srsets = 1;
91dfc423 2045
4c063034
PB		 2046 if (cpu_has_mips_r6)
2047 elf_hwcap |= HWCAP_MIPS_R6;
2048
a8ad1367 2049 if (cpu_has_msa) {
a5e9a69e 2050 c->msa_id = cpu_get_msa_id();
a8ad1367
PB		 2051 WARN(c->msa_id & MSA_IR_WRPF,
2052 "Vector register partitioning unimplemented!");
3cc9fa7f 2053 elf_hwcap |= HWCAP_MIPS_MSA;
a8ad1367 2054 }
a5e9a69e 2055
6ad816e7
JH		 2056 if (cpu_has_vz)
2057 cpu_probe_vz(c);
2058
91dfc423 2059 cpu_probe_vmbits(c);
949e51be
DD		 2060
2061#ifdef CONFIG_64BIT
2062 if (cpu == 0)
2063 __ua_limit = ~((1ull << cpu_vmbits) - 1);
2064#endif
1da177e4
LT		 2065}
2066
078a55fc 2067void cpu_report(void)
1da177e4
LT		 2068{
2069 struct cpuinfo_mips *c = &current_cpu_data;
2070
d9f897c9
LY		 2071 pr_info("CPU%d revision is: %08x (%s)\n",
2072 smp_processor_id(), c->processor_id, cpu_name_string());
1da177e4 2073 if (c->options & MIPS_CPU_FPU)
9966db25 2074 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
a5e9a69e
PB		 2075 if (cpu_has_msa)
2076 pr_info("MSA revision is: %08x\n", c->msa_id);
1da177e4 2077}
Linux 6.x block layer and io_uring tree(s)