projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
MIPS: BMIPS: Add cpu-feature-overrides.h
[linux-2.6-block.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
70342287 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4 22#include <asm/cpu.h>
f6843626 23#include <asm/cpu-features.h>
69f24d17 24#include <asm/cpu-type.h>
1da177e4
LT		 25#include <asm/fpu.h>
26#include <asm/mipsregs.h>
30ee615b 27#include <asm/mipsmtregs.h>
a5e9a69e 28#include <asm/msa.h>
654f57bf 29#include <asm/watch.h>
06372a63 30#include <asm/elf.h>
4f12b91d 31#include <asm/pgtable-bits.h>
a074f0e8 32#include <asm/spram.h>
949e51be
DD		 33#include <asm/uaccess.h>
34
e14f1db7
PB		 35/* Hardware capabilities */
36unsigned int elf_hwcap __read_mostly;
37
7aecd5ca
MR		 38/*
39 * Get the FPU Implementation/Revision.
40 */
41static inline unsigned long cpu_get_fpu_id(void)
42{
43 unsigned long tmp, fpu_id;
44
45 tmp = read_c0_status();
46 __enable_fpu(FPU_AS_IS);
47 fpu_id = read_32bit_cp1_register(CP1_REVISION);
48 write_c0_status(tmp);
49 return fpu_id;
50}
51
52/*
53 * Check if the CPU has an external FPU.
54 */
55static inline int __cpu_has_fpu(void)
56{
57 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
58}
59
60static inline unsigned long cpu_get_msa_id(void)
61{
62 unsigned long status, msa_id;
63
64 status = read_c0_status();
65 __enable_fpu(FPU_64BIT);
66 enable_msa();
67 msa_id = read_msa_ir();
68 disable_msa();
69 write_c0_status(status);
70 return msa_id;
71}
72
9b26616c
MR		 73/*
74 * Determine the FCSR mask for FPU hardware.
75 */
76static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
77{
78 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
79
90b712dd 80 fcsr = c->fpu_csr31;
9b26616c
MR		 81 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
82
83 sr = read_c0_status();
84 __enable_fpu(FPU_AS_IS);
85
9b26616c
MR		 86 fcsr0 = fcsr & mask;
87 write_32bit_cp1_register(CP1_STATUS, fcsr0);
88 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
89
90 fcsr1 = fcsr | ~mask;
91 write_32bit_cp1_register(CP1_STATUS, fcsr1);
92 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
93
94 write_32bit_cp1_register(CP1_STATUS, fcsr);
95
96 write_c0_status(sr);
97
98 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
99}
100
93adeaf6
MR		 101/*
102 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
103 * supported by FPU hardware.
104 */
105static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
106{
107 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
108 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
109 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
110 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
111
112 sr = read_c0_status();
113 __enable_fpu(FPU_AS_IS);
114
115 fir = read_32bit_cp1_register(CP1_REVISION);
116 if (fir & MIPS_FPIR_HAS2008) {
117 fcsr = read_32bit_cp1_register(CP1_STATUS);
118
119 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
120 write_32bit_cp1_register(CP1_STATUS, fcsr0);
121 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
122
123 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
124 write_32bit_cp1_register(CP1_STATUS, fcsr1);
125 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
126
127 write_32bit_cp1_register(CP1_STATUS, fcsr);
128
129 if (!(fcsr0 & FPU_CSR_NAN2008))
130 c->options |= MIPS_CPU_NAN_LEGACY;
131 if (fcsr1 & FPU_CSR_NAN2008)
132 c->options |= MIPS_CPU_NAN_2008;
133
134 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
135 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
136 else
137 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
138
139 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
140 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
141 else
142 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
143 } else {
144 c->options |= MIPS_CPU_NAN_LEGACY;
145 }
146
147 write_c0_status(sr);
148 } else {
149 c->options |= MIPS_CPU_NAN_LEGACY;
150 }
151}
152
153/*
503943e0
MR		 154 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
155 * ABS.fmt/NEG.fmt execution mode.
156 */
157static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
158
159/*
160 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
161 * to support by the FPU emulator according to the IEEE 754 conformance
162 * mode selected. Note that "relaxed" straps the emulator so that it
163 * allows 2008-NaN binaries even for legacy processors.
93adeaf6
MR		 164 */
165static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
166{
503943e0 167 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
93adeaf6 168 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
503943e0
MR		 169 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
170
171 switch (ieee754) {
172 case STRICT:
173 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
174 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
175 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
176 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
177 } else {
178 c->options |= MIPS_CPU_NAN_LEGACY;
179 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
180 }
181 break;
182 case LEGACY:
93adeaf6
MR		 183 c->options |= MIPS_CPU_NAN_LEGACY;
184 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
503943e0
MR		 185 break;
186 case STD2008:
187 c->options |= MIPS_CPU_NAN_2008;
188 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
189 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
190 break;
191 case RELAXED:
192 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
193 break;
93adeaf6
MR		 194 }
195}
196
503943e0
MR		 197/*
198 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
199 * according to the "ieee754=" parameter.
200 */
201static void cpu_set_nan_2008(struct cpuinfo_mips *c)
202{
203 switch (ieee754) {
204 case STRICT:
205 mips_use_nan_legacy = !!cpu_has_nan_legacy;
206 mips_use_nan_2008 = !!cpu_has_nan_2008;
207 break;
208 case LEGACY:
209 mips_use_nan_legacy = !!cpu_has_nan_legacy;
210 mips_use_nan_2008 = !cpu_has_nan_legacy;
211 break;
212 case STD2008:
213 mips_use_nan_legacy = !cpu_has_nan_2008;
214 mips_use_nan_2008 = !!cpu_has_nan_2008;
215 break;
216 case RELAXED:
217 mips_use_nan_legacy = true;
218 mips_use_nan_2008 = true;
219 break;
220 }
221}
222
223/*
224 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
225 * settings:
226 *
227 * strict: accept binaries that request a NaN encoding supported by the FPU
228 * legacy: only accept legacy-NaN binaries
229 * 2008: only accept 2008-NaN binaries
230 * relaxed: accept any binaries regardless of whether supported by the FPU
231 */
232static int __init ieee754_setup(char *s)
233{
234 if (!s)
235 return -1;
236 else if (!strcmp(s, "strict"))
237 ieee754 = STRICT;
238 else if (!strcmp(s, "legacy"))
239 ieee754 = LEGACY;
240 else if (!strcmp(s, "2008"))
241 ieee754 = STD2008;
242 else if (!strcmp(s, "relaxed"))
243 ieee754 = RELAXED;
244 else
245 return -1;
246
247 if (!(boot_cpu_data.options & MIPS_CPU_FPU))
248 cpu_set_nofpu_2008(&boot_cpu_data);
249 cpu_set_nan_2008(&boot_cpu_data);
250
251 return 0;
252}
253
254early_param("ieee754", ieee754_setup);
255
f6843626
MR		 256/*
257 * Set the FIR feature flags for the FPU emulator.
258 */
259static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
260{
261 u32 value;
262
263 value = 0;
264 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
265 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
266 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
267 value |= MIPS_FPIR_D | MIPS_FPIR_S;
268 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
269 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
270 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
90d53a91
MR		 271 if (c->options & MIPS_CPU_NAN_2008)
272 value |= MIPS_FPIR_HAS2008;
f6843626
MR		 273 c->fpu_id = value;
274}
275
9b26616c
MR		 276/* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
277static unsigned int mips_nofpu_msk31;
278
7aecd5ca
MR		 279/*
280 * Set options for FPU hardware.
281 */
282static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
283{
284 c->fpu_id = cpu_get_fpu_id();
285 mips_nofpu_msk31 = c->fpu_msk31;
286
287 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
288 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
289 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
290 if (c->fpu_id & MIPS_FPIR_3D)
291 c->ases |= MIPS_ASE_MIPS3D;
292 if (c->fpu_id & MIPS_FPIR_FREP)
293 c->options |= MIPS_CPU_FRE;
294 }
295
296 cpu_set_fpu_fcsr_mask(c);
93adeaf6 297 cpu_set_fpu_2008(c);
503943e0 298 cpu_set_nan_2008(c);
7aecd5ca
MR		 299}
300
301/*
302 * Set options for the FPU emulator.
303 */
304static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
305{
306 c->options &= ~MIPS_CPU_FPU;
307 c->fpu_msk31 = mips_nofpu_msk31;
308
93adeaf6 309 cpu_set_nofpu_2008(c);
503943e0 310 cpu_set_nan_2008(c);
7aecd5ca
MR		 311 cpu_set_nofpu_id(c);
312}
313
078a55fc 314static int mips_fpu_disabled;
0103d23f
KC		 315
316static int __init fpu_disable(char *s)
317{
7aecd5ca 318 cpu_set_nofpu_opts(&boot_cpu_data);
0103d23f
KC		 319 mips_fpu_disabled = 1;
320
321 return 1;
322}
323
324__setup("nofpu", fpu_disable);
325
078a55fc 326int mips_dsp_disabled;
0103d23f
KC		 327
328static int __init dsp_disable(char *s)
329{
ee80f7c7 330 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f
KC		 331 mips_dsp_disabled = 1;
332
333 return 1;
334}
335
336__setup("nodsp", dsp_disable);
337
3d528b32
MC		 338static int mips_htw_disabled;
339
340static int __init htw_disable(char *s)
341{
342 mips_htw_disabled = 1;
343 cpu_data[0].options &= ~MIPS_CPU_HTW;
344 write_c0_pwctl(read_c0_pwctl() &
345 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
346
347 return 1;
348}
349
350__setup("nohtw", htw_disable);
351
97f4ad29
MC		 352static int mips_ftlb_disabled;
353static int mips_has_ftlb_configured;
354
912708c2 355static int set_ftlb_enable(struct cpuinfo_mips *c, int enable);
97f4ad29
MC		 356
357static int __init ftlb_disable(char *s)
358{
359 unsigned int config4, mmuextdef;
360
361 /*
362 * If the core hasn't done any FTLB configuration, there is nothing
363 * for us to do here.
364 */
365 if (!mips_has_ftlb_configured)
366 return 1;
367
368 /* Disable it in the boot cpu */
912708c2
MC		 369 if (set_ftlb_enable(&cpu_data[0], 0)) {
370 pr_warn("Can't turn FTLB off\n");
371 return 1;
372 }
97f4ad29
MC		 373
374 back_to_back_c0_hazard();
375
376 config4 = read_c0_config4();
377
378 /* Check that FTLB has been disabled */
379 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
380 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
381 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
382 /* This should never happen */
383 pr_warn("FTLB could not be disabled!\n");
384 return 1;
385 }
386
387 mips_ftlb_disabled = 1;
388 mips_has_ftlb_configured = 0;
389
390 /*
391 * noftlb is mainly used for debug purposes so print
392 * an informative message instead of using pr_debug()
393 */
394 pr_info("FTLB has been disabled\n");
395
396 /*
397 * Some of these bits are duplicated in the decode_config4.
398 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
399 * once FTLB has been disabled so undo what decode_config4 did.
400 */
401 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
402 cpu_data[0].tlbsizeftlbsets;
403 cpu_data[0].tlbsizeftlbsets = 0;
404 cpu_data[0].tlbsizeftlbways = 0;
405
406 return 1;
407}
408
409__setup("noftlb", ftlb_disable);
410
411
9267a30d
MSJ		 412static inline void check_errata(void)
413{
414 struct cpuinfo_mips *c = &current_cpu_data;
415
69f24d17 416 switch (current_cpu_type()) {
9267a30d
MSJ		 417 case CPU_34K:
418 /*
419 * Erratum "RPS May Cause Incorrect Instruction Execution"
b633648c 420 * This code only handles VPE0, any SMP/RTOS code
9267a30d
MSJ		 421 * making use of VPE1 will be responsable for that VPE.
422 */
423 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
424 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
425 break;
426 default:
427 break;
428 }
429}
430
1da177e4
LT		 431void __init check_bugs32(void)
432{
9267a30d 433 check_errata();
1da177e4
LT		 434}
435
436/*
437 * Probe whether cpu has config register by trying to play with
438 * alternate cache bit and see whether it matters.
439 * It's used by cpu_probe to distinguish between R3000A and R3081.
440 */
441static inline int cpu_has_confreg(void)
442{
443#ifdef CONFIG_CPU_R3000
444 extern unsigned long r3k_cache_size(unsigned long);
445 unsigned long size1, size2;
446 unsigned long cfg = read_c0_conf();
447
448 size1 = r3k_cache_size(ST0_ISC);
449 write_c0_conf(cfg ^ R30XX_CONF_AC);
450 size2 = r3k_cache_size(ST0_ISC);
451 write_c0_conf(cfg);
452 return size1 != size2;
453#else
454 return 0;
455#endif
456}
457
c094c99e
RM		 458static inline void set_elf_platform(int cpu, const char *plat)
459{
460 if (cpu == 0)
461 __elf_platform = plat;
462}
463
91dfc423
GR		 464static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
465{
466#ifdef __NEED_VMBITS_PROBE
5b7efa89 467 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 468 back_to_back_c0_hazard();
5b7efa89 469 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 470#endif
471}
472
078a55fc 473static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
a96102be
SH		 474{
475 switch (isa) {
476 case MIPS_CPU_ISA_M64R2:
477 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
478 case MIPS_CPU_ISA_M64R1:
479 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
480 case MIPS_CPU_ISA_V:
481 c->isa_level |= MIPS_CPU_ISA_V;
482 case MIPS_CPU_ISA_IV:
483 c->isa_level |= MIPS_CPU_ISA_IV;
484 case MIPS_CPU_ISA_III:
1990e542 485 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
a96102be
SH		 486 break;
487
8b8aa636
LY		 488 /* R6 incompatible with everything else */
489 case MIPS_CPU_ISA_M64R6:
490 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
491 case MIPS_CPU_ISA_M32R6:
492 c->isa_level |= MIPS_CPU_ISA_M32R6;
493 /* Break here so we don't add incompatible ISAs */
494 break;
a96102be
SH		 495 case MIPS_CPU_ISA_M32R2:
496 c->isa_level |= MIPS_CPU_ISA_M32R2;
497 case MIPS_CPU_ISA_M32R1:
498 c->isa_level |= MIPS_CPU_ISA_M32R1;
499 case MIPS_CPU_ISA_II:
500 c->isa_level |= MIPS_CPU_ISA_II;
a96102be
SH		 501 break;
502 }
503}
504
078a55fc 505static char unknown_isa[] = KERN_ERR \
2fa36399
KC		 506 "Unsupported ISA type, c0.config0: %d.";
507
cf0a8aa0
MC		 508static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
509{
510
511 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
512
513 /*
514 * 0 = All TLBWR instructions go to FTLB
515 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
516 * FTLB and 1 goes to the VTLB.
517 * 2 = 7:1: As above with 7:1 ratio.
518 * 3 = 3:1: As above with 3:1 ratio.
519 *
520 * Use the linear midpoint as the probability threshold.
521 */
522 if (probability >= 12)
523 return 1;
524 else if (probability >= 6)
525 return 2;
526 else
527 /*
528 * So FTLB is less than 4 times bigger than VTLB.
529 * A 3:1 ratio can still be useful though.
530 */
531 return 3;
532}
533
912708c2 534static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
75b5b5e0 535{
20a7f7e5 536 unsigned int config;
d83b0e82
JH		 537
538 /* It's implementation dependent how the FTLB can be enabled */
539 switch (c->cputype) {
540 case CPU_PROAPTIV:
541 case CPU_P5600:
1091bfa2 542 case CPU_P6600:
d83b0e82 543 /* proAptiv & related cores use Config6 to enable the FTLB */
20a7f7e5 544 config = read_c0_config6();
cf0a8aa0 545 /* Clear the old probability value */
20a7f7e5 546 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
75b5b5e0
LY		 547 if (enable)
548 /* Enable FTLB */
20a7f7e5 549 write_c0_config6(config |
cf0a8aa0
MC		 550 (calculate_ftlb_probability(c)
551 << MIPS_CONF6_FTLBP_SHIFT)
552 | MIPS_CONF6_FTLBEN);
75b5b5e0
LY		 553 else
554 /* Disable FTLB */
20a7f7e5
MC		 555 write_c0_config6(config & ~MIPS_CONF6_FTLBEN);
556 break;
557 case CPU_I6400:
558 /* I6400 & related cores use Config7 to configure FTLB */
559 config = read_c0_config7();
560 /* Clear the old probability value */
561 config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT);
562 write_c0_config7(config | (calculate_ftlb_probability(c)
563 << MIPS_CONF7_FTLBP_SHIFT));
d83b0e82 564 break;
912708c2
MC		 565 default:
566 return 1;
75b5b5e0 567 }
912708c2
MC		 568
569 return 0;
75b5b5e0
LY		 570}
571
2fa36399
KC		 572static inline unsigned int decode_config0(struct cpuinfo_mips *c)
573{
574 unsigned int config0;
2f6f3136 575 int isa, mt;
2fa36399
KC		 576
577 config0 = read_c0_config();
578
75b5b5e0
LY		 579 /*
580 * Look for Standard TLB or Dual VTLB and FTLB
581 */
2f6f3136
JH		 582 mt = config0 & MIPS_CONF_MT;
583 if (mt == MIPS_CONF_MT_TLB)
2fa36399 584 c->options |= MIPS_CPU_TLB;
2f6f3136
JH		 585 else if (mt == MIPS_CONF_MT_FTLB)
586 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
75b5b5e0 587
2fa36399
KC		 588 isa = (config0 & MIPS_CONF_AT) >> 13;
589 switch (isa) {
590 case 0:
591 switch ((config0 & MIPS_CONF_AR) >> 10) {
592 case 0:
a96102be 593 set_isa(c, MIPS_CPU_ISA_M32R1);
2fa36399
KC		 594 break;
595 case 1:
a96102be 596 set_isa(c, MIPS_CPU_ISA_M32R2);
2fa36399 597 break;
8b8aa636
LY		 598 case 2:
599 set_isa(c, MIPS_CPU_ISA_M32R6);
600 break;
2fa36399
KC		 601 default:
602 goto unknown;
603 }
604 break;
605 case 2:
606 switch ((config0 & MIPS_CONF_AR) >> 10) {
607 case 0:
a96102be 608 set_isa(c, MIPS_CPU_ISA_M64R1);
2fa36399
KC		 609 break;
610 case 1:
a96102be 611 set_isa(c, MIPS_CPU_ISA_M64R2);
2fa36399 612 break;
8b8aa636
LY		 613 case 2:
614 set_isa(c, MIPS_CPU_ISA_M64R6);
615 break;
2fa36399
KC		 616 default:
617 goto unknown;
618 }
619 break;
620 default:
621 goto unknown;
622 }
623
624 return config0 & MIPS_CONF_M;
625
626unknown:
627 panic(unknown_isa, config0);
628}
629
630static inline unsigned int decode_config1(struct cpuinfo_mips *c)
631{
632 unsigned int config1;
633
634 config1 = read_c0_config1();
635
636 if (config1 & MIPS_CONF1_MD)
637 c->ases |= MIPS_ASE_MDMX;
638 if (config1 & MIPS_CONF1_WR)
639 c->options |= MIPS_CPU_WATCH;
640 if (config1 & MIPS_CONF1_CA)
641 c->ases |= MIPS_ASE_MIPS16;
642 if (config1 & MIPS_CONF1_EP)
643 c->options |= MIPS_CPU_EJTAG;
644 if (config1 & MIPS_CONF1_FP) {
645 c->options |= MIPS_CPU_FPU;
646 c->options |= MIPS_CPU_32FPR;
647 }
75b5b5e0 648 if (cpu_has_tlb) {
2fa36399 649 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
75b5b5e0
LY		 650 c->tlbsizevtlb = c->tlbsize;
651 c->tlbsizeftlbsets = 0;
652 }
2fa36399
KC		 653
654 return config1 & MIPS_CONF_M;
655}
656
657static inline unsigned int decode_config2(struct cpuinfo_mips *c)
658{
659 unsigned int config2;
660
661 config2 = read_c0_config2();
662
663 if (config2 & MIPS_CONF2_SL)
664 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
665
666 return config2 & MIPS_CONF_M;
667}
668
669static inline unsigned int decode_config3(struct cpuinfo_mips *c)
670{
671 unsigned int config3;
672
673 config3 = read_c0_config3();
674
b2ab4f08 675 if (config3 & MIPS_CONF3_SM) {
2fa36399 676 c->ases |= MIPS_ASE_SMARTMIPS;
b2ab4f08
SH		 677 c->options |= MIPS_CPU_RIXI;
678 }
679 if (config3 & MIPS_CONF3_RXI)
680 c->options |= MIPS_CPU_RIXI;
2fa36399
KC		 681 if (config3 & MIPS_CONF3_DSP)
682 c->ases |= MIPS_ASE_DSP;
b5a6455c 683 if (config3 & MIPS_CONF3_DSP2P) {
ee80f7c7 684 c->ases |= MIPS_ASE_DSP2P;
b5a6455c
ZLK		 685 if (cpu_has_mips_r6)
686 c->ases |= MIPS_ASE_DSP3;
687 }
2fa36399
KC		 688 if (config3 & MIPS_CONF3_VINT)
689 c->options |= MIPS_CPU_VINT;
690 if (config3 & MIPS_CONF3_VEIC)
691 c->options |= MIPS_CPU_VEIC;
692 if (config3 & MIPS_CONF3_MT)
693 c->ases |= MIPS_ASE_MIPSMT;
694 if (config3 & MIPS_CONF3_ULRI)
695 c->options |= MIPS_CPU_ULRI;
f8fa4811
SH		 696 if (config3 & MIPS_CONF3_ISA)
697 c->options |= MIPS_CPU_MICROMIPS;
1e7decdb
DD		 698 if (config3 & MIPS_CONF3_VZ)
699 c->ases |= MIPS_ASE_VZ;
4a0156fb
SH		 700 if (config3 & MIPS_CONF3_SC)
701 c->options |= MIPS_CPU_SEGMENTS;
a5e9a69e
PB		 702 if (config3 & MIPS_CONF3_MSA)
703 c->ases |= MIPS_ASE_MSA;
cab25bc7 704 if (config3 & MIPS_CONF3_PW) {
ed4cbc81 705 c->htw_seq = 0;
3d528b32 706 c->options |= MIPS_CPU_HTW;
ed4cbc81 707 }
9b3274bd
JH		 708 if (config3 & MIPS_CONF3_CDMM)
709 c->options |= MIPS_CPU_CDMM;
aaa7be48
JH		 710 if (config3 & MIPS_CONF3_SP)
711 c->options |= MIPS_CPU_SP;
2fa36399
KC		 712
713 return config3 & MIPS_CONF_M;
714}
715
716static inline unsigned int decode_config4(struct cpuinfo_mips *c)
717{
718 unsigned int config4;
75b5b5e0
LY		 719 unsigned int newcf4;
720 unsigned int mmuextdef;
721 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
2fa36399
KC		 722
723 config4 = read_c0_config4();
724
1745c1ef
LY		 725 if (cpu_has_tlb) {
726 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
727 c->options |= MIPS_CPU_TLBINV;
43d104db 728
e87569cd 729 /*
43d104db
JH		 730 * R6 has dropped the MMUExtDef field from config4.
731 * On R6 the fields always describe the FTLB, and only if it is
732 * present according to Config.MT.
e87569cd 733 */
43d104db
JH		 734 if (!cpu_has_mips_r6)
735 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
736 else if (cpu_has_ftlb)
e87569cd
MC		 737 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
738 else
43d104db 739 mmuextdef = 0;
e87569cd 740
75b5b5e0
LY		 741 switch (mmuextdef) {
742 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
743 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
744 c->tlbsizevtlb = c->tlbsize;
745 break;
746 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
747 c->tlbsizevtlb +=
748 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
749 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
750 c->tlbsize = c->tlbsizevtlb;
751 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
752 /* fall through */
753 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
97f4ad29
MC		 754 if (mips_ftlb_disabled)
755 break;
75b5b5e0
LY		 756 newcf4 = (config4 & ~ftlb_page) |
757 (page_size_ftlb(mmuextdef) <<
758 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
759 write_c0_config4(newcf4);
760 back_to_back_c0_hazard();
761 config4 = read_c0_config4();
762 if (config4 != newcf4) {
763 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
764 PAGE_SIZE, config4);
765 /* Switch FTLB off */
766 set_ftlb_enable(c, 0);
767 break;
768 }
769 c->tlbsizeftlbsets = 1 <<
770 ((config4 & MIPS_CONF4_FTLBSETS) >>
771 MIPS_CONF4_FTLBSETS_SHIFT);
772 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
773 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
774 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
97f4ad29 775 mips_has_ftlb_configured = 1;
75b5b5e0
LY		 776 break;
777 }
1745c1ef
LY		 778 }
779
2fa36399
KC		 780 c->kscratch_mask = (config4 >> 16) & 0xff;
781
782 return config4 & MIPS_CONF_M;
783}
784
8b8a7634
RB		 785static inline unsigned int decode_config5(struct cpuinfo_mips *c)
786{
787 unsigned int config5;
788
789 config5 = read_c0_config5();
d175ed2b 790 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
8b8a7634
RB		 791 write_c0_config5(config5);
792
49016748
MC		 793 if (config5 & MIPS_CONF5_EVA)
794 c->options |= MIPS_CPU_EVA;
1f6c52ff
PB		 795 if (config5 & MIPS_CONF5_MRP)
796 c->options |= MIPS_CPU_MAAR;
5aed9da1
MC		 797 if (config5 & MIPS_CONF5_LLB)
798 c->options |= MIPS_CPU_RW_LLB;
c5b36783
SH		 799#ifdef CONFIG_XPA
800 if (config5 & MIPS_CONF5_MVH)
801 c->options |= MIPS_CPU_XPA;
802#endif
f270d881
PB		 803 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
804 c->options |= MIPS_CPU_VP;
49016748 805
8b8a7634
RB		 806 return config5 & MIPS_CONF_M;
807}
808
078a55fc 809static void decode_configs(struct cpuinfo_mips *c)
2fa36399
KC		 810{
811 int ok;
812
813 /* MIPS32 or MIPS64 compliant CPU. */
814 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
815 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
816
817 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
818
97f4ad29
MC		 819 /* Enable FTLB if present and not disabled */
820 set_ftlb_enable(c, !mips_ftlb_disabled);
75b5b5e0 821
2fa36399 822 ok = decode_config0(c); /* Read Config registers. */
70342287 823 BUG_ON(!ok); /* Arch spec violation! */
2fa36399
KC		 824 if (ok)
825 ok = decode_config1(c);
826 if (ok)
827 ok = decode_config2(c);
828 if (ok)
829 ok = decode_config3(c);
830 if (ok)
831 ok = decode_config4(c);
8b8a7634
RB		 832 if (ok)
833 ok = decode_config5(c);
2fa36399
KC		 834
835 mips_probe_watch_registers(c);
836
6575b1d4
LY		 837 if (cpu_has_rixi) {
838 /* Enable the RIXI exceptions */
a5770df0 839 set_c0_pagegrain(PG_IEC);
6575b1d4
LY		 840 back_to_back_c0_hazard();
841 /* Verify the IEC bit is set */
842 if (read_c0_pagegrain() & PG_IEC)
843 c->options |= MIPS_CPU_RIXIEX;
844 }
845
0ee958e1 846#ifndef CONFIG_MIPS_CPS
8b8aa636 847 if (cpu_has_mips_r2_r6) {
45b585c8 848 c->core = get_ebase_cpunum();
30ee615b
PB		 849 if (cpu_has_mipsmt)
850 c->core >>= fls(core_nvpes()) - 1;
851 }
0ee958e1 852#endif
2fa36399
KC		 853}
854
02cf2119 855#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 856 | MIPS_CPU_COUNTER)
857
cea7e2df 858static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 859{
8ff374b9 860 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 861 case PRID_IMP_R2000:
862 c->cputype = CPU_R2000;
cea7e2df 863 __cpu_name[cpu] = "R2000";
9b26616c 864 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 865 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 866 MIPS_CPU_NOFPUEX;
1da177e4
LT		 867 if (__cpu_has_fpu())
868 c->options |= MIPS_CPU_FPU;
869 c->tlbsize = 64;
870 break;
871 case PRID_IMP_R3000:
8ff374b9 872 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
cea7e2df 873 if (cpu_has_confreg()) {
1da177e4 874 c->cputype = CPU_R3081E;
cea7e2df
RB		 875 __cpu_name[cpu] = "R3081";
876 } else {
1da177e4 877 c->cputype = CPU_R3000A;
cea7e2df
RB		 878 __cpu_name[cpu] = "R3000A";
879 }
cea7e2df 880 } else {
1da177e4 881 c->cputype = CPU_R3000;
cea7e2df
RB		 882 __cpu_name[cpu] = "R3000";
883 }
9b26616c 884 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 885 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 886 MIPS_CPU_NOFPUEX;
1da177e4
LT		 887 if (__cpu_has_fpu())
888 c->options |= MIPS_CPU_FPU;
889 c->tlbsize = 64;
890 break;
891 case PRID_IMP_R4000:
892 if (read_c0_config() & CONF_SC) {
8ff374b9
MR		 893 if ((c->processor_id & PRID_REV_MASK) >=
894 PRID_REV_R4400) {
1da177e4 895 c->cputype = CPU_R4400PC;
cea7e2df
RB		 896 __cpu_name[cpu] = "R4400PC";
897 } else {
1da177e4 898 c->cputype = CPU_R4000PC;
cea7e2df
RB		 899 __cpu_name[cpu] = "R4000PC";
900 }
1da177e4 901 } else {
7f177a52
MR		 902 int cca = read_c0_config() & CONF_CM_CMASK;
903 int mc;
904
905 /*
906 * SC and MC versions can't be reliably told apart,
907 * but only the latter support coherent caching
908 * modes so assume the firmware has set the KSEG0
909 * coherency attribute reasonably (if uncached, we
910 * assume SC).
911 */
912 switch (cca) {
913 case CONF_CM_CACHABLE_CE:
914 case CONF_CM_CACHABLE_COW:
915 case CONF_CM_CACHABLE_CUW:
916 mc = 1;
917 break;
918 default:
919 mc = 0;
920 break;
921 }
8ff374b9
MR		 922 if ((c->processor_id & PRID_REV_MASK) >=
923 PRID_REV_R4400) {
7f177a52
MR		 924 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
925 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
cea7e2df 926 } else {
7f177a52
MR		 927 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
928 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
cea7e2df 929 }
1da177e4
LT		 930 }
931
a96102be 932 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 933 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 934 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 935 MIPS_CPU_WATCH | MIPS_CPU_VCE |
936 MIPS_CPU_LLSC;
1da177e4
LT		 937 c->tlbsize = 48;
938 break;
939 case PRID_IMP_VR41XX:
9f91e506 940 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 941 c->fpu_msk31 |= FPU_CSR_CONDX;
9f91e506
YY		 942 c->options = R4K_OPTS;
943 c->tlbsize = 32;
1da177e4 944 switch (c->processor_id & 0xf0) {
1da177e4
LT		 945 case PRID_REV_VR4111:
946 c->cputype = CPU_VR4111;
cea7e2df 947 __cpu_name[cpu] = "NEC VR4111";
1da177e4 948 break;
1da177e4
LT		 949 case PRID_REV_VR4121:
950 c->cputype = CPU_VR4121;
cea7e2df 951 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 952 break;
953 case PRID_REV_VR4122:
cea7e2df 954 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 955 c->cputype = CPU_VR4122;
cea7e2df
RB		 956 __cpu_name[cpu] = "NEC VR4122";
957 } else {
1da177e4 958 c->cputype = CPU_VR4181A;
cea7e2df
RB		 959 __cpu_name[cpu] = "NEC VR4181A";
960 }
1da177e4
LT		 961 break;
962 case PRID_REV_VR4130:
cea7e2df 963 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 964 c->cputype = CPU_VR4131;
cea7e2df
RB		 965 __cpu_name[cpu] = "NEC VR4131";
966 } else {
1da177e4 967 c->cputype = CPU_VR4133;
9f91e506 968 c->options |= MIPS_CPU_LLSC;
cea7e2df
RB		 969 __cpu_name[cpu] = "NEC VR4133";
970 }
1da177e4
LT		 971 break;
972 default:
973 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
974 c->cputype = CPU_VR41XX;
cea7e2df 975 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 976 break;
977 }
1da177e4
LT		 978 break;
979 case PRID_IMP_R4300:
980 c->cputype = CPU_R4300;
cea7e2df 981 __cpu_name[cpu] = "R4300";
a96102be 982 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 983 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 984 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 985 MIPS_CPU_LLSC;
1da177e4
LT		 986 c->tlbsize = 32;
987 break;
988 case PRID_IMP_R4600:
989 c->cputype = CPU_R4600;
cea7e2df 990 __cpu_name[cpu] = "R4600";
a96102be 991 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 992 c->fpu_msk31 |= FPU_CSR_CONDX;
075e7502
TS		 993 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
994 MIPS_CPU_LLSC;
1da177e4
LT		 995 c->tlbsize = 48;
996 break;
997 #if 0
03751e79 998 case PRID_IMP_R4650:
1da177e4
LT		 999 /*
1000 * This processor doesn't have an MMU, so it's not
1001 * "real easy" to run Linux on it. It is left purely
1002 * for documentation. Commented out because it shares
1003 * it's c0_prid id number with the TX3900.
1004 */
a3dddd56 1005 c->cputype = CPU_R4650;
cea7e2df 1006 __cpu_name[cpu] = "R4650";
a96102be 1007 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1008 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 1009 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 1010 c->tlbsize = 48;
1da177e4
LT		 1011 break;
1012 #endif
1013 case PRID_IMP_TX39:
9b26616c 1014 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 1015 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 1016
1017 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1018 c->cputype = CPU_TX3927;
cea7e2df 1019 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 1020 c->tlbsize = 64;
1021 } else {
8ff374b9 1022 switch (c->processor_id & PRID_REV_MASK) {
1da177e4
LT		 1023 case PRID_REV_TX3912:
1024 c->cputype = CPU_TX3912;
cea7e2df 1025 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 1026 c->tlbsize = 32;
1027 break;
1028 case PRID_REV_TX3922:
1029 c->cputype = CPU_TX3922;
cea7e2df 1030 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 1031 c->tlbsize = 64;
1032 break;
1da177e4
LT		 1033 }
1034 }
1035 break;
1036 case PRID_IMP_R4700:
1037 c->cputype = CPU_R4700;
cea7e2df 1038 __cpu_name[cpu] = "R4700";
a96102be 1039 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1040 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 1041 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1042 MIPS_CPU_LLSC;
1da177e4
LT		 1043 c->tlbsize = 48;
1044 break;
1045 case PRID_IMP_TX49:
1046 c->cputype = CPU_TX49XX;
cea7e2df 1047 __cpu_name[cpu] = "R49XX";
a96102be 1048 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1049 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4
LT		 1050 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1051 if (!(c->processor_id & 0x08))
1052 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1053 c->tlbsize = 48;
1054 break;
1055 case PRID_IMP_R5000:
1056 c->cputype = CPU_R5000;
cea7e2df 1057 __cpu_name[cpu] = "R5000";
a96102be 1058 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1059 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1060 MIPS_CPU_LLSC;
1da177e4
LT		 1061 c->tlbsize = 48;
1062 break;
1063 case PRID_IMP_R5432:
1064 c->cputype = CPU_R5432;
cea7e2df 1065 __cpu_name[cpu] = "R5432";
a96102be 1066 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1067 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1068 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 1069 c->tlbsize = 48;
1070 break;
1071 case PRID_IMP_R5500:
1072 c->cputype = CPU_R5500;
cea7e2df 1073 __cpu_name[cpu] = "R5500";
a96102be 1074 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1075 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1076 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 1077 c->tlbsize = 48;
1078 break;
1079 case PRID_IMP_NEVADA:
1080 c->cputype = CPU_NEVADA;
cea7e2df 1081 __cpu_name[cpu] = "Nevada";
a96102be 1082 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1083 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1084 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 1085 c->tlbsize = 48;
1086 break;
1087 case PRID_IMP_R6000:
1088 c->cputype = CPU_R6000;
cea7e2df 1089 __cpu_name[cpu] = "R6000";
a96102be 1090 set_isa(c, MIPS_CPU_ISA_II);
9b26616c 1091 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1da177e4 1092 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 1093 MIPS_CPU_LLSC;
1da177e4
LT		 1094 c->tlbsize = 32;
1095 break;
1096 case PRID_IMP_R6000A:
1097 c->cputype = CPU_R6000A;
cea7e2df 1098 __cpu_name[cpu] = "R6000A";
a96102be 1099 set_isa(c, MIPS_CPU_ISA_II);
9b26616c 1100 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1da177e4 1101 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 1102 MIPS_CPU_LLSC;
1da177e4
LT		 1103 c->tlbsize = 32;
1104 break;
1105 case PRID_IMP_RM7000:
1106 c->cputype = CPU_RM7000;
cea7e2df 1107 __cpu_name[cpu] = "RM7000";
a96102be 1108 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1109 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1110 MIPS_CPU_LLSC;
1da177e4 1111 /*
70342287 1112 * Undocumented RM7000: Bit 29 in the info register of
1da177e4
LT		 1113 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1114 * entries.
1115 *
70342287
RB		 1116 * 29 1 => 64 entry JTLB
1117 * 0 => 48 entry JTLB
1da177e4
LT		 1118 */
1119 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1da177e4
LT		 1120 break;
1121 case PRID_IMP_R8000:
1122 c->cputype = CPU_R8000;
cea7e2df 1123 __cpu_name[cpu] = "RM8000";
a96102be 1124 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1125 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 1126 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1127 MIPS_CPU_LLSC;
1da177e4
LT		 1128 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
1129 break;
1130 case PRID_IMP_R10000:
1131 c->cputype = CPU_R10000;
cea7e2df 1132 __cpu_name[cpu] = "R10000";
a96102be 1133 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 1134 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 1135 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 1136 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 1137 MIPS_CPU_LLSC;
1da177e4
LT		 1138 c->tlbsize = 64;
1139 break;
1140 case PRID_IMP_R12000:
1141 c->cputype = CPU_R12000;
cea7e2df 1142 __cpu_name[cpu] = "R12000";
a96102be 1143 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 1144 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 1145 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 1146 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
8d5ded16 1147 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1da177e4
LT		 1148 c->tlbsize = 64;
1149 break;
44d921b2 1150 case PRID_IMP_R14000:
30577391
JK		 1151 if (((c->processor_id >> 4) & 0x0f) > 2) {
1152 c->cputype = CPU_R16000;
1153 __cpu_name[cpu] = "R16000";
1154 } else {
1155 c->cputype = CPU_R14000;
1156 __cpu_name[cpu] = "R14000";
1157 }
a96102be 1158 set_isa(c, MIPS_CPU_ISA_IV);
44d921b2 1159 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 1160 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 1161 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
8d5ded16 1162 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
44d921b2
K		 1163 c->tlbsize = 64;
1164 break;
26859198 1165 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
5aac1e8a
RM		 1166 switch (c->processor_id & PRID_REV_MASK) {
1167 case PRID_REV_LOONGSON2E:
c579d310
HC		 1168 c->cputype = CPU_LOONGSON2;
1169 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 1170 set_elf_platform(cpu, "loongson2e");
7352c8b1 1171 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1172 c->fpu_msk31 |= FPU_CSR_CONDX;
5aac1e8a
RM		 1173 break;
1174 case PRID_REV_LOONGSON2F:
c579d310
HC		 1175 c->cputype = CPU_LOONGSON2;
1176 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 1177 set_elf_platform(cpu, "loongson2f");
7352c8b1 1178 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1179 c->fpu_msk31 |= FPU_CSR_CONDX;
5aac1e8a 1180 break;
c579d310
HC		 1181 case PRID_REV_LOONGSON3A:
1182 c->cputype = CPU_LOONGSON3;
1183 __cpu_name[cpu] = "ICT Loongson-3";
1184 set_elf_platform(cpu, "loongson3a");
7352c8b1 1185 set_isa(c, MIPS_CPU_ISA_M64R1);
c579d310 1186 break;
e7841be5
HC		 1187 case PRID_REV_LOONGSON3B_R1:
1188 case PRID_REV_LOONGSON3B_R2:
1189 c->cputype = CPU_LOONGSON3;
1190 __cpu_name[cpu] = "ICT Loongson-3";
1191 set_elf_platform(cpu, "loongson3b");
7352c8b1 1192 set_isa(c, MIPS_CPU_ISA_M64R1);
e7841be5 1193 break;
5aac1e8a
RM		 1194 }
1195
2a21c730
FZ		 1196 c->options = R4K_OPTS |
1197 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1198 MIPS_CPU_32FPR;
1199 c->tlbsize = 64;
cc94ea31 1200 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2a21c730 1201 break;
26859198 1202 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
2fa36399 1203 decode_configs(c);
b4672d37 1204
2fa36399 1205 c->cputype = CPU_LOONGSON1;
1da177e4 1206
2fa36399
KC		 1207 switch (c->processor_id & PRID_REV_MASK) {
1208 case PRID_REV_LOONGSON1B:
1209 __cpu_name[cpu] = "Loongson 1B";
b4672d37 1210 break;
b4672d37 1211 }
4194318c 1212
2fa36399 1213 break;
1da177e4 1214 }
1da177e4
LT		 1215}
1216
cea7e2df 1217static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1218{
4f12b91d 1219 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 1220 switch (c->processor_id & PRID_IMP_MASK) {
b2498af5
LY		 1221 case PRID_IMP_QEMU_GENERIC:
1222 c->writecombine = _CACHE_UNCACHED;
1223 c->cputype = CPU_QEMU_GENERIC;
1224 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1225 break;
1da177e4
LT		 1226 case PRID_IMP_4KC:
1227 c->cputype = CPU_4KC;
4f12b91d 1228 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1229 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 1230 break;
1231 case PRID_IMP_4KEC:
2b07bd02
RB		 1232 case PRID_IMP_4KECR2:
1233 c->cputype = CPU_4KEC;
4f12b91d 1234 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1235 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 1236 break;
1da177e4 1237 case PRID_IMP_4KSC:
8afcb5d8 1238 case PRID_IMP_4KSD:
1da177e4 1239 c->cputype = CPU_4KSC;
4f12b91d 1240 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1241 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 1242 break;
1243 case PRID_IMP_5KC:
1244 c->cputype = CPU_5KC;
4f12b91d 1245 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1246 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4 1247 break;
78d4803f
LY		 1248 case PRID_IMP_5KE:
1249 c->cputype = CPU_5KE;
4f12b91d 1250 c->writecombine = _CACHE_UNCACHED;
78d4803f
LY		 1251 __cpu_name[cpu] = "MIPS 5KE";
1252 break;
1da177e4
LT		 1253 case PRID_IMP_20KC:
1254 c->cputype = CPU_20KC;
4f12b91d 1255 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1256 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 1257 break;
1258 case PRID_IMP_24K:
1259 c->cputype = CPU_24K;
4f12b91d 1260 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1261 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4 1262 break;
42f3caef
JC		 1263 case PRID_IMP_24KE:
1264 c->cputype = CPU_24K;
4f12b91d 1265 c->writecombine = _CACHE_UNCACHED;
42f3caef
JC		 1266 __cpu_name[cpu] = "MIPS 24KEc";
1267 break;
1da177e4
LT		 1268 case PRID_IMP_25KF:
1269 c->cputype = CPU_25KF;
4f12b91d 1270 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1271 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 1272 break;
bbc7f22f
RB		 1273 case PRID_IMP_34K:
1274 c->cputype = CPU_34K;
4f12b91d 1275 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1276 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 1277 break;
c620953c
CD		 1278 case PRID_IMP_74K:
1279 c->cputype = CPU_74K;
4f12b91d 1280 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1281 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 1282 break;
113c62d9
SH		 1283 case PRID_IMP_M14KC:
1284 c->cputype = CPU_M14KC;
4f12b91d 1285 c->writecombine = _CACHE_UNCACHED;
113c62d9
SH		 1286 __cpu_name[cpu] = "MIPS M14Kc";
1287 break;
f8fa4811
SH		 1288 case PRID_IMP_M14KEC:
1289 c->cputype = CPU_M14KEC;
4f12b91d 1290 c->writecombine = _CACHE_UNCACHED;
f8fa4811
SH		 1291 __cpu_name[cpu] = "MIPS M14KEc";
1292 break;
39b8d525
RB		 1293 case PRID_IMP_1004K:
1294 c->cputype = CPU_1004K;
4f12b91d 1295 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1296 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 1297 break;
006a851b 1298 case PRID_IMP_1074K:
442e14a2 1299 c->cputype = CPU_1074K;
4f12b91d 1300 c->writecombine = _CACHE_UNCACHED;
006a851b
SH		 1301 __cpu_name[cpu] = "MIPS 1074Kc";
1302 break;
b5f065e7
LY		 1303 case PRID_IMP_INTERAPTIV_UP:
1304 c->cputype = CPU_INTERAPTIV;
1305 __cpu_name[cpu] = "MIPS interAptiv";
1306 break;
1307 case PRID_IMP_INTERAPTIV_MP:
1308 c->cputype = CPU_INTERAPTIV;
1309 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1310 break;
b0d4d300
LY		 1311 case PRID_IMP_PROAPTIV_UP:
1312 c->cputype = CPU_PROAPTIV;
1313 __cpu_name[cpu] = "MIPS proAptiv";
1314 break;
1315 case PRID_IMP_PROAPTIV_MP:
1316 c->cputype = CPU_PROAPTIV;
1317 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1318 break;
829dcc0a
JH		 1319 case PRID_IMP_P5600:
1320 c->cputype = CPU_P5600;
1321 __cpu_name[cpu] = "MIPS P5600";
1322 break;
eba20a3a
PB		 1323 case PRID_IMP_P6600:
1324 c->cputype = CPU_P6600;
1325 __cpu_name[cpu] = "MIPS P6600";
1326 break;
e57f9a2d
MC		 1327 case PRID_IMP_I6400:
1328 c->cputype = CPU_I6400;
1329 __cpu_name[cpu] = "MIPS I6400";
1330 break;
9943ed92
LY		 1331 case PRID_IMP_M5150:
1332 c->cputype = CPU_M5150;
1333 __cpu_name[cpu] = "MIPS M5150";
1334 break;
43aff742
PB		 1335 case PRID_IMP_M6250:
1336 c->cputype = CPU_M6250;
1337 __cpu_name[cpu] = "MIPS M6250";
1338 break;
1da177e4 1339 }
0b6d497f 1340
75b5b5e0
LY		 1341 decode_configs(c);
1342
0b6d497f 1343 spram_config();
1da177e4
LT		 1344}
1345
cea7e2df 1346static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1347{
4194318c 1348 decode_configs(c);
8ff374b9 1349 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1350 case PRID_IMP_AU1_REV1:
1351 case PRID_IMP_AU1_REV2:
270717a8 1352 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 1353 switch ((c->processor_id >> 24) & 0xff) {
1354 case 0:
cea7e2df 1355 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 1356 break;
1357 case 1:
cea7e2df 1358 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 1359 break;
1360 case 2:
cea7e2df 1361 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 1362 break;
1363 case 3:
cea7e2df 1364 __cpu_name[cpu] = "Au1550";
1da177e4 1365 break;
e3ad1c23 1366 case 4:
cea7e2df 1367 __cpu_name[cpu] = "Au1200";
8ff374b9 1368 if ((c->processor_id & PRID_REV_MASK) == 2)
cea7e2df 1369 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 1370 break;
1371 case 5:
cea7e2df 1372 __cpu_name[cpu] = "Au1210";
e3ad1c23 1373 break;
1da177e4 1374 default:
270717a8 1375 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 1376 break;
1377 }
1da177e4
LT		 1378 break;
1379 }
1380}
1381
cea7e2df 1382static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1383{
4194318c 1384 decode_configs(c);
02cf2119 1385
4f12b91d 1386 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 1387 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1388 case PRID_IMP_SB1:
1389 c->cputype = CPU_SB1;
cea7e2df 1390 __cpu_name[cpu] = "SiByte SB1";
1da177e4 1391 /* FPU in pass1 is known to have issues. */
8ff374b9 1392 if ((c->processor_id & PRID_REV_MASK) < 0x02)
010b853b 1393 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 1394 break;
93ce2f52
AI		 1395 case PRID_IMP_SB1A:
1396 c->cputype = CPU_SB1A;
cea7e2df 1397 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 1398 break;
1da177e4
LT		 1399 }
1400}
1401
cea7e2df 1402static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1403{
4194318c 1404 decode_configs(c);
8ff374b9 1405 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1406 case PRID_IMP_SR71000:
1407 c->cputype = CPU_SR71000;
cea7e2df 1408 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 1409 c->scache.ways = 8;
1410 c->tlbsize = 64;
1411 break;
1412 }
1413}
1414
cea7e2df 1415static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 1416{
1417 decode_configs(c);
8ff374b9 1418 switch (c->processor_id & PRID_IMP_MASK) {
bdf21b18
PP		 1419 case PRID_IMP_PR4450:
1420 c->cputype = CPU_PR4450;
cea7e2df 1421 __cpu_name[cpu] = "Philips PR4450";
a96102be 1422 set_isa(c, MIPS_CPU_ISA_M32R1);
bdf21b18 1423 break;
bdf21b18
PP		 1424 }
1425}
1426
cea7e2df 1427static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 1428{
1429 decode_configs(c);
8ff374b9 1430 switch (c->processor_id & PRID_IMP_MASK) {
190fca3e
KC		 1431 case PRID_IMP_BMIPS32_REV4:
1432 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 1433 c->cputype = CPU_BMIPS32;
1434 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 1435 set_elf_platform(cpu, "bmips32");
602977b0
KC		 1436 break;
1437 case PRID_IMP_BMIPS3300:
1438 case PRID_IMP_BMIPS3300_ALT:
1439 case PRID_IMP_BMIPS3300_BUG:
1440 c->cputype = CPU_BMIPS3300;
1441 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 1442 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 1443 break;
1444 case PRID_IMP_BMIPS43XX: {
8ff374b9 1445 int rev = c->processor_id & PRID_REV_MASK;
602977b0
KC		 1446
1447 if (rev >= PRID_REV_BMIPS4380_LO &&
1448 rev <= PRID_REV_BMIPS4380_HI) {
1449 c->cputype = CPU_BMIPS4380;
1450 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 1451 set_elf_platform(cpu, "bmips4380");
602977b0
KC		 1452 } else {
1453 c->cputype = CPU_BMIPS4350;
1454 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 1455 set_elf_platform(cpu, "bmips4350");
602977b0 1456 }
0de663ef 1457 break;
602977b0
KC		 1458 }
1459 case PRID_IMP_BMIPS5000:
68e6a783 1460 case PRID_IMP_BMIPS5200:
602977b0
KC		 1461 c->cputype = CPU_BMIPS5000;
1462 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 1463 set_elf_platform(cpu, "bmips5000");
602977b0 1464 c->options |= MIPS_CPU_ULRI;
0de663ef 1465 break;
1c0c13eb
AJ		 1466 }
1467}
1468
0dd4781b
DD		 1469static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1470{
1471 decode_configs(c);
8ff374b9 1472 switch (c->processor_id & PRID_IMP_MASK) {
0dd4781b
DD		 1473 case PRID_IMP_CAVIUM_CN38XX:
1474 case PRID_IMP_CAVIUM_CN31XX:
1475 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 1476 c->cputype = CPU_CAVIUM_OCTEON;
1477 __cpu_name[cpu] = "Cavium Octeon";
1478 goto platform;
0dd4781b
DD		 1479 case PRID_IMP_CAVIUM_CN58XX:
1480 case PRID_IMP_CAVIUM_CN56XX:
1481 case PRID_IMP_CAVIUM_CN50XX:
1482 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 1483 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1484 __cpu_name[cpu] = "Cavium Octeon+";
1485platform:
c094c99e 1486 set_elf_platform(cpu, "octeon");
0dd4781b 1487 break;
a1431b61 1488 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 1489 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 1490 case PRID_IMP_CAVIUM_CN66XX:
1491 case PRID_IMP_CAVIUM_CN68XX:
af04bb85 1492 case PRID_IMP_CAVIUM_CNF71XX:
0e56b385
DD		 1493 c->cputype = CPU_CAVIUM_OCTEON2;
1494 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 1495 set_elf_platform(cpu, "octeon2");
0e56b385 1496 break;
af04bb85 1497 case PRID_IMP_CAVIUM_CN70XX:
b8c8f665
DD		 1498 case PRID_IMP_CAVIUM_CN73XX:
1499 case PRID_IMP_CAVIUM_CNF75XX:
af04bb85
DD		 1500 case PRID_IMP_CAVIUM_CN78XX:
1501 c->cputype = CPU_CAVIUM_OCTEON3;
1502 __cpu_name[cpu] = "Cavium Octeon III";
1503 set_elf_platform(cpu, "octeon3");
1504 break;
0dd4781b
DD		 1505 default:
1506 printk(KERN_INFO "Unknown Octeon chip!\n");
1507 c->cputype = CPU_UNKNOWN;
1508 break;
1509 }
1510}
1511
83ccf69d
LPC		 1512static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1513{
1514 decode_configs(c);
1515 /* JZRISC does not implement the CP0 counter. */
1516 c->options &= ~MIPS_CPU_COUNTER;
06947aaa 1517 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
8ff374b9 1518 switch (c->processor_id & PRID_IMP_MASK) {
83ccf69d
LPC		 1519 case PRID_IMP_JZRISC:
1520 c->cputype = CPU_JZRISC;
4f12b91d 1521 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
83ccf69d
LPC		 1522 __cpu_name[cpu] = "Ingenic JZRISC";
1523 break;
1524 default:
1525 panic("Unknown Ingenic Processor ID!");
1526 break;
1527 }
1528}
1529
a7117c6b
J		 1530static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1531{
1532 decode_configs(c);
1533
8ff374b9 1534 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
809f36c6
ML		 1535 c->cputype = CPU_ALCHEMY;
1536 __cpu_name[cpu] = "Au1300";
1537 /* following stuff is not for Alchemy */
1538 return;
1539 }
1540
70342287
RB		 1541 c->options = (MIPS_CPU_TLB |
1542 MIPS_CPU_4KEX |
a7117c6b 1543 MIPS_CPU_COUNTER |
70342287
RB		 1544 MIPS_CPU_DIVEC |
1545 MIPS_CPU_WATCH |
1546 MIPS_CPU_EJTAG |
a7117c6b
J		 1547 MIPS_CPU_LLSC);
1548
8ff374b9 1549 switch (c->processor_id & PRID_IMP_MASK) {
4ca86a2f 1550 case PRID_IMP_NETLOGIC_XLP2XX:
8907c55e 1551 case PRID_IMP_NETLOGIC_XLP9XX:
1c983986 1552 case PRID_IMP_NETLOGIC_XLP5XX:
4ca86a2f
J		 1553 c->cputype = CPU_XLP;
1554 __cpu_name[cpu] = "Broadcom XLPII";
1555 break;
1556
2aa54b20
J		 1557 case PRID_IMP_NETLOGIC_XLP8XX:
1558 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 1559 c->cputype = CPU_XLP;
1560 __cpu_name[cpu] = "Netlogic XLP";
1561 break;
1562
a7117c6b
J		 1563 case PRID_IMP_NETLOGIC_XLR732:
1564 case PRID_IMP_NETLOGIC_XLR716:
1565 case PRID_IMP_NETLOGIC_XLR532:
1566 case PRID_IMP_NETLOGIC_XLR308:
1567 case PRID_IMP_NETLOGIC_XLR532C:
1568 case PRID_IMP_NETLOGIC_XLR516C:
1569 case PRID_IMP_NETLOGIC_XLR508C:
1570 case PRID_IMP_NETLOGIC_XLR308C:
1571 c->cputype = CPU_XLR;
1572 __cpu_name[cpu] = "Netlogic XLR";
1573 break;
1574
1575 case PRID_IMP_NETLOGIC_XLS608:
1576 case PRID_IMP_NETLOGIC_XLS408:
1577 case PRID_IMP_NETLOGIC_XLS404:
1578 case PRID_IMP_NETLOGIC_XLS208:
1579 case PRID_IMP_NETLOGIC_XLS204:
1580 case PRID_IMP_NETLOGIC_XLS108:
1581 case PRID_IMP_NETLOGIC_XLS104:
1582 case PRID_IMP_NETLOGIC_XLS616B:
1583 case PRID_IMP_NETLOGIC_XLS608B:
1584 case PRID_IMP_NETLOGIC_XLS416B:
1585 case PRID_IMP_NETLOGIC_XLS412B:
1586 case PRID_IMP_NETLOGIC_XLS408B:
1587 case PRID_IMP_NETLOGIC_XLS404B:
1588 c->cputype = CPU_XLR;
1589 __cpu_name[cpu] = "Netlogic XLS";
1590 break;
1591
1592 default:
a3d4fb2d 1593 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 1594 c->processor_id);
1595 c->cputype = CPU_XLR;
1596 break;
1597 }
1598
a3d4fb2d 1599 if (c->cputype == CPU_XLP) {
a96102be 1600 set_isa(c, MIPS_CPU_ISA_M64R2);
a3d4fb2d
J		 1601 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1602 /* This will be updated again after all threads are woken up */
1603 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1604 } else {
a96102be 1605 set_isa(c, MIPS_CPU_ISA_M64R1);
a3d4fb2d
J		 1606 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1607 }
7777b939 1608 c->kscratch_mask = 0xf;
a7117c6b
J		 1609}
1610
949e51be
DD		 1611#ifdef CONFIG_64BIT
1612/* For use by uaccess.h */
1613u64 __ua_limit;
1614EXPORT_SYMBOL(__ua_limit);
1615#endif
1616
9966db25 1617const char *__cpu_name[NR_CPUS];
874fd3b5 1618const char *__elf_platform;
9966db25 1619
078a55fc 1620void cpu_probe(void)
1da177e4
LT		 1621{
1622 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 1623 unsigned int cpu = smp_processor_id();
1da177e4 1624
70342287 1625 c->processor_id = PRID_IMP_UNKNOWN;
1da177e4
LT		 1626 c->fpu_id = FPIR_IMP_NONE;
1627 c->cputype = CPU_UNKNOWN;
4f12b91d 1628 c->writecombine = _CACHE_UNCACHED;
1da177e4 1629
9b26616c
MR		 1630 c->fpu_csr31 = FPU_CSR_RN;
1631 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1632
1da177e4 1633 c->processor_id = read_c0_prid();
8ff374b9 1634 switch (c->processor_id & PRID_COMP_MASK) {
1da177e4 1635 case PRID_COMP_LEGACY:
cea7e2df 1636 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1637 break;
1638 case PRID_COMP_MIPS:
cea7e2df 1639 cpu_probe_mips(c, cpu);
1da177e4
LT		 1640 break;
1641 case PRID_COMP_ALCHEMY:
cea7e2df 1642 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1643 break;
1644 case PRID_COMP_SIBYTE:
cea7e2df 1645 cpu_probe_sibyte(c, cpu);
1da177e4 1646 break;
1c0c13eb 1647 case PRID_COMP_BROADCOM:
cea7e2df 1648 cpu_probe_broadcom(c, cpu);
1c0c13eb 1649 break;
1da177e4 1650 case PRID_COMP_SANDCRAFT:
cea7e2df 1651 cpu_probe_sandcraft(c, cpu);
1da177e4 1652 break;
a92b0588 1653 case PRID_COMP_NXP:
cea7e2df 1654 cpu_probe_nxp(c, cpu);
a3dddd56 1655 break;
0dd4781b
DD		 1656 case PRID_COMP_CAVIUM:
1657 cpu_probe_cavium(c, cpu);
1658 break;
252617a4
PB		 1659 case PRID_COMP_INGENIC_D0:
1660 case PRID_COMP_INGENIC_D1:
1661 case PRID_COMP_INGENIC_E1:
83ccf69d
LPC		 1662 cpu_probe_ingenic(c, cpu);
1663 break;
a7117c6b
J		 1664 case PRID_COMP_NETLOGIC:
1665 cpu_probe_netlogic(c, cpu);
1666 break;
1da177e4 1667 }
dec8b1ca 1668
cea7e2df
RB		 1669 BUG_ON(!__cpu_name[cpu]);
1670 BUG_ON(c->cputype == CPU_UNKNOWN);
1671
dec8b1ca
FBH		 1672 /*
1673 * Platform code can force the cpu type to optimize code
1674 * generation. In that case be sure the cpu type is correctly
1675 * manually setup otherwise it could trigger some nasty bugs.
1676 */
1677 BUG_ON(current_cpu_type() != c->cputype);
1678
0103d23f
KC		 1679 if (mips_fpu_disabled)
1680 c->options &= ~MIPS_CPU_FPU;
1681
1682 if (mips_dsp_disabled)
ee80f7c7 1683 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f 1684
3d528b32
MC		 1685 if (mips_htw_disabled) {
1686 c->options &= ~MIPS_CPU_HTW;
1687 write_c0_pwctl(read_c0_pwctl() &
1688 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1689 }
1690
7aecd5ca
MR		 1691 if (c->options & MIPS_CPU_FPU)
1692 cpu_set_fpu_opts(c);
1693 else
1694 cpu_set_nofpu_opts(c);
9966db25 1695
8d5ded16
JK		 1696 if (cpu_has_bp_ghist)
1697 write_c0_r10k_diag(read_c0_r10k_diag() |
1698 R10K_DIAG_E_GHIST);
1699
8b8aa636 1700 if (cpu_has_mips_r2_r6) {
f6771dbb 1701 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
da4b62cd
AC		 1702 /* R2 has Performance Counter Interrupt indicator */
1703 c->options |= MIPS_CPU_PCI;
1704 }
f6771dbb
RB		 1705 else
1706 c->srsets = 1;
91dfc423 1707
4c063034
PB		 1708 if (cpu_has_mips_r6)
1709 elf_hwcap |= HWCAP_MIPS_R6;
1710
a8ad1367 1711 if (cpu_has_msa) {
a5e9a69e 1712 c->msa_id = cpu_get_msa_id();
a8ad1367
PB		 1713 WARN(c->msa_id & MSA_IR_WRPF,
1714 "Vector register partitioning unimplemented!");
3cc9fa7f 1715 elf_hwcap |= HWCAP_MIPS_MSA;
a8ad1367 1716 }
a5e9a69e 1717
91dfc423 1718 cpu_probe_vmbits(c);
949e51be
DD		 1719
1720#ifdef CONFIG_64BIT
1721 if (cpu == 0)
1722 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1723#endif
1da177e4
LT		 1724}
1725
078a55fc 1726void cpu_report(void)
1da177e4
LT		 1727{
1728 struct cpuinfo_mips *c = &current_cpu_data;
1729
d9f897c9
LY		 1730 pr_info("CPU%d revision is: %08x (%s)\n",
1731 smp_processor_id(), c->processor_id, cpu_name_string());
1da177e4 1732 if (c->options & MIPS_CPU_FPU)
9966db25 1733 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
a5e9a69e
PB		 1734 if (cpu_has_msa)
1735 pr_info("MSA revision is: %08x\n", c->msa_id);
1da177e4 1736}
Linux 6.x block layer and io_uring tree(s)