[linux-2.6-block.git] / arch / mips / kernel / cpu-probe.c

/*
 * Processor capabilities determination functions.
 *
 * Copyright (C) xxxx  the Anonymous
 * Copyright (C) 2003, 2004  Maciej W. Rozycki
 * Copyright (C) 1994 - 2003 Ralf Baechle
 * Copyright (C) 2001, 2004  MIPS Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ptrace.h>
#include <linux/stddef.h>

#include <asm/cpu.h>
#include <asm/fpu.h>
#include <asm/mipsregs.h>
#include <asm/system.h>

/*
 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
 * the implementation of the "wait" feature differs between CPU families. This
 * points to the function that implements CPU specific wait.
 * The wait instruction stops the pipeline and reduces the power consumption of
 * the CPU very much.
 */
void (*cpu_wait)(void) = NULL;

static void r3081_wait(void)
{
	unsigned long cfg = read_c0_conf();
	write_c0_conf(cfg | R30XX_CONF_HALT);
}

static void r39xx_wait(void)
{
	unsigned long cfg = read_c0_conf();
	write_c0_conf(cfg | TX39_CONF_HALT);
}

static void r4k_wait(void)
{
	__asm__(".set\tmips3\n\t"
		"wait\n\t"
		".set\tmips0");
}

/* The Au1xxx wait is available only if using 32khz counter or
 * external timer source, but specifically not CP0 Counter. */
int allow_au1k_wait;

static void au1k_wait(void)
{
	/* using the wait instruction makes CP0 counter unusable */
	__asm__(".set mips3\n\t"
		"cache 0x14, 0(%0)\n\t"
		"cache 0x14, 32(%0)\n\t"
		"sync\n\t"
		"nop\n\t"
		"wait\n\t"
		"nop\n\t"
		"nop\n\t"
		"nop\n\t"
		"nop\n\t"
		".set mips0\n\t"
		: : "r" (au1k_wait));
}

static int __initdata nowait = 0;

int __init wait_disable(char *s)
{
	nowait = 1;

	return 1;
}

__setup("nowait", wait_disable);

static inline void check_wait(void)
{
	struct cpuinfo_mips *c = &current_cpu_data;

	printk("Checking for 'wait' instruction... ");
	if (nowait) {
		printk (" disabled.\n");
		return;
	}

	switch (c->cputype) {
	case CPU_R3081:
	case CPU_R3081E:
		cpu_wait = r3081_wait;
		printk(" available.\n");
		break;
	case CPU_TX3927:
		cpu_wait = r39xx_wait;
		printk(" available.\n");
		break;
	case CPU_R4200:
/*	case CPU_R4300: */
	case CPU_R4600:
	case CPU_R4640:
	case CPU_R4650:
	case CPU_R4700:
	case CPU_R5000:
	case CPU_NEVADA:
	case CPU_RM7000:
	case CPU_RM9000:
	case CPU_TX49XX:
	case CPU_4KC:
	case CPU_4KEC:
	case CPU_4KSC:
	case CPU_5KC:
/*	case CPU_20KC:*/
	case CPU_24K:
	case CPU_25KF:
	case CPU_34K:
 	case CPU_PR4450:
		cpu_wait = r4k_wait;
		printk(" available.\n");
		break;
	case CPU_AU1000:
	case CPU_AU1100:
	case CPU_AU1500:
	case CPU_AU1550:
	case CPU_AU1200:
		if (allow_au1k_wait) {
			cpu_wait = au1k_wait;
			printk(" available.\n");
		} else
			printk(" unavailable.\n");
		break;
	default:
		printk(" unavailable.\n");
		break;
	}
}

void __init check_bugs32(void)
{
	check_wait();
}

/*
 * Probe whether cpu has config register by trying to play with
 * alternate cache bit and see whether it matters.
 * It's used by cpu_probe to distinguish between R3000A and R3081.
 */
static inline int cpu_has_confreg(void)
{
#ifdef CONFIG_CPU_R3000
	extern unsigned long r3k_cache_size(unsigned long);
	unsigned long size1, size2;
	unsigned long cfg = read_c0_conf();

	size1 = r3k_cache_size(ST0_ISC);
	write_c0_conf(cfg ^ R30XX_CONF_AC);
	size2 = r3k_cache_size(ST0_ISC);
	write_c0_conf(cfg);
	return size1 != size2;
#else
	return 0;
#endif
}

/*
 * Get the FPU Implementation/Revision.
 */
static inline unsigned long cpu_get_fpu_id(void)
{
	unsigned long tmp, fpu_id;

	tmp = read_c0_status();
	__enable_fpu();
	fpu_id = read_32bit_cp1_register(CP1_REVISION);
	write_c0_status(tmp);
	return fpu_id;
}

/*
 * Check the CPU has an FPU the official way.
 */
static inline int __cpu_has_fpu(void)
{
	return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
}

#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
		| MIPS_CPU_COUNTER)

static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
{
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_R2000:
		c->cputype = CPU_R2000;
		c->isa_level = MIPS_CPU_ISA_I;
		c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
		             MIPS_CPU_NOFPUEX;
		if (__cpu_has_fpu())
			c->options |= MIPS_CPU_FPU;
		c->tlbsize = 64;
		break;
	case PRID_IMP_R3000:
		if ((c->processor_id & 0xff) == PRID_REV_R3000A)
			if (cpu_has_confreg())
				c->cputype = CPU_R3081E;
			else
				c->cputype = CPU_R3000A;
		else
			c->cputype = CPU_R3000;
		c->isa_level = MIPS_CPU_ISA_I;
		c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
		             MIPS_CPU_NOFPUEX;
		if (__cpu_has_fpu())
			c->options |= MIPS_CPU_FPU;
		c->tlbsize = 64;
		break;
	case PRID_IMP_R4000:
		if (read_c0_config() & CONF_SC) {
			if ((c->processor_id & 0xff) >= PRID_REV_R4400)
				c->cputype = CPU_R4400PC;
			else
				c->cputype = CPU_R4000PC;
		} else {
			if ((c->processor_id & 0xff) >= PRID_REV_R4400)
				c->cputype = CPU_R4400SC;
			else
				c->cputype = CPU_R4000SC;
		}

		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_WATCH | MIPS_CPU_VCE |
		             MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_VR41XX:
		switch (c->processor_id & 0xf0) {
		case PRID_REV_VR4111:
			c->cputype = CPU_VR4111;
			break;
		case PRID_REV_VR4121:
			c->cputype = CPU_VR4121;
			break;
		case PRID_REV_VR4122:
			if ((c->processor_id & 0xf) < 0x3)
				c->cputype = CPU_VR4122;
			else
				c->cputype = CPU_VR4181A;
			break;
		case PRID_REV_VR4130:
			if ((c->processor_id & 0xf) < 0x4)
				c->cputype = CPU_VR4131;
			else
				c->cputype = CPU_VR4133;
			break;
		default:
			printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
			c->cputype = CPU_VR41XX;
			break;
		}
		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS;
		c->tlbsize = 32;
		break;
	case PRID_IMP_R4300:
		c->cputype = CPU_R4300;
		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		c->tlbsize = 32;
		break;
	case PRID_IMP_R4600:
		c->cputype = CPU_R4600;
		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
			     MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	#if 0
 	case PRID_IMP_R4650:
		/*
		 * This processor doesn't have an MMU, so it's not
		 * "real easy" to run Linux on it. It is left purely
		 * for documentation.  Commented out because it shares
		 * it's c0_prid id number with the TX3900.
		 */
 		c->cputype = CPU_R4650;
	 	c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
	        c->tlbsize = 48;
		break;
	#endif
	case PRID_IMP_TX39:
		c->isa_level = MIPS_CPU_ISA_I;
		c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;

		if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
			c->cputype = CPU_TX3927;
			c->tlbsize = 64;
		} else {
			switch (c->processor_id & 0xff) {
			case PRID_REV_TX3912:
				c->cputype = CPU_TX3912;
				c->tlbsize = 32;
				break;
			case PRID_REV_TX3922:
				c->cputype = CPU_TX3922;
				c->tlbsize = 64;
				break;
			default:
				c->cputype = CPU_UNKNOWN;
				break;
			}
		}
		break;
	case PRID_IMP_R4700:
		c->cputype = CPU_R4700;
		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_TX49:
		c->cputype = CPU_TX49XX;
		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_LLSC;
		if (!(c->processor_id & 0x08))
			c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
		c->tlbsize = 48;
		break;
	case PRID_IMP_R5000:
		c->cputype = CPU_R5000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_R5432:
		c->cputype = CPU_R5432;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_WATCH | MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_R5500:
		c->cputype = CPU_R5500;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_WATCH | MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_NEVADA:
		c->cputype = CPU_NEVADA;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_R6000:
		c->cputype = CPU_R6000;
		c->isa_level = MIPS_CPU_ISA_II;
		c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
		             MIPS_CPU_LLSC;
		c->tlbsize = 32;
		break;
	case PRID_IMP_R6000A:
		c->cputype = CPU_R6000A;
		c->isa_level = MIPS_CPU_ISA_II;
		c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
		             MIPS_CPU_LLSC;
		c->tlbsize = 32;
		break;
	case PRID_IMP_RM7000:
		c->cputype = CPU_RM7000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		/*
		 * Undocumented RM7000:  Bit 29 in the info register of
		 * the RM7000 v2.0 indicates if the TLB has 48 or 64
		 * entries.
		 *
		 * 29      1 =>    64 entry JTLB
		 *         0 =>    48 entry JTLB
		 */
		c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
		break;
	case PRID_IMP_RM9000:
		c->cputype = CPU_RM9000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		/*
		 * Bit 29 in the info register of the RM9000
		 * indicates if the TLB has 48 or 64 entries.
		 *
		 * 29      1 =>    64 entry JTLB
		 *         0 =>    48 entry JTLB
		 */
		c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
		break;
	case PRID_IMP_R8000:
		c->cputype = CPU_R8000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
		             MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
		break;
	case PRID_IMP_R10000:
		c->cputype = CPU_R10000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
		             MIPS_CPU_FPU | MIPS_CPU_32FPR |
			     MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
		             MIPS_CPU_LLSC;
		c->tlbsize = 64;
		break;
	case PRID_IMP_R12000:
		c->cputype = CPU_R12000;
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
		             MIPS_CPU_FPU | MIPS_CPU_32FPR |
			     MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
		             MIPS_CPU_LLSC;
		c->tlbsize = 64;
		break;
	}
}

static inline unsigned int decode_config0(struct cpuinfo_mips *c)
{
	unsigned int config0;
	int isa;

	config0 = read_c0_config();

	if (((config0 & MIPS_CONF_MT) >> 7) == 1)
		c->options |= MIPS_CPU_TLB;
	isa = (config0 & MIPS_CONF_AT) >> 13;
	switch (isa) {
	case 0:
		c->isa_level = MIPS_CPU_ISA_M32R1;
		break;
	case 2:
		c->isa_level = MIPS_CPU_ISA_M64R1;
		break;
	default:
		panic("Unsupported ISA type, cp0.config0.at: %d.", isa);
	}

	return config0 & MIPS_CONF_M;
}

static inline unsigned int decode_config1(struct cpuinfo_mips *c)
{
	unsigned int config1;

	config1 = read_c0_config1();

	if (config1 & MIPS_CONF1_MD)
		c->ases |= MIPS_ASE_MDMX;
	if (config1 & MIPS_CONF1_WR)
		c->options |= MIPS_CPU_WATCH;
	if (config1 & MIPS_CONF1_CA)
		c->ases |= MIPS_ASE_MIPS16;
	if (config1 & MIPS_CONF1_EP)
		c->options |= MIPS_CPU_EJTAG;
	if (config1 & MIPS_CONF1_FP) {
		c->options |= MIPS_CPU_FPU;
		c->options |= MIPS_CPU_32FPR;
	}
	if (cpu_has_tlb)
		c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;

	return config1 & MIPS_CONF_M;
}

static inline unsigned int decode_config2(struct cpuinfo_mips *c)
{
	unsigned int config2;

	config2 = read_c0_config2();

	if (config2 & MIPS_CONF2_SL)
		c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;

	return config2 & MIPS_CONF_M;
}

static inline unsigned int decode_config3(struct cpuinfo_mips *c)
{
	unsigned int config3;

	config3 = read_c0_config3();

	if (config3 & MIPS_CONF3_SM)
		c->ases |= MIPS_ASE_SMARTMIPS;
	if (config3 & MIPS_CONF3_DSP)
		c->ases |= MIPS_ASE_DSP;
	if (config3 & MIPS_CONF3_VINT)
		c->options |= MIPS_CPU_VINT;
	if (config3 & MIPS_CONF3_VEIC)
		c->options |= MIPS_CPU_VEIC;
	if (config3 & MIPS_CONF3_MT)
                c->ases |= MIPS_ASE_MIPSMT;

	return config3 & MIPS_CONF_M;
}

static inline void decode_configs(struct cpuinfo_mips *c)
{
	/* MIPS32 or MIPS64 compliant CPU.  */
	c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
	             MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;

	c->scache.flags = MIPS_CACHE_NOT_PRESENT;

	/* Read Config registers.  */
	if (!decode_config0(c))
		return;			/* actually worth a panic() */
	if (!decode_config1(c))
		return;
	if (!decode_config2(c))
		return;
	if (!decode_config3(c))
		return;
}

static inline void cpu_probe_mips(struct cpuinfo_mips *c)
{
	decode_configs(c);
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_4KC:
		c->cputype = CPU_4KC;
		break;
	case PRID_IMP_4KEC:
		c->cputype = CPU_4KEC;
		break;
	case PRID_IMP_4KECR2:
		c->cputype = CPU_4KEC;
		break;
	case PRID_IMP_4KSC:
	case PRID_IMP_4KSD:
		c->cputype = CPU_4KSC;
		break;
	case PRID_IMP_5KC:
		c->cputype = CPU_5KC;
		break;
	case PRID_IMP_20KC:
		c->cputype = CPU_20KC;
		break;
	case PRID_IMP_24K:
	case PRID_IMP_24KE:
		c->cputype = CPU_24K;
		break;
	case PRID_IMP_25KF:
		c->cputype = CPU_25KF;
		/* Probe for L2 cache */
		c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
		break;
	case PRID_IMP_34K:
		c->cputype = CPU_34K;
		c->isa_level = MIPS_CPU_ISA_M32R1;
		break;
	}
}

static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
{
	decode_configs(c);
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_AU1_REV1:
	case PRID_IMP_AU1_REV2:
		switch ((c->processor_id >> 24) & 0xff) {
		case 0:
 			c->cputype = CPU_AU1000;
			break;
		case 1:
			c->cputype = CPU_AU1500;
			break;
		case 2:
			c->cputype = CPU_AU1100;
			break;
		case 3:
			c->cputype = CPU_AU1550;
			break;
		case 4:
			c->cputype = CPU_AU1200;
			break;
		default:
			panic("Unknown Au Core!");
			break;
		}
		break;
	}
}

static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
{
	decode_configs(c);

	/*
	 * For historical reasons the SB1 comes with it's own variant of
	 * cache code which eventually will be folded into c-r4k.c.  Until
	 * then we pretend it's got it's own cache architecture.
	 */
	c->options &= ~MIPS_CPU_4K_CACHE;
	c->options |= MIPS_CPU_SB1_CACHE;

	switch (c->processor_id & 0xff00) {
	case PRID_IMP_SB1:
		c->cputype = CPU_SB1;
#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
		/* FPU in pass1 is known to have issues. */
		c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
#endif
		break;
	case PRID_IMP_SB1A:
		c->cputype = CPU_SB1A;
		break;
	}
}

static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
{
	decode_configs(c);
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_SR71000:
		c->cputype = CPU_SR71000;
		c->scache.ways = 8;
		c->tlbsize = 64;
		break;
	}
}

static inline void cpu_probe_philips(struct cpuinfo_mips *c)
{
	decode_configs(c);
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_PR4450:
		c->cputype = CPU_PR4450;
		c->isa_level = MIPS_CPU_ISA_M32R1;
		break;
	default:
		panic("Unknown Philips Core!"); /* REVISIT: die? */
		break;
	}
}


__init void cpu_probe(void)
{
	struct cpuinfo_mips *c = &current_cpu_data;

	c->processor_id	= PRID_IMP_UNKNOWN;
	c->fpu_id	= FPIR_IMP_NONE;
	c->cputype	= CPU_UNKNOWN;

	c->processor_id = read_c0_prid();
	switch (c->processor_id & 0xff0000) {
	case PRID_COMP_LEGACY:
		cpu_probe_legacy(c);
		break;
	case PRID_COMP_MIPS:
		cpu_probe_mips(c);
		break;
	case PRID_COMP_ALCHEMY:
		cpu_probe_alchemy(c);
		break;
	case PRID_COMP_SIBYTE:
		cpu_probe_sibyte(c);
		break;
	case PRID_COMP_SANDCRAFT:
		cpu_probe_sandcraft(c);
		break;
 	case PRID_COMP_PHILIPS:
		cpu_probe_philips(c);
 		break;
	default:
		c->cputype = CPU_UNKNOWN;
	}
	if (c->options & MIPS_CPU_FPU) {
		c->fpu_id = cpu_get_fpu_id();

		if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
		    c->isa_level == MIPS_CPU_ISA_M64R1) {
			if (c->fpu_id & MIPS_FPIR_3D)
				c->ases |= MIPS_ASE_MIPS3D;
		}
	}
}

__init void cpu_report(void)
{
	struct cpuinfo_mips *c = &current_cpu_data;

	printk("CPU revision is: %08x\n", c->processor_id);
	if (c->options & MIPS_CPU_FPU)
		printk("FPU revision is: %08x\n", c->fpu_id);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Processor capabilities determination functions.
	3	*
	4	* Copyright (C) xxxx the Anonymous
4194318c	5	* Copyright (C) 2003, 2004 Maciej W. Rozycki
1da177e4	6	* Copyright (C) 1994 - 2003 Ralf Baechle
4194318c	7	* Copyright (C) 2001, 2004 MIPS Inc.
1da177e4 LT	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version
	12	* 2 of the License, or (at your option) any later version.
	13	*/
	14	#include <linux/config.h>
	15	#include <linux/init.h>
	16	#include <linux/kernel.h>
	17	#include <linux/ptrace.h>
	18	#include <linux/stddef.h>
	19
1da177e4 LT	20	#include <asm/cpu.h>
	21	#include <asm/fpu.h>
	22	#include <asm/mipsregs.h>
	23	#include <asm/system.h>
	24
	25	/*
	26	* Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
	27	* the implementation of the "wait" feature differs between CPU families. This
	28	* points to the function that implements CPU specific wait.
	29	* The wait instruction stops the pipeline and reduces the power consumption of
	30	* the CPU very much.
	31	*/
	32	void (*cpu_wait)(void) = NULL;
	33
	34	static void r3081_wait(void)
	35	{
	36	unsigned long cfg = read_c0_conf();
	37	write_c0_conf(cfg \| R30XX_CONF_HALT);
	38	}
	39
	40	static void r39xx_wait(void)
	41	{
	42	unsigned long cfg = read_c0_conf();
	43	write_c0_conf(cfg \| TX39_CONF_HALT);
	44	}
	45
	46	static void r4k_wait(void)
	47	{
	48	__asm__(".set\tmips3\n\t"
	49	"wait\n\t"
	50	".set\tmips0");
	51	}
	52
494900af PP	53	/* The Au1xxx wait is available only if using 32khz counter or
494900af PP	54	* external timer source, but specifically not CP0 Counter. */
fe359bf5	55	int allow_au1k_wait;
10f650db	56
494900af	57	static void au1k_wait(void)
1da177e4	58	{
1da177e4	59	/* using the wait instruction makes CP0 counter unusable */
10f650db RB	60	__asm__(".set mips3\n\t"
	61	"cache 0x14, 0(%0)\n\t"
	62	"cache 0x14, 32(%0)\n\t"
494900af PP	63	"sync\n\t"
494900af PP	64	"nop\n\t"
1da177e4 LT	65	"wait\n\t"
	66	"nop\n\t"
	67	"nop\n\t"
	68	"nop\n\t"
	69	"nop\n\t"
494900af	70	".set mips0\n\t"
10f650db	71	: : "r" (au1k_wait));
1da177e4 LT	72	}
1da177e4 LT	73
55d04dff RB	74	static int __initdata nowait = 0;
	75
	76	int __init wait_disable(char *s)
	77	{
	78	nowait = 1;
	79
	80	return 1;
	81	}
	82
	83	__setup("nowait", wait_disable);
	84
1da177e4 LT	85	static inline void check_wait(void)
	86	{
	87	struct cpuinfo_mips *c = &current_cpu_data;
	88
	89	printk("Checking for 'wait' instruction... ");
55d04dff RB	90	if (nowait) {
	91	printk (" disabled.\n");
	92	return;
	93	}
	94
1da177e4 LT	95	switch (c->cputype) {
	96	case CPU_R3081:
	97	case CPU_R3081E:
	98	cpu_wait = r3081_wait;
	99	printk(" available.\n");
	100	break;
	101	case CPU_TX3927:
	102	cpu_wait = r39xx_wait;
	103	printk(" available.\n");
	104	break;
	105	case CPU_R4200:
	106	/* case CPU_R4300: */
	107	case CPU_R4600:
	108	case CPU_R4640:
	109	case CPU_R4650:
	110	case CPU_R4700:
	111	case CPU_R5000:
	112	case CPU_NEVADA:
	113	case CPU_RM7000:
	114	case CPU_RM9000:
	115	case CPU_TX49XX:
	116	case CPU_4KC:
	117	case CPU_4KEC:
	118	case CPU_4KSC:
	119	case CPU_5KC:
	120	/* case CPU_20KC:*/
	121	case CPU_24K:
	122	case CPU_25KF:
bbc7f22f	123	case CPU_34K:
bdf21b18	124	case CPU_PR4450:
1da177e4 LT	125	cpu_wait = r4k_wait;
	126	printk(" available.\n");
	127	break;
1da177e4 LT	128	case CPU_AU1000:
	129	case CPU_AU1100:
	130	case CPU_AU1500:
e3ad1c23 PP	131	case CPU_AU1550:
e3ad1c23 PP	132	case CPU_AU1200:
fe359bf5 PP	133	if (allow_au1k_wait) {
	134	cpu_wait = au1k_wait;
	135	printk(" available.\n");
	136	} else
	137	printk(" unavailable.\n");
1da177e4	138	break;
1da177e4 LT	139	default:
	140	printk(" unavailable.\n");
	141	break;
	142	}
	143	}
	144
	145	void __init check_bugs32(void)
	146	{
	147	check_wait();
	148	}
	149
	150	/*
	151	* Probe whether cpu has config register by trying to play with
	152	* alternate cache bit and see whether it matters.
	153	* It's used by cpu_probe to distinguish between R3000A and R3081.
	154	*/
	155	static inline int cpu_has_confreg(void)
	156	{
	157	#ifdef CONFIG_CPU_R3000
	158	extern unsigned long r3k_cache_size(unsigned long);
	159	unsigned long size1, size2;
	160	unsigned long cfg = read_c0_conf();
	161
	162	size1 = r3k_cache_size(ST0_ISC);
	163	write_c0_conf(cfg ^ R30XX_CONF_AC);
	164	size2 = r3k_cache_size(ST0_ISC);
	165	write_c0_conf(cfg);
	166	return size1 != size2;
	167	#else
	168	return 0;
	169	#endif
	170	}
	171
	172	/*
	173	* Get the FPU Implementation/Revision.
	174	*/
	175	static inline unsigned long cpu_get_fpu_id(void)
	176	{
	177	unsigned long tmp, fpu_id;
	178
	179	tmp = read_c0_status();
	180	__enable_fpu();
	181	fpu_id = read_32bit_cp1_register(CP1_REVISION);
	182	write_c0_status(tmp);
	183	return fpu_id;
	184	}
	185
	186	/*
	187	* Check the CPU has an FPU the official way.
	188	*/
	189	static inline int __cpu_has_fpu(void)
	190	{
	191	return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
	192	}
	193
02cf2119	194	#define R4K_OPTS (MIPS_CPU_TLB \| MIPS_CPU_4KEX \| MIPS_CPU_4K_CACHE \
1da177e4 LT	195	\| MIPS_CPU_COUNTER)
	196
	197	static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
	198	{
	199	switch (c->processor_id & 0xff00) {
	200	case PRID_IMP_R2000:
	201	c->cputype = CPU_R2000;
	202	c->isa_level = MIPS_CPU_ISA_I;
02cf2119 RB	203	c->options = MIPS_CPU_TLB \| MIPS_CPU_3K_CACHE \|
02cf2119 RB	204	MIPS_CPU_NOFPUEX;
1da177e4 LT	205	if (__cpu_has_fpu())
	206	c->options \|= MIPS_CPU_FPU;
	207	c->tlbsize = 64;
	208	break;
	209	case PRID_IMP_R3000:
	210	if ((c->processor_id & 0xff) == PRID_REV_R3000A)
	211	if (cpu_has_confreg())
	212	c->cputype = CPU_R3081E;
	213	else
	214	c->cputype = CPU_R3000A;
	215	else
	216	c->cputype = CPU_R3000;
	217	c->isa_level = MIPS_CPU_ISA_I;
02cf2119 RB	218	c->options = MIPS_CPU_TLB \| MIPS_CPU_3K_CACHE \|
02cf2119 RB	219	MIPS_CPU_NOFPUEX;
1da177e4 LT	220	if (__cpu_has_fpu())
	221	c->options \|= MIPS_CPU_FPU;
	222	c->tlbsize = 64;
	223	break;
	224	case PRID_IMP_R4000:
	225	if (read_c0_config() & CONF_SC) {
	226	if ((c->processor_id & 0xff) >= PRID_REV_R4400)
	227	c->cputype = CPU_R4400PC;
	228	else
	229	c->cputype = CPU_R4000PC;
	230	} else {
	231	if ((c->processor_id & 0xff) >= PRID_REV_R4400)
	232	c->cputype = CPU_R4400SC;
	233	else
	234	c->cputype = CPU_R4000SC;
	235	}
	236
	237	c->isa_level = MIPS_CPU_ISA_III;
	238	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
	239	MIPS_CPU_WATCH \| MIPS_CPU_VCE \|
	240	MIPS_CPU_LLSC;
	241	c->tlbsize = 48;
	242	break;
	243	case PRID_IMP_VR41XX:
	244	switch (c->processor_id & 0xf0) {
1da177e4 LT	245	case PRID_REV_VR4111:
	246	c->cputype = CPU_VR4111;
	247	break;
1da177e4 LT	248	case PRID_REV_VR4121:
	249	c->cputype = CPU_VR4121;
	250	break;
	251	case PRID_REV_VR4122:
	252	if ((c->processor_id & 0xf) < 0x3)
	253	c->cputype = CPU_VR4122;
	254	else
	255	c->cputype = CPU_VR4181A;
	256	break;
	257	case PRID_REV_VR4130:
	258	if ((c->processor_id & 0xf) < 0x4)
	259	c->cputype = CPU_VR4131;
	260	else
	261	c->cputype = CPU_VR4133;
	262	break;
	263	default:
	264	printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
	265	c->cputype = CPU_VR41XX;
	266	break;
	267	}
	268	c->isa_level = MIPS_CPU_ISA_III;
	269	c->options = R4K_OPTS;
	270	c->tlbsize = 32;
	271	break;
	272	case PRID_IMP_R4300:
	273	c->cputype = CPU_R4300;
	274	c->isa_level = MIPS_CPU_ISA_III;
	275	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
	276	MIPS_CPU_LLSC;
	277	c->tlbsize = 32;
	278	break;
	279	case PRID_IMP_R4600:
	280	c->cputype = CPU_R4600;
	281	c->isa_level = MIPS_CPU_ISA_III;
075e7502 TS	282	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
075e7502 TS	283	MIPS_CPU_LLSC;
1da177e4 LT	284	c->tlbsize = 48;
	285	break;
	286	#if 0
	287	case PRID_IMP_R4650:
	288	/*
	289	* This processor doesn't have an MMU, so it's not
	290	* "real easy" to run Linux on it. It is left purely
	291	* for documentation. Commented out because it shares
	292	* it's c0_prid id number with the TX3900.
	293	*/
	294	c->cputype = CPU_R4650;
	295	c->isa_level = MIPS_CPU_ISA_III;
	296	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_LLSC;
	297	c->tlbsize = 48;
	298	break;
	299	#endif
	300	case PRID_IMP_TX39:
	301	c->isa_level = MIPS_CPU_ISA_I;
02cf2119	302	c->options = MIPS_CPU_TLB \| MIPS_CPU_TX39_CACHE;
1da177e4 LT	303
	304	if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
	305	c->cputype = CPU_TX3927;
	306	c->tlbsize = 64;
	307	} else {
	308	switch (c->processor_id & 0xff) {
	309	case PRID_REV_TX3912:
	310	c->cputype = CPU_TX3912;
	311	c->tlbsize = 32;
	312	break;
	313	case PRID_REV_TX3922:
	314	c->cputype = CPU_TX3922;
	315	c->tlbsize = 64;
	316	break;
	317	default:
	318	c->cputype = CPU_UNKNOWN;
	319	break;
	320	}
	321	}
	322	break;
	323	case PRID_IMP_R4700:
	324	c->cputype = CPU_R4700;
	325	c->isa_level = MIPS_CPU_ISA_III;
	326	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
	327	MIPS_CPU_LLSC;
	328	c->tlbsize = 48;
	329	break;
	330	case PRID_IMP_TX49:
	331	c->cputype = CPU_TX49XX;
	332	c->isa_level = MIPS_CPU_ISA_III;
	333	c->options = R4K_OPTS \| MIPS_CPU_LLSC;
	334	if (!(c->processor_id & 0x08))
	335	c->options \|= MIPS_CPU_FPU \| MIPS_CPU_32FPR;
	336	c->tlbsize = 48;
	337	break;
	338	case PRID_IMP_R5000:
	339	c->cputype = CPU_R5000;
	340	c->isa_level = MIPS_CPU_ISA_IV;
	341	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
	342	MIPS_CPU_LLSC;
	343	c->tlbsize = 48;
	344	break;
	345	case PRID_IMP_R5432:
	346	c->cputype = CPU_R5432;
	347	c->isa_level = MIPS_CPU_ISA_IV;
	348	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
	349	MIPS_CPU_WATCH \| MIPS_CPU_LLSC;
	350	c->tlbsize = 48;
	351	break;
	352	case PRID_IMP_R5500:
	353	c->cputype = CPU_R5500;
	354	c->isa_level = MIPS_CPU_ISA_IV;
	355	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
	356	MIPS_CPU_WATCH \| MIPS_CPU_LLSC;
	357	c->tlbsize = 48;
	358	break;
	359	case PRID_IMP_NEVADA:
	360	c->cputype = CPU_NEVADA;
	361	c->isa_level = MIPS_CPU_ISA_IV;
	362	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
	363	MIPS_CPU_DIVEC \| MIPS_CPU_LLSC;
	364	c->tlbsize = 48;
	365	break;
	366	case PRID_IMP_R6000:
367	c->cputype = CPU_R6000;
368	c->isa_level = MIPS_CPU_ISA_II;
369	c->options = MIPS_CPU_TLB \| MIPS_CPU_FPU \|
370	MIPS_CPU_LLSC;
371	c->tlbsize = 32;
372	break;
373	case PRID_IMP_R6000A:
374	c->cputype = CPU_R6000A;
375	c->isa_level = MIPS_CPU_ISA_II;
376	c->options = MIPS_CPU_TLB \| MIPS_CPU_FPU \|
377	MIPS_CPU_LLSC;
378	c->tlbsize = 32;
379	break;
380	case PRID_IMP_RM7000:
381	c->cputype = CPU_RM7000;
382	c->isa_level = MIPS_CPU_ISA_IV;
383	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
384	MIPS_CPU_LLSC;
385	/*
386	* Undocumented RM7000: Bit 29 in the info register of
387	* the RM7000 v2.0 indicates if the TLB has 48 or 64
388	* entries.
389	*
390	* 29 1 => 64 entry JTLB
391	* 0 => 48 entry JTLB
392	*/
393	c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
394	break;
395	case PRID_IMP_RM9000:
396	c->cputype = CPU_RM9000;
397	c->isa_level = MIPS_CPU_ISA_IV;
398	c->options = R4K_OPTS \| MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
399	MIPS_CPU_LLSC;
400	/*
401	* Bit 29 in the info register of the RM9000
402	* indicates if the TLB has 48 or 64 entries.
403	*
404	* 29 1 => 64 entry JTLB
405	* 0 => 48 entry JTLB
406	*/
407	c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
408	break;
409	case PRID_IMP_R8000:
410	c->cputype = CPU_R8000;
411	c->isa_level = MIPS_CPU_ISA_IV;
412	c->options = MIPS_CPU_TLB \| MIPS_CPU_4KEX \|
413	MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
414	MIPS_CPU_LLSC;
415	c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
416	break;
417	case PRID_IMP_R10000:
418	c->cputype = CPU_R10000;
419	c->isa_level = MIPS_CPU_ISA_IV;
8b36612a	420	c->options = MIPS_CPU_TLB \| MIPS_CPU_4K_CACHE \| MIPS_CPU_4KEX \|
1da177e4 LT	421	MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
	422	MIPS_CPU_COUNTER \| MIPS_CPU_WATCH \|
	423	MIPS_CPU_LLSC;
	424	c->tlbsize = 64;
	425	break;
	426	case PRID_IMP_R12000:
	427	c->cputype = CPU_R12000;
	428	c->isa_level = MIPS_CPU_ISA_IV;
8b36612a	429	c->options = MIPS_CPU_TLB \| MIPS_CPU_4K_CACHE \| MIPS_CPU_4KEX \|
1da177e4 LT	430	MIPS_CPU_FPU \| MIPS_CPU_32FPR \|
	431	MIPS_CPU_COUNTER \| MIPS_CPU_WATCH \|
	432	MIPS_CPU_LLSC;
	433	c->tlbsize = 64;
	434	break;
	435	}
	436	}
	437
4194318c	438	static inline unsigned int decode_config0(struct cpuinfo_mips *c)
1da177e4	439	{
4194318c RB	440	unsigned int config0;
4194318c RB	441	int isa;
1da177e4	442
4194318c RB	443	config0 = read_c0_config();
	444
	445	if (((config0 & MIPS_CONF_MT) >> 7) == 1)
02cf2119	446	c->options \|= MIPS_CPU_TLB;
4194318c RB	447	isa = (config0 & MIPS_CONF_AT) >> 13;
	448	switch (isa) {
	449	case 0:
e7958bb9	450	c->isa_level = MIPS_CPU_ISA_M32R1;
4194318c RB	451	break;
4194318c RB	452	case 2:
e7958bb9	453	c->isa_level = MIPS_CPU_ISA_M64R1;
4194318c RB	454	break;
	455	default:
	456	panic("Unsupported ISA type, cp0.config0.at: %d.", isa);
	457	}
	458
	459	return config0 & MIPS_CONF_M;
	460	}
	461
	462	static inline unsigned int decode_config1(struct cpuinfo_mips *c)
	463	{
	464	unsigned int config1;
1da177e4	465
1da177e4	466	config1 = read_c0_config1();
4194318c RB	467
	468	if (config1 & MIPS_CONF1_MD)
	469	c->ases \|= MIPS_ASE_MDMX;
	470	if (config1 & MIPS_CONF1_WR)
1da177e4	471	c->options \|= MIPS_CPU_WATCH;
4194318c RB	472	if (config1 & MIPS_CONF1_CA)
	473	c->ases \|= MIPS_ASE_MIPS16;
	474	if (config1 & MIPS_CONF1_EP)
1da177e4	475	c->options \|= MIPS_CPU_EJTAG;
4194318c	476	if (config1 & MIPS_CONF1_FP) {
1da177e4 LT	477	c->options \|= MIPS_CPU_FPU;
	478	c->options \|= MIPS_CPU_32FPR;
	479	}
4194318c RB	480	if (cpu_has_tlb)
	481	c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
	482
	483	return config1 & MIPS_CONF_M;
	484	}
	485
	486	static inline unsigned int decode_config2(struct cpuinfo_mips *c)
	487	{
	488	unsigned int config2;
	489
	490	config2 = read_c0_config2();
	491
	492	if (config2 & MIPS_CONF2_SL)
	493	c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
	494
	495	return config2 & MIPS_CONF_M;
	496	}
	497
	498	static inline unsigned int decode_config3(struct cpuinfo_mips *c)
	499	{
	500	unsigned int config3;
	501
	502	config3 = read_c0_config3();
	503
	504	if (config3 & MIPS_CONF3_SM)
	505	c->ases \|= MIPS_ASE_SMARTMIPS;
e50c0a8f RB	506	if (config3 & MIPS_CONF3_DSP)
e50c0a8f RB	507	c->ases \|= MIPS_ASE_DSP;
8f40611d RB	508	if (config3 & MIPS_CONF3_VINT)
	509	c->options \|= MIPS_CPU_VINT;
	510	if (config3 & MIPS_CONF3_VEIC)
	511	c->options \|= MIPS_CPU_VEIC;
	512	if (config3 & MIPS_CONF3_MT)
	513	c->ases \|= MIPS_ASE_MIPSMT;
4194318c RB	514
	515	return config3 & MIPS_CONF_M;
	516	}
	517
	518	static inline void decode_configs(struct cpuinfo_mips *c)
	519	{
	520	/* MIPS32 or MIPS64 compliant CPU. */
02cf2119 RB	521	c->options = MIPS_CPU_4KEX \| MIPS_CPU_4K_CACHE \| MIPS_CPU_COUNTER \|
02cf2119 RB	522	MIPS_CPU_DIVEC \| MIPS_CPU_LLSC \| MIPS_CPU_MCHECK;
4194318c	523
1da177e4 LT	524	c->scache.flags = MIPS_CACHE_NOT_PRESENT;
1da177e4 LT	525
4194318c RB	526	/* Read Config registers. */
	527	if (!decode_config0(c))
	528	return; /* actually worth a panic() */
	529	if (!decode_config1(c))
	530	return;
	531	if (!decode_config2(c))
	532	return;
	533	if (!decode_config3(c))
	534	return;
1da177e4 LT	535	}
	536
	537	static inline void cpu_probe_mips(struct cpuinfo_mips *c)
	538	{
4194318c	539	decode_configs(c);
1da177e4 LT	540	switch (c->processor_id & 0xff00) {
	541	case PRID_IMP_4KC:
	542	c->cputype = CPU_4KC;
1da177e4 LT	543	break;
	544	case PRID_IMP_4KEC:
	545	c->cputype = CPU_4KEC;
1da177e4	546	break;
2b07bd02 RB	547	case PRID_IMP_4KECR2:
2b07bd02 RB	548	c->cputype = CPU_4KEC;
2b07bd02	549	break;
1da177e4	550	case PRID_IMP_4KSC:
8afcb5d8	551	case PRID_IMP_4KSD:
1da177e4	552	c->cputype = CPU_4KSC;
1da177e4 LT	553	break;
	554	case PRID_IMP_5KC:
	555	c->cputype = CPU_5KC;
1da177e4 LT	556	break;
	557	case PRID_IMP_20KC:
	558	c->cputype = CPU_20KC;
1da177e4 LT	559	break;
1da177e4 LT	560	case PRID_IMP_24K:
e50c0a8f	561	case PRID_IMP_24KE:
1da177e4	562	c->cputype = CPU_24K;
1da177e4 LT	563	break;
	564	case PRID_IMP_25KF:
	565	c->cputype = CPU_25KF;
1da177e4 LT	566	/* Probe for L2 cache */
	567	c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
	568	break;
bbc7f22f RB	569	case PRID_IMP_34K:
bbc7f22f RB	570	c->cputype = CPU_34K;
e7958bb9	571	c->isa_level = MIPS_CPU_ISA_M32R1;
bbc7f22f	572	break;
1da177e4 LT	573	}
	574	}
	575
	576	static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
	577	{
4194318c	578	decode_configs(c);
1da177e4 LT	579	switch (c->processor_id & 0xff00) {
	580	case PRID_IMP_AU1_REV1:
	581	case PRID_IMP_AU1_REV2:
	582	switch ((c->processor_id >> 24) & 0xff) {
	583	case 0:
	584	c->cputype = CPU_AU1000;
	585	break;
	586	case 1:
	587	c->cputype = CPU_AU1500;
	588	break;
	589	case 2:
	590	c->cputype = CPU_AU1100;
	591	break;
	592	case 3:
	593	c->cputype = CPU_AU1550;
	594	break;
e3ad1c23 PP	595	case 4:
	596	c->cputype = CPU_AU1200;
	597	break;
1da177e4 LT	598	default:
	599	panic("Unknown Au Core!");
	600	break;
	601	}
1da177e4 LT	602	break;
	603	}
	604	}
	605
	606	static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
	607	{
4194318c	608	decode_configs(c);
02cf2119 RB	609
	610	/*
	611	* For historical reasons the SB1 comes with it's own variant of
	612	* cache code which eventually will be folded into c-r4k.c. Until
	613	* then we pretend it's got it's own cache architecture.
	614	*/
d121ced2	615	c->options &= ~MIPS_CPU_4K_CACHE;
02cf2119 RB	616	c->options \|= MIPS_CPU_SB1_CACHE;
02cf2119 RB	617
1da177e4 LT	618	switch (c->processor_id & 0xff00) {
	619	case PRID_IMP_SB1:
	620	c->cputype = CPU_SB1;
4194318c	621	#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
1da177e4	622	/* FPU in pass1 is known to have issues. */
4194318c	623	c->options &= ~(MIPS_CPU_FPU \| MIPS_CPU_32FPR);
1da177e4 LT	624	#endif
1da177e4 LT	625	break;
93ce2f52 AI	626	case PRID_IMP_SB1A:
	627	c->cputype = CPU_SB1A;
	628	break;
1da177e4 LT	629	}
	630	}
	631
	632	static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
	633	{
4194318c	634	decode_configs(c);
1da177e4 LT	635	switch (c->processor_id & 0xff00) {
	636	case PRID_IMP_SR71000:
	637	c->cputype = CPU_SR71000;
1da177e4 LT	638	c->scache.ways = 8;
	639	c->tlbsize = 64;
	640	break;
	641	}
	642	}
	643
bdf21b18 PP	644	static inline void cpu_probe_philips(struct cpuinfo_mips *c)
	645	{
	646	decode_configs(c);
	647	switch (c->processor_id & 0xff00) {
	648	case PRID_IMP_PR4450:
	649	c->cputype = CPU_PR4450;
e7958bb9	650	c->isa_level = MIPS_CPU_ISA_M32R1;
bdf21b18 PP	651	break;
	652	default:
	653	panic("Unknown Philips Core!"); /* REVISIT: die? */
	654	break;
	655	}
	656	}
	657
	658
1da177e4 LT	659	__init void cpu_probe(void)
	660	{
	661	struct cpuinfo_mips *c = &current_cpu_data;
	662
	663	c->processor_id = PRID_IMP_UNKNOWN;
	664	c->fpu_id = FPIR_IMP_NONE;
	665	c->cputype = CPU_UNKNOWN;
	666
	667	c->processor_id = read_c0_prid();
	668	switch (c->processor_id & 0xff0000) {
	669	case PRID_COMP_LEGACY:
	670	cpu_probe_legacy(c);
	671	break;
	672	case PRID_COMP_MIPS:
	673	cpu_probe_mips(c);
	674	break;
	675	case PRID_COMP_ALCHEMY:
	676	cpu_probe_alchemy(c);
	677	break;
	678	case PRID_COMP_SIBYTE:
	679	cpu_probe_sibyte(c);
	680	break;
1da177e4 LT	681	case PRID_COMP_SANDCRAFT:
	682	cpu_probe_sandcraft(c);
	683	break;
bdf21b18 PP	684	case PRID_COMP_PHILIPS:
	685	cpu_probe_philips(c);
	686	break;
1da177e4 LT	687	default:
	688	c->cputype = CPU_UNKNOWN;
	689	}
4194318c	690	if (c->options & MIPS_CPU_FPU) {
1da177e4	691	c->fpu_id = cpu_get_fpu_id();
4194318c	692
e7958bb9 RB	693	if (c->isa_level == MIPS_CPU_ISA_M32R1 \|\|
e7958bb9 RB	694	c->isa_level == MIPS_CPU_ISA_M64R1) {
4194318c RB	695	if (c->fpu_id & MIPS_FPIR_3D)
	696	c->ases \|= MIPS_ASE_MIPS3D;
	697	}
	698	}
1da177e4 LT	699	}
	700
	701	__init void cpu_report(void)
	702	{
	703	struct cpuinfo_mips *c = &current_cpu_data;
	704
	705	printk("CPU revision is: %08x\n", c->processor_id);
	706	if (c->options & MIPS_CPU_FPU)
	707	printk("FPU revision is: %08x\n", c->fpu_id);
	708	}