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MIPS: SEAD-3: Fix GIC interrupt specifiers
[linux-2.6-block.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
70342287 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4 22#include <asm/cpu.h>
f6843626 23#include <asm/cpu-features.h>
69f24d17 24#include <asm/cpu-type.h>
1da177e4
LT		 25#include <asm/fpu.h>
26#include <asm/mipsregs.h>
30ee615b 27#include <asm/mipsmtregs.h>
a5e9a69e 28#include <asm/msa.h>
654f57bf 29#include <asm/watch.h>
06372a63 30#include <asm/elf.h>
4f12b91d 31#include <asm/pgtable-bits.h>
a074f0e8 32#include <asm/spram.h>
7c0f6ba6 33#include <linux/uaccess.h>
949e51be 34
e14f1db7
PB		 35/* Hardware capabilities */
36unsigned int elf_hwcap __read_mostly;
05510f2b 37EXPORT_SYMBOL_GPL(elf_hwcap);
e14f1db7 38
7aecd5ca
MR		 39/*
40 * Get the FPU Implementation/Revision.
41 */
42static inline unsigned long cpu_get_fpu_id(void)
43{
44 unsigned long tmp, fpu_id;
45
46 tmp = read_c0_status();
47 __enable_fpu(FPU_AS_IS);
48 fpu_id = read_32bit_cp1_register(CP1_REVISION);
49 write_c0_status(tmp);
50 return fpu_id;
51}
52
53/*
54 * Check if the CPU has an external FPU.
55 */
56static inline int __cpu_has_fpu(void)
57{
58 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
59}
60
61static inline unsigned long cpu_get_msa_id(void)
62{
63 unsigned long status, msa_id;
64
65 status = read_c0_status();
66 __enable_fpu(FPU_64BIT);
67 enable_msa();
68 msa_id = read_msa_ir();
69 disable_msa();
70 write_c0_status(status);
71 return msa_id;
72}
73
9b26616c
MR		 74/*
75 * Determine the FCSR mask for FPU hardware.
76 */
77static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
78{
79 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
80
90b712dd 81 fcsr = c->fpu_csr31;
9b26616c
MR		 82 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
83
84 sr = read_c0_status();
85 __enable_fpu(FPU_AS_IS);
86
9b26616c
MR		 87 fcsr0 = fcsr & mask;
88 write_32bit_cp1_register(CP1_STATUS, fcsr0);
89 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
90
91 fcsr1 = fcsr | ~mask;
92 write_32bit_cp1_register(CP1_STATUS, fcsr1);
93 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
94
95 write_32bit_cp1_register(CP1_STATUS, fcsr);
96
97 write_c0_status(sr);
98
99 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
100}
101
93adeaf6
MR		 102/*
103 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
104 * supported by FPU hardware.
105 */
106static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
107{
108 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
109 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
110 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
111 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
112
113 sr = read_c0_status();
114 __enable_fpu(FPU_AS_IS);
115
116 fir = read_32bit_cp1_register(CP1_REVISION);
117 if (fir & MIPS_FPIR_HAS2008) {
118 fcsr = read_32bit_cp1_register(CP1_STATUS);
119
120 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
121 write_32bit_cp1_register(CP1_STATUS, fcsr0);
122 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
123
124 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
125 write_32bit_cp1_register(CP1_STATUS, fcsr1);
126 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
127
128 write_32bit_cp1_register(CP1_STATUS, fcsr);
129
130 if (!(fcsr0 & FPU_CSR_NAN2008))
131 c->options |= MIPS_CPU_NAN_LEGACY;
132 if (fcsr1 & FPU_CSR_NAN2008)
133 c->options |= MIPS_CPU_NAN_2008;
134
135 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
136 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
137 else
138 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
139
140 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
141 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
142 else
143 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
144 } else {
145 c->options |= MIPS_CPU_NAN_LEGACY;
146 }
147
148 write_c0_status(sr);
149 } else {
150 c->options |= MIPS_CPU_NAN_LEGACY;
151 }
152}
153
154/*
503943e0
MR		 155 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
156 * ABS.fmt/NEG.fmt execution mode.
157 */
158static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
159
160/*
161 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
162 * to support by the FPU emulator according to the IEEE 754 conformance
163 * mode selected. Note that "relaxed" straps the emulator so that it
164 * allows 2008-NaN binaries even for legacy processors.
93adeaf6
MR		 165 */
166static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
167{
503943e0 168 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
93adeaf6 169 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
503943e0
MR		 170 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
171
172 switch (ieee754) {
173 case STRICT:
174 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
175 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
176 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
177 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
178 } else {
179 c->options |= MIPS_CPU_NAN_LEGACY;
180 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
181 }
182 break;
183 case LEGACY:
93adeaf6
MR		 184 c->options |= MIPS_CPU_NAN_LEGACY;
185 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
503943e0
MR		 186 break;
187 case STD2008:
188 c->options |= MIPS_CPU_NAN_2008;
189 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
190 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
191 break;
192 case RELAXED:
193 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
194 break;
93adeaf6
MR		 195 }
196}
197
503943e0
MR		 198/*
199 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
200 * according to the "ieee754=" parameter.
201 */
202static void cpu_set_nan_2008(struct cpuinfo_mips *c)
203{
204 switch (ieee754) {
205 case STRICT:
206 mips_use_nan_legacy = !!cpu_has_nan_legacy;
207 mips_use_nan_2008 = !!cpu_has_nan_2008;
208 break;
209 case LEGACY:
210 mips_use_nan_legacy = !!cpu_has_nan_legacy;
211 mips_use_nan_2008 = !cpu_has_nan_legacy;
212 break;
213 case STD2008:
214 mips_use_nan_legacy = !cpu_has_nan_2008;
215 mips_use_nan_2008 = !!cpu_has_nan_2008;
216 break;
217 case RELAXED:
218 mips_use_nan_legacy = true;
219 mips_use_nan_2008 = true;
220 break;
221 }
222}
223
224/*
225 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
226 * settings:
227 *
228 * strict: accept binaries that request a NaN encoding supported by the FPU
229 * legacy: only accept legacy-NaN binaries
230 * 2008: only accept 2008-NaN binaries
231 * relaxed: accept any binaries regardless of whether supported by the FPU
232 */
233static int __init ieee754_setup(char *s)
234{
235 if (!s)
236 return -1;
237 else if (!strcmp(s, "strict"))
238 ieee754 = STRICT;
239 else if (!strcmp(s, "legacy"))
240 ieee754 = LEGACY;
241 else if (!strcmp(s, "2008"))
242 ieee754 = STD2008;
243 else if (!strcmp(s, "relaxed"))
244 ieee754 = RELAXED;
245 else
246 return -1;
247
248 if (!(boot_cpu_data.options & MIPS_CPU_FPU))
249 cpu_set_nofpu_2008(&boot_cpu_data);
250 cpu_set_nan_2008(&boot_cpu_data);
251
252 return 0;
253}
254
255early_param("ieee754", ieee754_setup);
256
f6843626
MR		 257/*
258 * Set the FIR feature flags for the FPU emulator.
259 */
260static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
261{
262 u32 value;
263
264 value = 0;
265 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
266 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
267 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
268 value |= MIPS_FPIR_D | MIPS_FPIR_S;
269 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
270 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
271 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
90d53a91
MR		 272 if (c->options & MIPS_CPU_NAN_2008)
273 value |= MIPS_FPIR_HAS2008;
f6843626
MR		 274 c->fpu_id = value;
275}
276
9b26616c
MR		 277/* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
278static unsigned int mips_nofpu_msk31;
279
7aecd5ca
MR		 280/*
281 * Set options for FPU hardware.
282 */
283static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
284{
285 c->fpu_id = cpu_get_fpu_id();
286 mips_nofpu_msk31 = c->fpu_msk31;
287
288 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
289 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
290 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
291 if (c->fpu_id & MIPS_FPIR_3D)
292 c->ases |= MIPS_ASE_MIPS3D;
4e87580e
JH		 293 if (c->fpu_id & MIPS_FPIR_UFRP)
294 c->options |= MIPS_CPU_UFR;
7aecd5ca
MR		 295 if (c->fpu_id & MIPS_FPIR_FREP)
296 c->options |= MIPS_CPU_FRE;
297 }
298
299 cpu_set_fpu_fcsr_mask(c);
93adeaf6 300 cpu_set_fpu_2008(c);
503943e0 301 cpu_set_nan_2008(c);
7aecd5ca
MR		 302}
303
304/*
305 * Set options for the FPU emulator.
306 */
307static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
308{
309 c->options &= ~MIPS_CPU_FPU;
310 c->fpu_msk31 = mips_nofpu_msk31;
311
93adeaf6 312 cpu_set_nofpu_2008(c);
503943e0 313 cpu_set_nan_2008(c);
7aecd5ca
MR		 314 cpu_set_nofpu_id(c);
315}
316
078a55fc 317static int mips_fpu_disabled;
0103d23f
KC		 318
319static int __init fpu_disable(char *s)
320{
7aecd5ca 321 cpu_set_nofpu_opts(&boot_cpu_data);
0103d23f
KC		 322 mips_fpu_disabled = 1;
323
324 return 1;
325}
326
327__setup("nofpu", fpu_disable);
328
078a55fc 329int mips_dsp_disabled;
0103d23f
KC		 330
331static int __init dsp_disable(char *s)
332{
ee80f7c7 333 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f
KC		 334 mips_dsp_disabled = 1;
335
336 return 1;
337}
338
339__setup("nodsp", dsp_disable);
340
3d528b32
MC		 341static int mips_htw_disabled;
342
343static int __init htw_disable(char *s)
344{
345 mips_htw_disabled = 1;
346 cpu_data[0].options &= ~MIPS_CPU_HTW;
347 write_c0_pwctl(read_c0_pwctl() &
348 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
349
350 return 1;
351}
352
353__setup("nohtw", htw_disable);
354
97f4ad29
MC		 355static int mips_ftlb_disabled;
356static int mips_has_ftlb_configured;
357
ebd0e0f5
PB		 358enum ftlb_flags {
359 FTLB_EN = 1 << 0,
360 FTLB_SET_PROB = 1 << 1,
361};
362
363static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
97f4ad29
MC		 364
365static int __init ftlb_disable(char *s)
366{
367 unsigned int config4, mmuextdef;
368
369 /*
370 * If the core hasn't done any FTLB configuration, there is nothing
371 * for us to do here.
372 */
373 if (!mips_has_ftlb_configured)
374 return 1;
375
376 /* Disable it in the boot cpu */
912708c2
MC		 377 if (set_ftlb_enable(&cpu_data[0], 0)) {
378 pr_warn("Can't turn FTLB off\n");
379 return 1;
380 }
97f4ad29 381
97f4ad29
MC		 382 config4 = read_c0_config4();
383
384 /* Check that FTLB has been disabled */
385 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
386 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
387 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
388 /* This should never happen */
389 pr_warn("FTLB could not be disabled!\n");
390 return 1;
391 }
392
393 mips_ftlb_disabled = 1;
394 mips_has_ftlb_configured = 0;
395
396 /*
397 * noftlb is mainly used for debug purposes so print
398 * an informative message instead of using pr_debug()
399 */
400 pr_info("FTLB has been disabled\n");
401
402 /*
403 * Some of these bits are duplicated in the decode_config4.
404 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
405 * once FTLB has been disabled so undo what decode_config4 did.
406 */
407 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
408 cpu_data[0].tlbsizeftlbsets;
409 cpu_data[0].tlbsizeftlbsets = 0;
410 cpu_data[0].tlbsizeftlbways = 0;
411
412 return 1;
413}
414
415__setup("noftlb", ftlb_disable);
416
417
9267a30d
MSJ		 418static inline void check_errata(void)
419{
420 struct cpuinfo_mips *c = &current_cpu_data;
421
69f24d17 422 switch (current_cpu_type()) {
9267a30d
MSJ		 423 case CPU_34K:
424 /*
425 * Erratum "RPS May Cause Incorrect Instruction Execution"
b633648c 426 * This code only handles VPE0, any SMP/RTOS code
9267a30d
MSJ		 427 * making use of VPE1 will be responsable for that VPE.
428 */
429 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
430 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
431 break;
432 default:
433 break;
434 }
435}
436
1da177e4
LT		 437void __init check_bugs32(void)
438{
9267a30d 439 check_errata();
1da177e4
LT		 440}
441
442/*
443 * Probe whether cpu has config register by trying to play with
444 * alternate cache bit and see whether it matters.
445 * It's used by cpu_probe to distinguish between R3000A and R3081.
446 */
447static inline int cpu_has_confreg(void)
448{
449#ifdef CONFIG_CPU_R3000
450 extern unsigned long r3k_cache_size(unsigned long);
451 unsigned long size1, size2;
452 unsigned long cfg = read_c0_conf();
453
454 size1 = r3k_cache_size(ST0_ISC);
455 write_c0_conf(cfg ^ R30XX_CONF_AC);
456 size2 = r3k_cache_size(ST0_ISC);
457 write_c0_conf(cfg);
458 return size1 != size2;
459#else
460 return 0;
461#endif
462}
463
c094c99e
RM		 464static inline void set_elf_platform(int cpu, const char *plat)
465{
466 if (cpu == 0)
467 __elf_platform = plat;
468}
469
91dfc423
GR		 470static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
471{
472#ifdef __NEED_VMBITS_PROBE
5b7efa89 473 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 474 back_to_back_c0_hazard();
5b7efa89 475 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 476#endif
477}
478
078a55fc 479static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
a96102be
SH		 480{
481 switch (isa) {
482 case MIPS_CPU_ISA_M64R2:
483 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
484 case MIPS_CPU_ISA_M64R1:
485 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
486 case MIPS_CPU_ISA_V:
487 c->isa_level |= MIPS_CPU_ISA_V;
488 case MIPS_CPU_ISA_IV:
489 c->isa_level |= MIPS_CPU_ISA_IV;
490 case MIPS_CPU_ISA_III:
1990e542 491 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
a96102be
SH		 492 break;
493
8b8aa636
LY		 494 /* R6 incompatible with everything else */
495 case MIPS_CPU_ISA_M64R6:
496 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
497 case MIPS_CPU_ISA_M32R6:
498 c->isa_level |= MIPS_CPU_ISA_M32R6;
499 /* Break here so we don't add incompatible ISAs */
500 break;
a96102be
SH		 501 case MIPS_CPU_ISA_M32R2:
502 c->isa_level |= MIPS_CPU_ISA_M32R2;
503 case MIPS_CPU_ISA_M32R1:
504 c->isa_level |= MIPS_CPU_ISA_M32R1;
505 case MIPS_CPU_ISA_II:
506 c->isa_level |= MIPS_CPU_ISA_II;
a96102be
SH		 507 break;
508 }
509}
510
078a55fc 511static char unknown_isa[] = KERN_ERR \
2fa36399
KC		 512 "Unsupported ISA type, c0.config0: %d.";
513
cf0a8aa0
MC		 514static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
515{
516
517 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
518
519 /*
520 * 0 = All TLBWR instructions go to FTLB
521 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
522 * FTLB and 1 goes to the VTLB.
523 * 2 = 7:1: As above with 7:1 ratio.
524 * 3 = 3:1: As above with 3:1 ratio.
525 *
526 * Use the linear midpoint as the probability threshold.
527 */
528 if (probability >= 12)
529 return 1;
530 else if (probability >= 6)
531 return 2;
532 else
533 /*
534 * So FTLB is less than 4 times bigger than VTLB.
535 * A 3:1 ratio can still be useful though.
536 */
537 return 3;
538}
539
ebd0e0f5 540static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
75b5b5e0 541{
20a7f7e5 542 unsigned int config;
d83b0e82
JH		 543
544 /* It's implementation dependent how the FTLB can be enabled */
545 switch (c->cputype) {
546 case CPU_PROAPTIV:
547 case CPU_P5600:
1091bfa2 548 case CPU_P6600:
d83b0e82 549 /* proAptiv & related cores use Config6 to enable the FTLB */
20a7f7e5 550 config = read_c0_config6();
ebd0e0f5
PB		 551
552 if (flags & FTLB_EN)
553 config |= MIPS_CONF6_FTLBEN;
75b5b5e0 554 else
ebd0e0f5
PB		 555 config &= ~MIPS_CONF6_FTLBEN;
556
557 if (flags & FTLB_SET_PROB) {
558 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
559 config |= calculate_ftlb_probability(c)
560 << MIPS_CONF6_FTLBP_SHIFT;
561 }
562
563 write_c0_config6(config);
67acd8d5 564 back_to_back_c0_hazard();
20a7f7e5
MC		 565 break;
566 case CPU_I6400:
859aeb1b 567 case CPU_I6500:
72c70f01 568 /* There's no way to disable the FTLB */
ebd0e0f5
PB		 569 if (!(flags & FTLB_EN))
570 return 1;
571 return 0;
b2edcfc8 572 case CPU_LOONGSON3:
06e4814e
HC		 573 /* Flush ITLB, DTLB, VTLB and FTLB */
574 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
575 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
b2edcfc8
HC		 576 /* Loongson-3 cores use Config6 to enable the FTLB */
577 config = read_c0_config6();
ebd0e0f5 578 if (flags & FTLB_EN)
b2edcfc8
HC		 579 /* Enable FTLB */
580 write_c0_config6(config & ~MIPS_CONF6_FTLBDIS);
581 else
582 /* Disable FTLB */
583 write_c0_config6(config | MIPS_CONF6_FTLBDIS);
584 break;
912708c2
MC		 585 default:
586 return 1;
75b5b5e0 587 }
912708c2
MC		 588
589 return 0;
75b5b5e0
LY		 590}
591
2fa36399
KC		 592static inline unsigned int decode_config0(struct cpuinfo_mips *c)
593{
594 unsigned int config0;
2f6f3136 595 int isa, mt;
2fa36399
KC		 596
597 config0 = read_c0_config();
598
75b5b5e0
LY		 599 /*
600 * Look for Standard TLB or Dual VTLB and FTLB
601 */
2f6f3136
JH		 602 mt = config0 & MIPS_CONF_MT;
603 if (mt == MIPS_CONF_MT_TLB)
2fa36399 604 c->options |= MIPS_CPU_TLB;
2f6f3136
JH		 605 else if (mt == MIPS_CONF_MT_FTLB)
606 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
75b5b5e0 607
2fa36399
KC		 608 isa = (config0 & MIPS_CONF_AT) >> 13;
609 switch (isa) {
610 case 0:
611 switch ((config0 & MIPS_CONF_AR) >> 10) {
612 case 0:
a96102be 613 set_isa(c, MIPS_CPU_ISA_M32R1);
2fa36399
KC		 614 break;
615 case 1:
a96102be 616 set_isa(c, MIPS_CPU_ISA_M32R2);
2fa36399 617 break;
8b8aa636
LY		 618 case 2:
619 set_isa(c, MIPS_CPU_ISA_M32R6);
620 break;
2fa36399
KC		 621 default:
622 goto unknown;
623 }
624 break;
625 case 2:
626 switch ((config0 & MIPS_CONF_AR) >> 10) {
627 case 0:
a96102be 628 set_isa(c, MIPS_CPU_ISA_M64R1);
2fa36399
KC		 629 break;
630 case 1:
a96102be 631 set_isa(c, MIPS_CPU_ISA_M64R2);
2fa36399 632 break;
8b8aa636
LY		 633 case 2:
634 set_isa(c, MIPS_CPU_ISA_M64R6);
635 break;
2fa36399
KC		 636 default:
637 goto unknown;
638 }
639 break;
640 default:
641 goto unknown;
642 }
643
644 return config0 & MIPS_CONF_M;
645
646unknown:
647 panic(unknown_isa, config0);
648}
649
650static inline unsigned int decode_config1(struct cpuinfo_mips *c)
651{
652 unsigned int config1;
653
654 config1 = read_c0_config1();
655
656 if (config1 & MIPS_CONF1_MD)
657 c->ases |= MIPS_ASE_MDMX;
30228c40
JH		 658 if (config1 & MIPS_CONF1_PC)
659 c->options |= MIPS_CPU_PERF;
2fa36399
KC		 660 if (config1 & MIPS_CONF1_WR)
661 c->options |= MIPS_CPU_WATCH;
662 if (config1 & MIPS_CONF1_CA)
663 c->ases |= MIPS_ASE_MIPS16;
664 if (config1 & MIPS_CONF1_EP)
665 c->options |= MIPS_CPU_EJTAG;
666 if (config1 & MIPS_CONF1_FP) {
667 c->options |= MIPS_CPU_FPU;
668 c->options |= MIPS_CPU_32FPR;
669 }
75b5b5e0 670 if (cpu_has_tlb) {
2fa36399 671 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
75b5b5e0
LY		 672 c->tlbsizevtlb = c->tlbsize;
673 c->tlbsizeftlbsets = 0;
674 }
2fa36399
KC		 675
676 return config1 & MIPS_CONF_M;
677}
678
679static inline unsigned int decode_config2(struct cpuinfo_mips *c)
680{
681 unsigned int config2;
682
683 config2 = read_c0_config2();
684
685 if (config2 & MIPS_CONF2_SL)
686 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
687
688 return config2 & MIPS_CONF_M;
689}
690
691static inline unsigned int decode_config3(struct cpuinfo_mips *c)
692{
693 unsigned int config3;
694
695 config3 = read_c0_config3();
696
b2ab4f08 697 if (config3 & MIPS_CONF3_SM) {
2fa36399 698 c->ases |= MIPS_ASE_SMARTMIPS;
f18bdfa1 699 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
b2ab4f08
SH		 700 }
701 if (config3 & MIPS_CONF3_RXI)
702 c->options |= MIPS_CPU_RIXI;
f18bdfa1
JH		 703 if (config3 & MIPS_CONF3_CTXTC)
704 c->options |= MIPS_CPU_CTXTC;
2fa36399
KC		 705 if (config3 & MIPS_CONF3_DSP)
706 c->ases |= MIPS_ASE_DSP;
b5a6455c 707 if (config3 & MIPS_CONF3_DSP2P) {
ee80f7c7 708 c->ases |= MIPS_ASE_DSP2P;
b5a6455c
ZLK		 709 if (cpu_has_mips_r6)
710 c->ases |= MIPS_ASE_DSP3;
711 }
2fa36399
KC		 712 if (config3 & MIPS_CONF3_VINT)
713 c->options |= MIPS_CPU_VINT;
714 if (config3 & MIPS_CONF3_VEIC)
715 c->options |= MIPS_CPU_VEIC;
12822570
JH		 716 if (config3 & MIPS_CONF3_LPA)
717 c->options |= MIPS_CPU_LPA;
2fa36399
KC		 718 if (config3 & MIPS_CONF3_MT)
719 c->ases |= MIPS_ASE_MIPSMT;
720 if (config3 & MIPS_CONF3_ULRI)
721 c->options |= MIPS_CPU_ULRI;
f8fa4811
SH		 722 if (config3 & MIPS_CONF3_ISA)
723 c->options |= MIPS_CPU_MICROMIPS;
1e7decdb
DD		 724 if (config3 & MIPS_CONF3_VZ)
725 c->ases |= MIPS_ASE_VZ;
4a0156fb
SH		 726 if (config3 & MIPS_CONF3_SC)
727 c->options |= MIPS_CPU_SEGMENTS;
e06a1548
JH		 728 if (config3 & MIPS_CONF3_BI)
729 c->options |= MIPS_CPU_BADINSTR;
730 if (config3 & MIPS_CONF3_BP)
731 c->options |= MIPS_CPU_BADINSTRP;
a5e9a69e
PB		 732 if (config3 & MIPS_CONF3_MSA)
733 c->ases |= MIPS_ASE_MSA;
cab25bc7 734 if (config3 & MIPS_CONF3_PW) {
ed4cbc81 735 c->htw_seq = 0;
3d528b32 736 c->options |= MIPS_CPU_HTW;
ed4cbc81 737 }
9b3274bd
JH		 738 if (config3 & MIPS_CONF3_CDMM)
739 c->options |= MIPS_CPU_CDMM;
aaa7be48
JH		 740 if (config3 & MIPS_CONF3_SP)
741 c->options |= MIPS_CPU_SP;
2fa36399
KC		 742
743 return config3 & MIPS_CONF_M;
744}
745
746static inline unsigned int decode_config4(struct cpuinfo_mips *c)
747{
748 unsigned int config4;
75b5b5e0
LY		 749 unsigned int newcf4;
750 unsigned int mmuextdef;
751 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
2db003a5 752 unsigned long asid_mask;
2fa36399
KC		 753
754 config4 = read_c0_config4();
755
1745c1ef
LY		 756 if (cpu_has_tlb) {
757 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
758 c->options |= MIPS_CPU_TLBINV;
43d104db 759
e87569cd 760 /*
43d104db
JH		 761 * R6 has dropped the MMUExtDef field from config4.
762 * On R6 the fields always describe the FTLB, and only if it is
763 * present according to Config.MT.
e87569cd 764 */
43d104db
JH		 765 if (!cpu_has_mips_r6)
766 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
767 else if (cpu_has_ftlb)
e87569cd
MC		 768 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
769 else
43d104db 770 mmuextdef = 0;
e87569cd 771
75b5b5e0
LY		 772 switch (mmuextdef) {
773 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
774 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
775 c->tlbsizevtlb = c->tlbsize;
776 break;
777 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
778 c->tlbsizevtlb +=
779 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
780 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
781 c->tlbsize = c->tlbsizevtlb;
782 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
783 /* fall through */
784 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
97f4ad29
MC		 785 if (mips_ftlb_disabled)
786 break;
75b5b5e0
LY		 787 newcf4 = (config4 & ~ftlb_page) |
788 (page_size_ftlb(mmuextdef) <<
789 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
790 write_c0_config4(newcf4);
791 back_to_back_c0_hazard();
792 config4 = read_c0_config4();
793 if (config4 != newcf4) {
794 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
795 PAGE_SIZE, config4);
796 /* Switch FTLB off */
797 set_ftlb_enable(c, 0);
ebd0e0f5 798 mips_ftlb_disabled = 1;
75b5b5e0
LY		 799 break;
800 }
801 c->tlbsizeftlbsets = 1 <<
802 ((config4 & MIPS_CONF4_FTLBSETS) >>
803 MIPS_CONF4_FTLBSETS_SHIFT);
804 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
805 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
806 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
97f4ad29 807 mips_has_ftlb_configured = 1;
75b5b5e0
LY		 808 break;
809 }
1745c1ef
LY		 810 }
811
9e575f75
JH		 812 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
813 >> MIPS_CONF4_KSCREXIST_SHIFT;
2fa36399 814
2db003a5
PB		 815 asid_mask = MIPS_ENTRYHI_ASID;
816 if (config4 & MIPS_CONF4_AE)
817 asid_mask |= MIPS_ENTRYHI_ASIDX;
818 set_cpu_asid_mask(c, asid_mask);
819
820 /*
821 * Warn if the computed ASID mask doesn't match the mask the kernel
822 * is built for. This may indicate either a serious problem or an
823 * easy optimisation opportunity, but either way should be addressed.
824 */
825 WARN_ON(asid_mask != cpu_asid_mask(c));
826
2fa36399
KC		 827 return config4 & MIPS_CONF_M;
828}
829
8b8a7634
RB		 830static inline unsigned int decode_config5(struct cpuinfo_mips *c)
831{
832 unsigned int config5;
833
834 config5 = read_c0_config5();
d175ed2b 835 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
8b8a7634
RB		 836 write_c0_config5(config5);
837
49016748
MC		 838 if (config5 & MIPS_CONF5_EVA)
839 c->options |= MIPS_CPU_EVA;
1f6c52ff
PB		 840 if (config5 & MIPS_CONF5_MRP)
841 c->options |= MIPS_CPU_MAAR;
5aed9da1
MC		 842 if (config5 & MIPS_CONF5_LLB)
843 c->options |= MIPS_CPU_RW_LLB;
c5b36783 844 if (config5 & MIPS_CONF5_MVH)
0f2d988d 845 c->options |= MIPS_CPU_MVH;
f270d881
PB		 846 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
847 c->options |= MIPS_CPU_VP;
49016748 848
8b8a7634
RB		 849 return config5 & MIPS_CONF_M;
850}
851
078a55fc 852static void decode_configs(struct cpuinfo_mips *c)
2fa36399
KC		 853{
854 int ok;
855
856 /* MIPS32 or MIPS64 compliant CPU. */
857 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
858 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
859
860 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
861
97f4ad29 862 /* Enable FTLB if present and not disabled */
ebd0e0f5 863 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN);
75b5b5e0 864
2fa36399 865 ok = decode_config0(c); /* Read Config registers. */
70342287 866 BUG_ON(!ok); /* Arch spec violation! */
2fa36399
KC		 867 if (ok)
868 ok = decode_config1(c);
869 if (ok)
870 ok = decode_config2(c);
871 if (ok)
872 ok = decode_config3(c);
873 if (ok)
874 ok = decode_config4(c);
8b8a7634
RB		 875 if (ok)
876 ok = decode_config5(c);
2fa36399 877
37fb60f8
JH		 878 /* Probe the EBase.WG bit */
879 if (cpu_has_mips_r2_r6) {
880 u64 ebase;
881 unsigned int status;
882
883 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
884 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
885 : (s32)read_c0_ebase();
886 if (ebase & MIPS_EBASE_WG) {
887 /* WG bit already set, we can avoid the clumsy probe */
888 c->options |= MIPS_CPU_EBASE_WG;
889 } else {
890 /* Its UNDEFINED to change EBase while BEV=0 */
891 status = read_c0_status();
892 write_c0_status(status | ST0_BEV);
893 irq_enable_hazard();
894 /*
895 * On pre-r6 cores, this may well clobber the upper bits
896 * of EBase. This is hard to avoid without potentially
897 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
898 */
899 if (cpu_has_mips64r6)
900 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
901 else
902 write_c0_ebase(ebase | MIPS_EBASE_WG);
903 back_to_back_c0_hazard();
904 /* Restore BEV */
905 write_c0_status(status);
906 if (read_c0_ebase() & MIPS_EBASE_WG) {
907 c->options |= MIPS_CPU_EBASE_WG;
908 write_c0_ebase(ebase);
909 }
910 }
911 }
912
ebd0e0f5
PB		 913 /* configure the FTLB write probability */
914 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
915
2fa36399
KC		 916 mips_probe_watch_registers(c);
917
0ee958e1 918#ifndef CONFIG_MIPS_CPS
8b8aa636 919 if (cpu_has_mips_r2_r6) {
45b585c8 920 c->core = get_ebase_cpunum();
30ee615b
PB		 921 if (cpu_has_mipsmt)
922 c->core >>= fls(core_nvpes()) - 1;
923 }
0ee958e1 924#endif
2fa36399
KC		 925}
926
6ad816e7
JH		 927/*
928 * Probe for certain guest capabilities by writing config bits and reading back.
929 * Finally write back the original value.
930 */
931#define probe_gc0_config(name, maxconf, bits) \
932do { \
933 unsigned int tmp; \
934 tmp = read_gc0_##name(); \
935 write_gc0_##name(tmp | (bits)); \
936 back_to_back_c0_hazard(); \
937 maxconf = read_gc0_##name(); \
938 write_gc0_##name(tmp); \
939} while (0)
940
941/*
942 * Probe for dynamic guest capabilities by changing certain config bits and
943 * reading back to see if they change. Finally write back the original value.
944 */
945#define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \
946do { \
947 maxconf = read_gc0_##name(); \
948 write_gc0_##name(maxconf ^ (bits)); \
949 back_to_back_c0_hazard(); \
950 dynconf = maxconf ^ read_gc0_##name(); \
951 write_gc0_##name(maxconf); \
952 maxconf |= dynconf; \
953} while (0)
954
955static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
956{
957 unsigned int config0;
958
959 probe_gc0_config(config, config0, MIPS_CONF_M);
960
961 if (config0 & MIPS_CONF_M)
962 c->guest.conf |= BIT(1);
963 return config0 & MIPS_CONF_M;
964}
965
966static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
967{
968 unsigned int config1, config1_dyn;
969
970 probe_gc0_config_dyn(config1, config1, config1_dyn,
971 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
972 MIPS_CONF1_FP);
973
974 if (config1 & MIPS_CONF1_FP)
975 c->guest.options |= MIPS_CPU_FPU;
976 if (config1_dyn & MIPS_CONF1_FP)
977 c->guest.options_dyn |= MIPS_CPU_FPU;
978
979 if (config1 & MIPS_CONF1_WR)
980 c->guest.options |= MIPS_CPU_WATCH;
981 if (config1_dyn & MIPS_CONF1_WR)
982 c->guest.options_dyn |= MIPS_CPU_WATCH;
983
984 if (config1 & MIPS_CONF1_PC)
985 c->guest.options |= MIPS_CPU_PERF;
986 if (config1_dyn & MIPS_CONF1_PC)
987 c->guest.options_dyn |= MIPS_CPU_PERF;
988
989 if (config1 & MIPS_CONF_M)
990 c->guest.conf |= BIT(2);
991 return config1 & MIPS_CONF_M;
992}
993
994static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
995{
996 unsigned int config2;
997
998 probe_gc0_config(config2, config2, MIPS_CONF_M);
999
1000 if (config2 & MIPS_CONF_M)
1001 c->guest.conf |= BIT(3);
1002 return config2 & MIPS_CONF_M;
1003}
1004
1005static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
1006{
1007 unsigned int config3, config3_dyn;
1008
1009 probe_gc0_config_dyn(config3, config3, config3_dyn,
a7c7ad6c
JH		 1010 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI |
1011 MIPS_CONF3_CTXTC);
6ad816e7
JH		 1012
1013 if (config3 & MIPS_CONF3_CTXTC)
1014 c->guest.options |= MIPS_CPU_CTXTC;
1015 if (config3_dyn & MIPS_CONF3_CTXTC)
1016 c->guest.options_dyn |= MIPS_CPU_CTXTC;
1017
1018 if (config3 & MIPS_CONF3_PW)
1019 c->guest.options |= MIPS_CPU_HTW;
1020
a7c7ad6c
JH		 1021 if (config3 & MIPS_CONF3_ULRI)
1022 c->guest.options |= MIPS_CPU_ULRI;
1023
6ad816e7
JH		 1024 if (config3 & MIPS_CONF3_SC)
1025 c->guest.options |= MIPS_CPU_SEGMENTS;
1026
1027 if (config3 & MIPS_CONF3_BI)
1028 c->guest.options |= MIPS_CPU_BADINSTR;
1029 if (config3 & MIPS_CONF3_BP)
1030 c->guest.options |= MIPS_CPU_BADINSTRP;
1031
1032 if (config3 & MIPS_CONF3_MSA)
1033 c->guest.ases |= MIPS_ASE_MSA;
1034 if (config3_dyn & MIPS_CONF3_MSA)
1035 c->guest.ases_dyn |= MIPS_ASE_MSA;
1036
1037 if (config3 & MIPS_CONF_M)
1038 c->guest.conf |= BIT(4);
1039 return config3 & MIPS_CONF_M;
1040}
1041
1042static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
1043{
1044 unsigned int config4;
1045
1046 probe_gc0_config(config4, config4,
1047 MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
1048
1049 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
1050 >> MIPS_CONF4_KSCREXIST_SHIFT;
1051
1052 if (config4 & MIPS_CONF_M)
1053 c->guest.conf |= BIT(5);
1054 return config4 & MIPS_CONF_M;
1055}
1056
1057static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
1058{
1059 unsigned int config5, config5_dyn;
1060
1061 probe_gc0_config_dyn(config5, config5, config5_dyn,
a929bdc5 1062 MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP);
6ad816e7
JH		 1063
1064 if (config5 & MIPS_CONF5_MRP)
1065 c->guest.options |= MIPS_CPU_MAAR;
1066 if (config5_dyn & MIPS_CONF5_MRP)
1067 c->guest.options_dyn |= MIPS_CPU_MAAR;
1068
1069 if (config5 & MIPS_CONF5_LLB)
1070 c->guest.options |= MIPS_CPU_RW_LLB;
1071
a929bdc5
JH		 1072 if (config5 & MIPS_CONF5_MVH)
1073 c->guest.options |= MIPS_CPU_MVH;
1074
6ad816e7
JH		 1075 if (config5 & MIPS_CONF_M)
1076 c->guest.conf |= BIT(6);
1077 return config5 & MIPS_CONF_M;
1078}
1079
1080static inline void decode_guest_configs(struct cpuinfo_mips *c)
1081{
1082 unsigned int ok;
1083
1084 ok = decode_guest_config0(c);
1085 if (ok)
1086 ok = decode_guest_config1(c);
1087 if (ok)
1088 ok = decode_guest_config2(c);
1089 if (ok)
1090 ok = decode_guest_config3(c);
1091 if (ok)
1092 ok = decode_guest_config4(c);
1093 if (ok)
1094 decode_guest_config5(c);
1095}
1096
1097static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
1098{
1099 unsigned int guestctl0, temp;
1100
1101 guestctl0 = read_c0_guestctl0();
1102
1103 if (guestctl0 & MIPS_GCTL0_G0E)
1104 c->options |= MIPS_CPU_GUESTCTL0EXT;
1105 if (guestctl0 & MIPS_GCTL0_G1)
1106 c->options |= MIPS_CPU_GUESTCTL1;
1107 if (guestctl0 & MIPS_GCTL0_G2)
1108 c->options |= MIPS_CPU_GUESTCTL2;
1109 if (!(guestctl0 & MIPS_GCTL0_RAD)) {
1110 c->options |= MIPS_CPU_GUESTID;
1111
1112 /*
1113 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
1114 * first, otherwise all data accesses will be fully virtualised
1115 * as if they were performed by guest mode.
1116 */
1117 write_c0_guestctl1(0);
1118 tlbw_use_hazard();
1119
1120 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
1121 back_to_back_c0_hazard();
1122 temp = read_c0_guestctl0();
1123
1124 if (temp & MIPS_GCTL0_DRG) {
1125 write_c0_guestctl0(guestctl0);
1126 c->options |= MIPS_CPU_DRG;
1127 }
1128 }
1129}
1130
1131static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
1132{
1133 if (cpu_has_guestid) {
1134 /* determine the number of bits of GuestID available */
1135 write_c0_guestctl1(MIPS_GCTL1_ID);
1136 back_to_back_c0_hazard();
1137 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
1138 >> MIPS_GCTL1_ID_SHIFT;
1139 write_c0_guestctl1(0);
1140 }
1141}
1142
1143static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
1144{
1145 /* determine the number of bits of GTOffset available */
1146 write_c0_gtoffset(0xffffffff);
1147 back_to_back_c0_hazard();
1148 c->gtoffset_mask = read_c0_gtoffset();
1149 write_c0_gtoffset(0);
1150}
1151
1152static inline void cpu_probe_vz(struct cpuinfo_mips *c)
1153{
1154 cpu_probe_guestctl0(c);
1155 if (cpu_has_guestctl1)
1156 cpu_probe_guestctl1(c);
1157
1158 cpu_probe_gtoffset(c);
1159
1160 decode_guest_configs(c);
1161}
1162
02cf2119 1163#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 1164 | MIPS_CPU_COUNTER)
1165
cea7e2df 1166static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1167{
8ff374b9 1168 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1169 case PRID_IMP_R2000:
1170 c->cputype = CPU_R2000;
cea7e2df 1171 __cpu_name[cpu] = "R2000";
9b26616c 1172 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 1173 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 1174 MIPS_CPU_NOFPUEX;
1da177e4
LT		 1175 if (__cpu_has_fpu())
1176 c->options |= MIPS_CPU_FPU;
1177 c->tlbsize = 64;
1178 break;
1179 case PRID_IMP_R3000:
8ff374b9 1180 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
cea7e2df 1181 if (cpu_has_confreg()) {
1da177e4 1182 c->cputype = CPU_R3081E;
cea7e2df
RB		 1183 __cpu_name[cpu] = "R3081";
1184 } else {
1da177e4 1185 c->cputype = CPU_R3000A;
cea7e2df
RB		 1186 __cpu_name[cpu] = "R3000A";
1187 }
cea7e2df 1188 } else {
1da177e4 1189 c->cputype = CPU_R3000;
cea7e2df
RB		 1190 __cpu_name[cpu] = "R3000";
1191 }
9b26616c 1192 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 1193 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 1194 MIPS_CPU_NOFPUEX;
1da177e4
LT		 1195 if (__cpu_has_fpu())
1196 c->options |= MIPS_CPU_FPU;
1197 c->tlbsize = 64;
1198 break;
1199 case PRID_IMP_R4000:
1200 if (read_c0_config() & CONF_SC) {
8ff374b9
MR		 1201 if ((c->processor_id & PRID_REV_MASK) >=
1202 PRID_REV_R4400) {
1da177e4 1203 c->cputype = CPU_R4400PC;
cea7e2df
RB		 1204 __cpu_name[cpu] = "R4400PC";
1205 } else {
1da177e4 1206 c->cputype = CPU_R4000PC;
cea7e2df
RB		 1207 __cpu_name[cpu] = "R4000PC";
1208 }
1da177e4 1209 } else {
7f177a52
MR		 1210 int cca = read_c0_config() & CONF_CM_CMASK;
1211 int mc;
1212
1213 /*
1214 * SC and MC versions can't be reliably told apart,
1215 * but only the latter support coherent caching
1216 * modes so assume the firmware has set the KSEG0
1217 * coherency attribute reasonably (if uncached, we
1218 * assume SC).
1219 */
1220 switch (cca) {
1221 case CONF_CM_CACHABLE_CE:
1222 case CONF_CM_CACHABLE_COW:
1223 case CONF_CM_CACHABLE_CUW:
1224 mc = 1;
1225 break;
1226 default:
1227 mc = 0;
1228 break;
1229 }
8ff374b9
MR		 1230 if ((c->processor_id & PRID_REV_MASK) >=
1231 PRID_REV_R4400) {
7f177a52
MR		 1232 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
1233 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
cea7e2df 1234 } else {
7f177a52
MR		 1235 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
1236 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
cea7e2df 1237 }
1da177e4
LT		 1238 }
1239
a96102be 1240 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1241 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 1242 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 1243 MIPS_CPU_WATCH | MIPS_CPU_VCE |
1244 MIPS_CPU_LLSC;
1da177e4
LT		 1245 c->tlbsize = 48;
1246 break;
1247 case PRID_IMP_VR41XX:
9f91e506 1248 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1249 c->fpu_msk31 |= FPU_CSR_CONDX;
9f91e506
YY		 1250 c->options = R4K_OPTS;
1251 c->tlbsize = 32;
1da177e4 1252 switch (c->processor_id & 0xf0) {
1da177e4
LT		 1253 case PRID_REV_VR4111:
1254 c->cputype = CPU_VR4111;
cea7e2df 1255 __cpu_name[cpu] = "NEC VR4111";
1da177e4 1256 break;
1da177e4
LT		 1257 case PRID_REV_VR4121:
1258 c->cputype = CPU_VR4121;
cea7e2df 1259 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 1260 break;
1261 case PRID_REV_VR4122:
cea7e2df 1262 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 1263 c->cputype = CPU_VR4122;
cea7e2df
RB		 1264 __cpu_name[cpu] = "NEC VR4122";
1265 } else {
1da177e4 1266 c->cputype = CPU_VR4181A;
cea7e2df
RB		 1267 __cpu_name[cpu] = "NEC VR4181A";
1268 }
1da177e4
LT		 1269 break;
1270 case PRID_REV_VR4130:
cea7e2df 1271 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 1272 c->cputype = CPU_VR4131;
cea7e2df
RB		 1273 __cpu_name[cpu] = "NEC VR4131";
1274 } else {
1da177e4 1275 c->cputype = CPU_VR4133;
9f91e506 1276 c->options |= MIPS_CPU_LLSC;
cea7e2df
RB		 1277 __cpu_name[cpu] = "NEC VR4133";
1278 }
1da177e4
LT		 1279 break;
1280 default:
1281 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
1282 c->cputype = CPU_VR41XX;
cea7e2df 1283 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 1284 break;
1285 }
1da177e4
LT		 1286 break;
1287 case PRID_IMP_R4300:
1288 c->cputype = CPU_R4300;
cea7e2df 1289 __cpu_name[cpu] = "R4300";
a96102be 1290 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1291 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 1292 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1293 MIPS_CPU_LLSC;
1da177e4
LT		 1294 c->tlbsize = 32;
1295 break;
1296 case PRID_IMP_R4600:
1297 c->cputype = CPU_R4600;
cea7e2df 1298 __cpu_name[cpu] = "R4600";
a96102be 1299 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1300 c->fpu_msk31 |= FPU_CSR_CONDX;
075e7502
TS		 1301 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1302 MIPS_CPU_LLSC;
1da177e4
LT		 1303 c->tlbsize = 48;
1304 break;
1305 #if 0
03751e79 1306 case PRID_IMP_R4650:
1da177e4
LT		 1307 /*
1308 * This processor doesn't have an MMU, so it's not
1309 * "real easy" to run Linux on it. It is left purely
1310 * for documentation. Commented out because it shares
1311 * it's c0_prid id number with the TX3900.
1312 */
a3dddd56 1313 c->cputype = CPU_R4650;
cea7e2df 1314 __cpu_name[cpu] = "R4650";
a96102be 1315 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1316 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 1317 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 1318 c->tlbsize = 48;
1da177e4
LT		 1319 break;
1320 #endif
1321 case PRID_IMP_TX39:
9b26616c 1322 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 1323 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 1324
1325 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1326 c->cputype = CPU_TX3927;
cea7e2df 1327 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 1328 c->tlbsize = 64;
1329 } else {
8ff374b9 1330 switch (c->processor_id & PRID_REV_MASK) {
1da177e4
LT		 1331 case PRID_REV_TX3912:
1332 c->cputype = CPU_TX3912;
cea7e2df 1333 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 1334 c->tlbsize = 32;
1335 break;
1336 case PRID_REV_TX3922:
1337 c->cputype = CPU_TX3922;
cea7e2df 1338 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 1339 c->tlbsize = 64;
1340 break;
1da177e4
LT		 1341 }
1342 }
1343 break;
1344 case PRID_IMP_R4700:
1345 c->cputype = CPU_R4700;
cea7e2df 1346 __cpu_name[cpu] = "R4700";
a96102be 1347 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1348 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 1349 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1350 MIPS_CPU_LLSC;
1da177e4
LT		 1351 c->tlbsize = 48;
1352 break;
1353 case PRID_IMP_TX49:
1354 c->cputype = CPU_TX49XX;
cea7e2df 1355 __cpu_name[cpu] = "R49XX";
a96102be 1356 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1357 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4
LT		 1358 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1359 if (!(c->processor_id & 0x08))
1360 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1361 c->tlbsize = 48;
1362 break;
1363 case PRID_IMP_R5000:
1364 c->cputype = CPU_R5000;
cea7e2df 1365 __cpu_name[cpu] = "R5000";
a96102be 1366 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1367 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1368 MIPS_CPU_LLSC;
1da177e4
LT		 1369 c->tlbsize = 48;
1370 break;
1371 case PRID_IMP_R5432:
1372 c->cputype = CPU_R5432;
cea7e2df 1373 __cpu_name[cpu] = "R5432";
a96102be 1374 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1375 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1376 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 1377 c->tlbsize = 48;
1378 break;
1379 case PRID_IMP_R5500:
1380 c->cputype = CPU_R5500;
cea7e2df 1381 __cpu_name[cpu] = "R5500";
a96102be 1382 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1383 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1384 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 1385 c->tlbsize = 48;
1386 break;
1387 case PRID_IMP_NEVADA:
1388 c->cputype = CPU_NEVADA;
cea7e2df 1389 __cpu_name[cpu] = "Nevada";
a96102be 1390 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1391 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1392 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 1393 c->tlbsize = 48;
1394 break;
1395 case PRID_IMP_R6000:
1396 c->cputype = CPU_R6000;
cea7e2df 1397 __cpu_name[cpu] = "R6000";
a96102be 1398 set_isa(c, MIPS_CPU_ISA_II);
9b26616c 1399 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1da177e4 1400 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 1401 MIPS_CPU_LLSC;
1da177e4
LT		 1402 c->tlbsize = 32;
1403 break;
1404 case PRID_IMP_R6000A:
1405 c->cputype = CPU_R6000A;
cea7e2df 1406 __cpu_name[cpu] = "R6000A";
a96102be 1407 set_isa(c, MIPS_CPU_ISA_II);
9b26616c 1408 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1da177e4 1409 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 1410 MIPS_CPU_LLSC;
1da177e4
LT		 1411 c->tlbsize = 32;
1412 break;
1413 case PRID_IMP_RM7000:
1414 c->cputype = CPU_RM7000;
cea7e2df 1415 __cpu_name[cpu] = "RM7000";
a96102be 1416 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1417 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1418 MIPS_CPU_LLSC;
1da177e4 1419 /*
70342287 1420 * Undocumented RM7000: Bit 29 in the info register of
1da177e4
LT		 1421 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1422 * entries.
1423 *
70342287
RB		 1424 * 29 1 => 64 entry JTLB
1425 * 0 => 48 entry JTLB
1da177e4
LT		 1426 */
1427 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1da177e4
LT		 1428 break;
1429 case PRID_IMP_R8000:
1430 c->cputype = CPU_R8000;
cea7e2df 1431 __cpu_name[cpu] = "RM8000";
a96102be 1432 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1433 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 1434 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1435 MIPS_CPU_LLSC;
1da177e4
LT		 1436 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
1437 break;
1438 case PRID_IMP_R10000:
1439 c->cputype = CPU_R10000;
cea7e2df 1440 __cpu_name[cpu] = "R10000";
a96102be 1441 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 1442 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 1443 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 1444 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 1445 MIPS_CPU_LLSC;
1da177e4
LT		 1446 c->tlbsize = 64;
1447 break;
1448 case PRID_IMP_R12000:
1449 c->cputype = CPU_R12000;
cea7e2df 1450 __cpu_name[cpu] = "R12000";
a96102be 1451 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 1452 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 1453 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 1454 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
8d5ded16 1455 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1da177e4
LT		 1456 c->tlbsize = 64;
1457 break;
44d921b2 1458 case PRID_IMP_R14000:
30577391
JK		 1459 if (((c->processor_id >> 4) & 0x0f) > 2) {
1460 c->cputype = CPU_R16000;
1461 __cpu_name[cpu] = "R16000";
1462 } else {
1463 c->cputype = CPU_R14000;
1464 __cpu_name[cpu] = "R14000";
1465 }
a96102be 1466 set_isa(c, MIPS_CPU_ISA_IV);
44d921b2 1467 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 1468 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 1469 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
8d5ded16 1470 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
44d921b2
K		 1471 c->tlbsize = 64;
1472 break;
26859198 1473 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
5aac1e8a
RM		 1474 switch (c->processor_id & PRID_REV_MASK) {
1475 case PRID_REV_LOONGSON2E:
c579d310
HC		 1476 c->cputype = CPU_LOONGSON2;
1477 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 1478 set_elf_platform(cpu, "loongson2e");
7352c8b1 1479 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1480 c->fpu_msk31 |= FPU_CSR_CONDX;
5aac1e8a
RM		 1481 break;
1482 case PRID_REV_LOONGSON2F:
c579d310
HC		 1483 c->cputype = CPU_LOONGSON2;
1484 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 1485 set_elf_platform(cpu, "loongson2f");
7352c8b1 1486 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1487 c->fpu_msk31 |= FPU_CSR_CONDX;
5aac1e8a 1488 break;
b2edcfc8 1489 case PRID_REV_LOONGSON3A_R1:
c579d310
HC		 1490 c->cputype = CPU_LOONGSON3;
1491 __cpu_name[cpu] = "ICT Loongson-3";
1492 set_elf_platform(cpu, "loongson3a");
7352c8b1 1493 set_isa(c, MIPS_CPU_ISA_M64R1);
c579d310 1494 break;
e7841be5
HC		 1495 case PRID_REV_LOONGSON3B_R1:
1496 case PRID_REV_LOONGSON3B_R2:
1497 c->cputype = CPU_LOONGSON3;
1498 __cpu_name[cpu] = "ICT Loongson-3";
1499 set_elf_platform(cpu, "loongson3b");
7352c8b1 1500 set_isa(c, MIPS_CPU_ISA_M64R1);
e7841be5 1501 break;
5aac1e8a
RM		 1502 }
1503
2a21c730
FZ		 1504 c->options = R4K_OPTS |
1505 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1506 MIPS_CPU_32FPR;
1507 c->tlbsize = 64;
cc94ea31 1508 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2a21c730 1509 break;
26859198 1510 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
2fa36399 1511 decode_configs(c);
b4672d37 1512
2fa36399 1513 c->cputype = CPU_LOONGSON1;
1da177e4 1514
2fa36399
KC		 1515 switch (c->processor_id & PRID_REV_MASK) {
1516 case PRID_REV_LOONGSON1B:
1517 __cpu_name[cpu] = "Loongson 1B";
b4672d37 1518 break;
b4672d37 1519 }
4194318c 1520
2fa36399 1521 break;
1da177e4 1522 }
1da177e4
LT		 1523}
1524
cea7e2df 1525static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1526{
4f12b91d 1527 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 1528 switch (c->processor_id & PRID_IMP_MASK) {
b2498af5
LY		 1529 case PRID_IMP_QEMU_GENERIC:
1530 c->writecombine = _CACHE_UNCACHED;
1531 c->cputype = CPU_QEMU_GENERIC;
1532 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1533 break;
1da177e4
LT		 1534 case PRID_IMP_4KC:
1535 c->cputype = CPU_4KC;
4f12b91d 1536 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1537 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 1538 break;
1539 case PRID_IMP_4KEC:
2b07bd02
RB		 1540 case PRID_IMP_4KECR2:
1541 c->cputype = CPU_4KEC;
4f12b91d 1542 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1543 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 1544 break;
1da177e4 1545 case PRID_IMP_4KSC:
8afcb5d8 1546 case PRID_IMP_4KSD:
1da177e4 1547 c->cputype = CPU_4KSC;
4f12b91d 1548 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1549 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 1550 break;
1551 case PRID_IMP_5KC:
1552 c->cputype = CPU_5KC;
4f12b91d 1553 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1554 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4 1555 break;
78d4803f
LY		 1556 case PRID_IMP_5KE:
1557 c->cputype = CPU_5KE;
4f12b91d 1558 c->writecombine = _CACHE_UNCACHED;
78d4803f
LY		 1559 __cpu_name[cpu] = "MIPS 5KE";
1560 break;
1da177e4
LT		 1561 case PRID_IMP_20KC:
1562 c->cputype = CPU_20KC;
4f12b91d 1563 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1564 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 1565 break;
1566 case PRID_IMP_24K:
1567 c->cputype = CPU_24K;
4f12b91d 1568 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1569 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4 1570 break;
42f3caef
JC		 1571 case PRID_IMP_24KE:
1572 c->cputype = CPU_24K;
4f12b91d 1573 c->writecombine = _CACHE_UNCACHED;
42f3caef
JC		 1574 __cpu_name[cpu] = "MIPS 24KEc";
1575 break;
1da177e4
LT		 1576 case PRID_IMP_25KF:
1577 c->cputype = CPU_25KF;
4f12b91d 1578 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1579 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 1580 break;
bbc7f22f
RB		 1581 case PRID_IMP_34K:
1582 c->cputype = CPU_34K;
4f12b91d 1583 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1584 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 1585 break;
c620953c
CD		 1586 case PRID_IMP_74K:
1587 c->cputype = CPU_74K;
4f12b91d 1588 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1589 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 1590 break;
113c62d9
SH		 1591 case PRID_IMP_M14KC:
1592 c->cputype = CPU_M14KC;
4f12b91d 1593 c->writecombine = _CACHE_UNCACHED;
113c62d9
SH		 1594 __cpu_name[cpu] = "MIPS M14Kc";
1595 break;
f8fa4811
SH		 1596 case PRID_IMP_M14KEC:
1597 c->cputype = CPU_M14KEC;
4f12b91d 1598 c->writecombine = _CACHE_UNCACHED;
f8fa4811
SH		 1599 __cpu_name[cpu] = "MIPS M14KEc";
1600 break;
39b8d525
RB		 1601 case PRID_IMP_1004K:
1602 c->cputype = CPU_1004K;
4f12b91d 1603 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1604 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 1605 break;
006a851b 1606 case PRID_IMP_1074K:
442e14a2 1607 c->cputype = CPU_1074K;
4f12b91d 1608 c->writecombine = _CACHE_UNCACHED;
006a851b
SH		 1609 __cpu_name[cpu] = "MIPS 1074Kc";
1610 break;
b5f065e7
LY		 1611 case PRID_IMP_INTERAPTIV_UP:
1612 c->cputype = CPU_INTERAPTIV;
1613 __cpu_name[cpu] = "MIPS interAptiv";
1614 break;
1615 case PRID_IMP_INTERAPTIV_MP:
1616 c->cputype = CPU_INTERAPTIV;
1617 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1618 break;
b0d4d300
LY		 1619 case PRID_IMP_PROAPTIV_UP:
1620 c->cputype = CPU_PROAPTIV;
1621 __cpu_name[cpu] = "MIPS proAptiv";
1622 break;
1623 case PRID_IMP_PROAPTIV_MP:
1624 c->cputype = CPU_PROAPTIV;
1625 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1626 break;
829dcc0a
JH		 1627 case PRID_IMP_P5600:
1628 c->cputype = CPU_P5600;
1629 __cpu_name[cpu] = "MIPS P5600";
1630 break;
eba20a3a
PB		 1631 case PRID_IMP_P6600:
1632 c->cputype = CPU_P6600;
1633 __cpu_name[cpu] = "MIPS P6600";
1634 break;
e57f9a2d
MC		 1635 case PRID_IMP_I6400:
1636 c->cputype = CPU_I6400;
1637 __cpu_name[cpu] = "MIPS I6400";
1638 break;
859aeb1b
PB		 1639 case PRID_IMP_I6500:
1640 c->cputype = CPU_I6500;
1641 __cpu_name[cpu] = "MIPS I6500";
1642 break;
9943ed92
LY		 1643 case PRID_IMP_M5150:
1644 c->cputype = CPU_M5150;
1645 __cpu_name[cpu] = "MIPS M5150";
1646 break;
43aff742
PB		 1647 case PRID_IMP_M6250:
1648 c->cputype = CPU_M6250;
1649 __cpu_name[cpu] = "MIPS M6250";
1650 break;
1da177e4 1651 }
0b6d497f 1652
75b5b5e0
LY		 1653 decode_configs(c);
1654
0b6d497f 1655 spram_config();
1da177e4
LT		 1656}
1657
cea7e2df 1658static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1659{
4194318c 1660 decode_configs(c);
8ff374b9 1661 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1662 case PRID_IMP_AU1_REV1:
1663 case PRID_IMP_AU1_REV2:
270717a8 1664 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 1665 switch ((c->processor_id >> 24) & 0xff) {
1666 case 0:
cea7e2df 1667 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 1668 break;
1669 case 1:
cea7e2df 1670 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 1671 break;
1672 case 2:
cea7e2df 1673 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 1674 break;
1675 case 3:
cea7e2df 1676 __cpu_name[cpu] = "Au1550";
1da177e4 1677 break;
e3ad1c23 1678 case 4:
cea7e2df 1679 __cpu_name[cpu] = "Au1200";
8ff374b9 1680 if ((c->processor_id & PRID_REV_MASK) == 2)
cea7e2df 1681 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 1682 break;
1683 case 5:
cea7e2df 1684 __cpu_name[cpu] = "Au1210";
e3ad1c23 1685 break;
1da177e4 1686 default:
270717a8 1687 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 1688 break;
1689 }
1da177e4
LT		 1690 break;
1691 }
1692}
1693
cea7e2df 1694static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1695{
4194318c 1696 decode_configs(c);
02cf2119 1697
4f12b91d 1698 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 1699 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1700 case PRID_IMP_SB1:
1701 c->cputype = CPU_SB1;
cea7e2df 1702 __cpu_name[cpu] = "SiByte SB1";
1da177e4 1703 /* FPU in pass1 is known to have issues. */
8ff374b9 1704 if ((c->processor_id & PRID_REV_MASK) < 0x02)
010b853b 1705 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 1706 break;
93ce2f52
AI		 1707 case PRID_IMP_SB1A:
1708 c->cputype = CPU_SB1A;
cea7e2df 1709 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 1710 break;
1da177e4
LT		 1711 }
1712}
1713
cea7e2df 1714static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1715{
4194318c 1716 decode_configs(c);
8ff374b9 1717 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1718 case PRID_IMP_SR71000:
1719 c->cputype = CPU_SR71000;
cea7e2df 1720 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 1721 c->scache.ways = 8;
1722 c->tlbsize = 64;
1723 break;
1724 }
1725}
1726
cea7e2df 1727static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 1728{
1729 decode_configs(c);
8ff374b9 1730 switch (c->processor_id & PRID_IMP_MASK) {
bdf21b18
PP		 1731 case PRID_IMP_PR4450:
1732 c->cputype = CPU_PR4450;
cea7e2df 1733 __cpu_name[cpu] = "Philips PR4450";
a96102be 1734 set_isa(c, MIPS_CPU_ISA_M32R1);
bdf21b18 1735 break;
bdf21b18
PP		 1736 }
1737}
1738
cea7e2df 1739static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 1740{
1741 decode_configs(c);
8ff374b9 1742 switch (c->processor_id & PRID_IMP_MASK) {
190fca3e
KC		 1743 case PRID_IMP_BMIPS32_REV4:
1744 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 1745 c->cputype = CPU_BMIPS32;
1746 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 1747 set_elf_platform(cpu, "bmips32");
602977b0
KC		 1748 break;
1749 case PRID_IMP_BMIPS3300:
1750 case PRID_IMP_BMIPS3300_ALT:
1751 case PRID_IMP_BMIPS3300_BUG:
1752 c->cputype = CPU_BMIPS3300;
1753 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 1754 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 1755 break;
1756 case PRID_IMP_BMIPS43XX: {
8ff374b9 1757 int rev = c->processor_id & PRID_REV_MASK;
602977b0
KC		 1758
1759 if (rev >= PRID_REV_BMIPS4380_LO &&
1760 rev <= PRID_REV_BMIPS4380_HI) {
1761 c->cputype = CPU_BMIPS4380;
1762 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 1763 set_elf_platform(cpu, "bmips4380");
b4720809 1764 c->options |= MIPS_CPU_RIXI;
602977b0
KC		 1765 } else {
1766 c->cputype = CPU_BMIPS4350;
1767 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 1768 set_elf_platform(cpu, "bmips4350");
602977b0 1769 }
0de663ef 1770 break;
602977b0
KC		 1771 }
1772 case PRID_IMP_BMIPS5000:
68e6a783 1773 case PRID_IMP_BMIPS5200:
602977b0 1774 c->cputype = CPU_BMIPS5000;
37808d62
FF		 1775 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1776 __cpu_name[cpu] = "Broadcom BMIPS5200";
1777 else
1778 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 1779 set_elf_platform(cpu, "bmips5000");
b4720809 1780 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
0de663ef 1781 break;
1c0c13eb
AJ		 1782 }
1783}
1784
0dd4781b
DD		 1785static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1786{
1787 decode_configs(c);
8ff374b9 1788 switch (c->processor_id & PRID_IMP_MASK) {
0dd4781b
DD		 1789 case PRID_IMP_CAVIUM_CN38XX:
1790 case PRID_IMP_CAVIUM_CN31XX:
1791 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 1792 c->cputype = CPU_CAVIUM_OCTEON;
1793 __cpu_name[cpu] = "Cavium Octeon";
1794 goto platform;
0dd4781b
DD		 1795 case PRID_IMP_CAVIUM_CN58XX:
1796 case PRID_IMP_CAVIUM_CN56XX:
1797 case PRID_IMP_CAVIUM_CN50XX:
1798 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 1799 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1800 __cpu_name[cpu] = "Cavium Octeon+";
1801platform:
c094c99e 1802 set_elf_platform(cpu, "octeon");
0dd4781b 1803 break;
a1431b61 1804 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 1805 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 1806 case PRID_IMP_CAVIUM_CN66XX:
1807 case PRID_IMP_CAVIUM_CN68XX:
af04bb85 1808 case PRID_IMP_CAVIUM_CNF71XX:
0e56b385
DD		 1809 c->cputype = CPU_CAVIUM_OCTEON2;
1810 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 1811 set_elf_platform(cpu, "octeon2");
0e56b385 1812 break;
af04bb85 1813 case PRID_IMP_CAVIUM_CN70XX:
b8c8f665
DD		 1814 case PRID_IMP_CAVIUM_CN73XX:
1815 case PRID_IMP_CAVIUM_CNF75XX:
af04bb85
DD		 1816 case PRID_IMP_CAVIUM_CN78XX:
1817 c->cputype = CPU_CAVIUM_OCTEON3;
1818 __cpu_name[cpu] = "Cavium Octeon III";
1819 set_elf_platform(cpu, "octeon3");
1820 break;
0dd4781b
DD		 1821 default:
1822 printk(KERN_INFO "Unknown Octeon chip!\n");
1823 c->cputype = CPU_UNKNOWN;
1824 break;
1825 }
1826}
1827
b2edcfc8
HC		 1828static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
1829{
1830 switch (c->processor_id & PRID_IMP_MASK) {
1831 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1832 switch (c->processor_id & PRID_REV_MASK) {
1833 case PRID_REV_LOONGSON3A_R2:
1834 c->cputype = CPU_LOONGSON3;
1835 __cpu_name[cpu] = "ICT Loongson-3";
1836 set_elf_platform(cpu, "loongson3a");
1837 set_isa(c, MIPS_CPU_ISA_M64R2);
1838 break;
1839 }
1840
1841 decode_configs(c);
033cffee 1842 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
b2edcfc8
HC		 1843 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1844 break;
1845 default:
1846 panic("Unknown Loongson Processor ID!");
1847 break;
1848 }
1849}
1850
83ccf69d
LPC		 1851static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1852{
1853 decode_configs(c);
1854 /* JZRISC does not implement the CP0 counter. */
1855 c->options &= ~MIPS_CPU_COUNTER;
06947aaa 1856 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
8ff374b9 1857 switch (c->processor_id & PRID_IMP_MASK) {
83ccf69d
LPC		 1858 case PRID_IMP_JZRISC:
1859 c->cputype = CPU_JZRISC;
4f12b91d 1860 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
83ccf69d
LPC		 1861 __cpu_name[cpu] = "Ingenic JZRISC";
1862 break;
1863 default:
1864 panic("Unknown Ingenic Processor ID!");
1865 break;
1866 }
1867}
1868
a7117c6b
J		 1869static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1870{
1871 decode_configs(c);
1872
8ff374b9 1873 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
809f36c6
ML		 1874 c->cputype = CPU_ALCHEMY;
1875 __cpu_name[cpu] = "Au1300";
1876 /* following stuff is not for Alchemy */
1877 return;
1878 }
1879
70342287
RB		 1880 c->options = (MIPS_CPU_TLB |
1881 MIPS_CPU_4KEX |
a7117c6b 1882 MIPS_CPU_COUNTER |
70342287
RB		 1883 MIPS_CPU_DIVEC |
1884 MIPS_CPU_WATCH |
1885 MIPS_CPU_EJTAG |
a7117c6b
J		 1886 MIPS_CPU_LLSC);
1887
8ff374b9 1888 switch (c->processor_id & PRID_IMP_MASK) {
4ca86a2f 1889 case PRID_IMP_NETLOGIC_XLP2XX:
8907c55e 1890 case PRID_IMP_NETLOGIC_XLP9XX:
1c983986 1891 case PRID_IMP_NETLOGIC_XLP5XX:
4ca86a2f
J		 1892 c->cputype = CPU_XLP;
1893 __cpu_name[cpu] = "Broadcom XLPII";
1894 break;
1895
2aa54b20
J		 1896 case PRID_IMP_NETLOGIC_XLP8XX:
1897 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 1898 c->cputype = CPU_XLP;
1899 __cpu_name[cpu] = "Netlogic XLP";
1900 break;
1901
a7117c6b
J		 1902 case PRID_IMP_NETLOGIC_XLR732:
1903 case PRID_IMP_NETLOGIC_XLR716:
1904 case PRID_IMP_NETLOGIC_XLR532:
1905 case PRID_IMP_NETLOGIC_XLR308:
1906 case PRID_IMP_NETLOGIC_XLR532C:
1907 case PRID_IMP_NETLOGIC_XLR516C:
1908 case PRID_IMP_NETLOGIC_XLR508C:
1909 case PRID_IMP_NETLOGIC_XLR308C:
1910 c->cputype = CPU_XLR;
1911 __cpu_name[cpu] = "Netlogic XLR";
1912 break;
1913
1914 case PRID_IMP_NETLOGIC_XLS608:
1915 case PRID_IMP_NETLOGIC_XLS408:
1916 case PRID_IMP_NETLOGIC_XLS404:
1917 case PRID_IMP_NETLOGIC_XLS208:
1918 case PRID_IMP_NETLOGIC_XLS204:
1919 case PRID_IMP_NETLOGIC_XLS108:
1920 case PRID_IMP_NETLOGIC_XLS104:
1921 case PRID_IMP_NETLOGIC_XLS616B:
1922 case PRID_IMP_NETLOGIC_XLS608B:
1923 case PRID_IMP_NETLOGIC_XLS416B:
1924 case PRID_IMP_NETLOGIC_XLS412B:
1925 case PRID_IMP_NETLOGIC_XLS408B:
1926 case PRID_IMP_NETLOGIC_XLS404B:
1927 c->cputype = CPU_XLR;
1928 __cpu_name[cpu] = "Netlogic XLS";
1929 break;
1930
1931 default:
a3d4fb2d 1932 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 1933 c->processor_id);
1934 c->cputype = CPU_XLR;
1935 break;
1936 }
1937
a3d4fb2d 1938 if (c->cputype == CPU_XLP) {
a96102be 1939 set_isa(c, MIPS_CPU_ISA_M64R2);
a3d4fb2d
J		 1940 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1941 /* This will be updated again after all threads are woken up */
1942 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1943 } else {
a96102be 1944 set_isa(c, MIPS_CPU_ISA_M64R1);
a3d4fb2d
J		 1945 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1946 }
7777b939 1947 c->kscratch_mask = 0xf;
a7117c6b
J		 1948}
1949
949e51be
DD		 1950#ifdef CONFIG_64BIT
1951/* For use by uaccess.h */
1952u64 __ua_limit;
1953EXPORT_SYMBOL(__ua_limit);
1954#endif
1955
9966db25 1956const char *__cpu_name[NR_CPUS];
874fd3b5 1957const char *__elf_platform;
9966db25 1958
078a55fc 1959void cpu_probe(void)
1da177e4
LT		 1960{
1961 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 1962 unsigned int cpu = smp_processor_id();
1da177e4 1963
05510f2b
MN		 1964 /*
1965 * Set a default elf platform, cpu probe may later
1966 * overwrite it with a more precise value
1967 */
1968 set_elf_platform(cpu, "mips");
1969
70342287 1970 c->processor_id = PRID_IMP_UNKNOWN;
1da177e4
LT		 1971 c->fpu_id = FPIR_IMP_NONE;
1972 c->cputype = CPU_UNKNOWN;
4f12b91d 1973 c->writecombine = _CACHE_UNCACHED;
1da177e4 1974
9b26616c
MR		 1975 c->fpu_csr31 = FPU_CSR_RN;
1976 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1977
1da177e4 1978 c->processor_id = read_c0_prid();
8ff374b9 1979 switch (c->processor_id & PRID_COMP_MASK) {
1da177e4 1980 case PRID_COMP_LEGACY:
cea7e2df 1981 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1982 break;
1983 case PRID_COMP_MIPS:
cea7e2df 1984 cpu_probe_mips(c, cpu);
1da177e4
LT		 1985 break;
1986 case PRID_COMP_ALCHEMY:
cea7e2df 1987 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1988 break;
1989 case PRID_COMP_SIBYTE:
cea7e2df 1990 cpu_probe_sibyte(c, cpu);
1da177e4 1991 break;
1c0c13eb 1992 case PRID_COMP_BROADCOM:
cea7e2df 1993 cpu_probe_broadcom(c, cpu);
1c0c13eb 1994 break;
1da177e4 1995 case PRID_COMP_SANDCRAFT:
cea7e2df 1996 cpu_probe_sandcraft(c, cpu);
1da177e4 1997 break;
a92b0588 1998 case PRID_COMP_NXP:
cea7e2df 1999 cpu_probe_nxp(c, cpu);
a3dddd56 2000 break;
0dd4781b
DD		 2001 case PRID_COMP_CAVIUM:
2002 cpu_probe_cavium(c, cpu);
2003 break;
b2edcfc8
HC		 2004 case PRID_COMP_LOONGSON:
2005 cpu_probe_loongson(c, cpu);
2006 break;
252617a4
PB		 2007 case PRID_COMP_INGENIC_D0:
2008 case PRID_COMP_INGENIC_D1:
2009 case PRID_COMP_INGENIC_E1:
83ccf69d
LPC		 2010 cpu_probe_ingenic(c, cpu);
2011 break;
a7117c6b
J		 2012 case PRID_COMP_NETLOGIC:
2013 cpu_probe_netlogic(c, cpu);
2014 break;
1da177e4 2015 }
dec8b1ca 2016
cea7e2df
RB		 2017 BUG_ON(!__cpu_name[cpu]);
2018 BUG_ON(c->cputype == CPU_UNKNOWN);
2019
dec8b1ca
FBH		 2020 /*
2021 * Platform code can force the cpu type to optimize code
2022 * generation. In that case be sure the cpu type is correctly
2023 * manually setup otherwise it could trigger some nasty bugs.
2024 */
2025 BUG_ON(current_cpu_type() != c->cputype);
2026
2e274768
FF		 2027 if (cpu_has_rixi) {
2028 /* Enable the RIXI exceptions */
2029 set_c0_pagegrain(PG_IEC);
2030 back_to_back_c0_hazard();
2031 /* Verify the IEC bit is set */
2032 if (read_c0_pagegrain() & PG_IEC)
2033 c->options |= MIPS_CPU_RIXIEX;
2034 }
2035
0103d23f
KC		 2036 if (mips_fpu_disabled)
2037 c->options &= ~MIPS_CPU_FPU;
2038
2039 if (mips_dsp_disabled)
ee80f7c7 2040 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f 2041
3d528b32
MC		 2042 if (mips_htw_disabled) {
2043 c->options &= ~MIPS_CPU_HTW;
2044 write_c0_pwctl(read_c0_pwctl() &
2045 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
2046 }
2047
7aecd5ca
MR		 2048 if (c->options & MIPS_CPU_FPU)
2049 cpu_set_fpu_opts(c);
2050 else
2051 cpu_set_nofpu_opts(c);
9966db25 2052
8d5ded16
JK		 2053 if (cpu_has_bp_ghist)
2054 write_c0_r10k_diag(read_c0_r10k_diag() |
2055 R10K_DIAG_E_GHIST);
2056
8b8aa636 2057 if (cpu_has_mips_r2_r6) {
f6771dbb 2058 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
da4b62cd
AC		 2059 /* R2 has Performance Counter Interrupt indicator */
2060 c->options |= MIPS_CPU_PCI;
2061 }
f6771dbb
RB		 2062 else
2063 c->srsets = 1;
91dfc423 2064
4c063034
PB		 2065 if (cpu_has_mips_r6)
2066 elf_hwcap |= HWCAP_MIPS_R6;
2067
a8ad1367 2068 if (cpu_has_msa) {
a5e9a69e 2069 c->msa_id = cpu_get_msa_id();
a8ad1367
PB		 2070 WARN(c->msa_id & MSA_IR_WRPF,
2071 "Vector register partitioning unimplemented!");
3cc9fa7f 2072 elf_hwcap |= HWCAP_MIPS_MSA;
a8ad1367 2073 }
a5e9a69e 2074
6ad816e7
JH		 2075 if (cpu_has_vz)
2076 cpu_probe_vz(c);
2077
91dfc423 2078 cpu_probe_vmbits(c);
949e51be
DD		 2079
2080#ifdef CONFIG_64BIT
2081 if (cpu == 0)
2082 __ua_limit = ~((1ull << cpu_vmbits) - 1);
2083#endif
1da177e4
LT		 2084}
2085
078a55fc 2086void cpu_report(void)
1da177e4
LT		 2087{
2088 struct cpuinfo_mips *c = &current_cpu_data;
2089
d9f897c9
LY		 2090 pr_info("CPU%d revision is: %08x (%s)\n",
2091 smp_processor_id(), c->processor_id, cpu_name_string());
1da177e4 2092 if (c->options & MIPS_CPU_FPU)
9966db25 2093 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
a5e9a69e
PB		 2094 if (cpu_has_msa)
2095 pr_info("MSA revision is: %08x\n", c->msa_id);
1da177e4 2096}
Linux 6.x block layer and io_uring tree(s)