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MIPS: detect presence of the FRE & UFR bits
[linux-2.6-block.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
70342287 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4 22#include <asm/cpu.h>
69f24d17 23#include <asm/cpu-type.h>
1da177e4
LT		 24#include <asm/fpu.h>
25#include <asm/mipsregs.h>
30ee615b 26#include <asm/mipsmtregs.h>
a5e9a69e 27#include <asm/msa.h>
654f57bf 28#include <asm/watch.h>
06372a63 29#include <asm/elf.h>
4f12b91d 30#include <asm/pgtable-bits.h>
a074f0e8 31#include <asm/spram.h>
949e51be
DD		 32#include <asm/uaccess.h>
33
078a55fc 34static int mips_fpu_disabled;
0103d23f
KC		 35
36static int __init fpu_disable(char *s)
37{
38 cpu_data[0].options &= ~MIPS_CPU_FPU;
39 mips_fpu_disabled = 1;
40
41 return 1;
42}
43
44__setup("nofpu", fpu_disable);
45
078a55fc 46int mips_dsp_disabled;
0103d23f
KC		 47
48static int __init dsp_disable(char *s)
49{
ee80f7c7 50 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f
KC		 51 mips_dsp_disabled = 1;
52
53 return 1;
54}
55
56__setup("nodsp", dsp_disable);
57
3d528b32
MC		 58static int mips_htw_disabled;
59
60static int __init htw_disable(char *s)
61{
62 mips_htw_disabled = 1;
63 cpu_data[0].options &= ~MIPS_CPU_HTW;
64 write_c0_pwctl(read_c0_pwctl() &
65 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
66
67 return 1;
68}
69
70__setup("nohtw", htw_disable);
71
97f4ad29
MC		 72static int mips_ftlb_disabled;
73static int mips_has_ftlb_configured;
74
75static void set_ftlb_enable(struct cpuinfo_mips *c, int enable);
76
77static int __init ftlb_disable(char *s)
78{
79 unsigned int config4, mmuextdef;
80
81 /*
82 * If the core hasn't done any FTLB configuration, there is nothing
83 * for us to do here.
84 */
85 if (!mips_has_ftlb_configured)
86 return 1;
87
88 /* Disable it in the boot cpu */
89 set_ftlb_enable(&cpu_data[0], 0);
90
91 back_to_back_c0_hazard();
92
93 config4 = read_c0_config4();
94
95 /* Check that FTLB has been disabled */
96 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
97 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
98 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
99 /* This should never happen */
100 pr_warn("FTLB could not be disabled!\n");
101 return 1;
102 }
103
104 mips_ftlb_disabled = 1;
105 mips_has_ftlb_configured = 0;
106
107 /*
108 * noftlb is mainly used for debug purposes so print
109 * an informative message instead of using pr_debug()
110 */
111 pr_info("FTLB has been disabled\n");
112
113 /*
114 * Some of these bits are duplicated in the decode_config4.
115 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
116 * once FTLB has been disabled so undo what decode_config4 did.
117 */
118 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
119 cpu_data[0].tlbsizeftlbsets;
120 cpu_data[0].tlbsizeftlbsets = 0;
121 cpu_data[0].tlbsizeftlbways = 0;
122
123 return 1;
124}
125
126__setup("noftlb", ftlb_disable);
127
128
9267a30d
MSJ		 129static inline void check_errata(void)
130{
131 struct cpuinfo_mips *c = &current_cpu_data;
132
69f24d17 133 switch (current_cpu_type()) {
9267a30d
MSJ		 134 case CPU_34K:
135 /*
136 * Erratum "RPS May Cause Incorrect Instruction Execution"
b633648c 137 * This code only handles VPE0, any SMP/RTOS code
9267a30d
MSJ		 138 * making use of VPE1 will be responsable for that VPE.
139 */
140 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
141 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
142 break;
143 default:
144 break;
145 }
146}
147
1da177e4
LT		 148void __init check_bugs32(void)
149{
9267a30d 150 check_errata();
1da177e4
LT		 151}
152
153/*
154 * Probe whether cpu has config register by trying to play with
155 * alternate cache bit and see whether it matters.
156 * It's used by cpu_probe to distinguish between R3000A and R3081.
157 */
158static inline int cpu_has_confreg(void)
159{
160#ifdef CONFIG_CPU_R3000
161 extern unsigned long r3k_cache_size(unsigned long);
162 unsigned long size1, size2;
163 unsigned long cfg = read_c0_conf();
164
165 size1 = r3k_cache_size(ST0_ISC);
166 write_c0_conf(cfg ^ R30XX_CONF_AC);
167 size2 = r3k_cache_size(ST0_ISC);
168 write_c0_conf(cfg);
169 return size1 != size2;
170#else
171 return 0;
172#endif
173}
174
c094c99e
RM		 175static inline void set_elf_platform(int cpu, const char *plat)
176{
177 if (cpu == 0)
178 __elf_platform = plat;
179}
180
1da177e4
LT		 181/*
182 * Get the FPU Implementation/Revision.
183 */
184static inline unsigned long cpu_get_fpu_id(void)
185{
186 unsigned long tmp, fpu_id;
187
188 tmp = read_c0_status();
597ce172 189 __enable_fpu(FPU_AS_IS);
1da177e4
LT		 190 fpu_id = read_32bit_cp1_register(CP1_REVISION);
191 write_c0_status(tmp);
192 return fpu_id;
193}
194
195/*
196 * Check the CPU has an FPU the official way.
197 */
198static inline int __cpu_has_fpu(void)
199{
635c9907 200 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
1da177e4
LT		 201}
202
a5e9a69e
PB		 203static inline unsigned long cpu_get_msa_id(void)
204{
3587ea88 205 unsigned long status, msa_id;
a5e9a69e
PB		 206
207 status = read_c0_status();
208 __enable_fpu(FPU_64BIT);
a5e9a69e
PB		 209 enable_msa();
210 msa_id = read_msa_ir();
3587ea88 211 disable_msa();
a5e9a69e
PB		 212 write_c0_status(status);
213 return msa_id;
214}
215
91dfc423
GR		 216static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
217{
218#ifdef __NEED_VMBITS_PROBE
5b7efa89 219 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 220 back_to_back_c0_hazard();
5b7efa89 221 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 222#endif
223}
224
078a55fc 225static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
a96102be
SH		 226{
227 switch (isa) {
228 case MIPS_CPU_ISA_M64R2:
229 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
230 case MIPS_CPU_ISA_M64R1:
231 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
232 case MIPS_CPU_ISA_V:
233 c->isa_level |= MIPS_CPU_ISA_V;
234 case MIPS_CPU_ISA_IV:
235 c->isa_level |= MIPS_CPU_ISA_IV;
236 case MIPS_CPU_ISA_III:
1990e542 237 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
a96102be
SH		 238 break;
239
240 case MIPS_CPU_ISA_M32R2:
241 c->isa_level |= MIPS_CPU_ISA_M32R2;
242 case MIPS_CPU_ISA_M32R1:
243 c->isa_level |= MIPS_CPU_ISA_M32R1;
244 case MIPS_CPU_ISA_II:
245 c->isa_level |= MIPS_CPU_ISA_II;
a96102be
SH		 246 break;
247 }
248}
249
078a55fc 250static char unknown_isa[] = KERN_ERR \
2fa36399
KC		 251 "Unsupported ISA type, c0.config0: %d.";
252
75b5b5e0
LY		 253static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
254{
255 unsigned int config6;
d83b0e82
JH		 256
257 /* It's implementation dependent how the FTLB can be enabled */
258 switch (c->cputype) {
259 case CPU_PROAPTIV:
260 case CPU_P5600:
261 /* proAptiv & related cores use Config6 to enable the FTLB */
75b5b5e0
LY		 262 config6 = read_c0_config6();
263 if (enable)
264 /* Enable FTLB */
265 write_c0_config6(config6 | MIPS_CONF6_FTLBEN);
266 else
267 /* Disable FTLB */
268 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
269 back_to_back_c0_hazard();
d83b0e82 270 break;
75b5b5e0
LY		 271 }
272}
273
2fa36399
KC		 274static inline unsigned int decode_config0(struct cpuinfo_mips *c)
275{
276 unsigned int config0;
277 int isa;
278
279 config0 = read_c0_config();
280
75b5b5e0
LY		 281 /*
282 * Look for Standard TLB or Dual VTLB and FTLB
283 */
284 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
285 (((config0 & MIPS_CONF_MT) >> 7) == 4))
2fa36399 286 c->options |= MIPS_CPU_TLB;
75b5b5e0 287
2fa36399
KC		 288 isa = (config0 & MIPS_CONF_AT) >> 13;
289 switch (isa) {
290 case 0:
291 switch ((config0 & MIPS_CONF_AR) >> 10) {
292 case 0:
a96102be 293 set_isa(c, MIPS_CPU_ISA_M32R1);
2fa36399
KC		 294 break;
295 case 1:
a96102be 296 set_isa(c, MIPS_CPU_ISA_M32R2);
2fa36399
KC		 297 break;
298 default:
299 goto unknown;
300 }
301 break;
302 case 2:
303 switch ((config0 & MIPS_CONF_AR) >> 10) {
304 case 0:
a96102be 305 set_isa(c, MIPS_CPU_ISA_M64R1);
2fa36399
KC		 306 break;
307 case 1:
a96102be 308 set_isa(c, MIPS_CPU_ISA_M64R2);
2fa36399
KC		 309 break;
310 default:
311 goto unknown;
312 }
313 break;
314 default:
315 goto unknown;
316 }
317
318 return config0 & MIPS_CONF_M;
319
320unknown:
321 panic(unknown_isa, config0);
322}
323
324static inline unsigned int decode_config1(struct cpuinfo_mips *c)
325{
326 unsigned int config1;
327
328 config1 = read_c0_config1();
329
330 if (config1 & MIPS_CONF1_MD)
331 c->ases |= MIPS_ASE_MDMX;
332 if (config1 & MIPS_CONF1_WR)
333 c->options |= MIPS_CPU_WATCH;
334 if (config1 & MIPS_CONF1_CA)
335 c->ases |= MIPS_ASE_MIPS16;
336 if (config1 & MIPS_CONF1_EP)
337 c->options |= MIPS_CPU_EJTAG;
338 if (config1 & MIPS_CONF1_FP) {
339 c->options |= MIPS_CPU_FPU;
340 c->options |= MIPS_CPU_32FPR;
341 }
75b5b5e0 342 if (cpu_has_tlb) {
2fa36399 343 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
75b5b5e0
LY		 344 c->tlbsizevtlb = c->tlbsize;
345 c->tlbsizeftlbsets = 0;
346 }
2fa36399
KC		 347
348 return config1 & MIPS_CONF_M;
349}
350
351static inline unsigned int decode_config2(struct cpuinfo_mips *c)
352{
353 unsigned int config2;
354
355 config2 = read_c0_config2();
356
357 if (config2 & MIPS_CONF2_SL)
358 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
359
360 return config2 & MIPS_CONF_M;
361}
362
363static inline unsigned int decode_config3(struct cpuinfo_mips *c)
364{
365 unsigned int config3;
366
367 config3 = read_c0_config3();
368
b2ab4f08 369 if (config3 & MIPS_CONF3_SM) {
2fa36399 370 c->ases |= MIPS_ASE_SMARTMIPS;
b2ab4f08
SH		 371 c->options |= MIPS_CPU_RIXI;
372 }
373 if (config3 & MIPS_CONF3_RXI)
374 c->options |= MIPS_CPU_RIXI;
2fa36399
KC		 375 if (config3 & MIPS_CONF3_DSP)
376 c->ases |= MIPS_ASE_DSP;
ee80f7c7
SH		 377 if (config3 & MIPS_CONF3_DSP2P)
378 c->ases |= MIPS_ASE_DSP2P;
2fa36399
KC		 379 if (config3 & MIPS_CONF3_VINT)
380 c->options |= MIPS_CPU_VINT;
381 if (config3 & MIPS_CONF3_VEIC)
382 c->options |= MIPS_CPU_VEIC;
383 if (config3 & MIPS_CONF3_MT)
384 c->ases |= MIPS_ASE_MIPSMT;
385 if (config3 & MIPS_CONF3_ULRI)
386 c->options |= MIPS_CPU_ULRI;
f8fa4811
SH		 387 if (config3 & MIPS_CONF3_ISA)
388 c->options |= MIPS_CPU_MICROMIPS;
1e7decdb
DD		 389 if (config3 & MIPS_CONF3_VZ)
390 c->ases |= MIPS_ASE_VZ;
4a0156fb
SH		 391 if (config3 & MIPS_CONF3_SC)
392 c->options |= MIPS_CPU_SEGMENTS;
a5e9a69e
PB		 393 if (config3 & MIPS_CONF3_MSA)
394 c->ases |= MIPS_ASE_MSA;
3d528b32
MC		 395 /* Only tested on 32-bit cores */
396 if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT))
397 c->options |= MIPS_CPU_HTW;
2fa36399
KC		 398
399 return config3 & MIPS_CONF_M;
400}
401
402static inline unsigned int decode_config4(struct cpuinfo_mips *c)
403{
404 unsigned int config4;
75b5b5e0
LY		 405 unsigned int newcf4;
406 unsigned int mmuextdef;
407 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
2fa36399
KC		 408
409 config4 = read_c0_config4();
410
1745c1ef
LY		 411 if (cpu_has_tlb) {
412 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
413 c->options |= MIPS_CPU_TLBINV;
75b5b5e0
LY		 414 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
415 switch (mmuextdef) {
416 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
417 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
418 c->tlbsizevtlb = c->tlbsize;
419 break;
420 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
421 c->tlbsizevtlb +=
422 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
423 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
424 c->tlbsize = c->tlbsizevtlb;
425 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
426 /* fall through */
427 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
97f4ad29
MC		 428 if (mips_ftlb_disabled)
429 break;
75b5b5e0
LY		 430 newcf4 = (config4 & ~ftlb_page) |
431 (page_size_ftlb(mmuextdef) <<
432 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
433 write_c0_config4(newcf4);
434 back_to_back_c0_hazard();
435 config4 = read_c0_config4();
436 if (config4 != newcf4) {
437 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
438 PAGE_SIZE, config4);
439 /* Switch FTLB off */
440 set_ftlb_enable(c, 0);
441 break;
442 }
443 c->tlbsizeftlbsets = 1 <<
444 ((config4 & MIPS_CONF4_FTLBSETS) >>
445 MIPS_CONF4_FTLBSETS_SHIFT);
446 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
447 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
448 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
97f4ad29 449 mips_has_ftlb_configured = 1;
75b5b5e0
LY		 450 break;
451 }
1745c1ef
LY		 452 }
453
2fa36399
KC		 454 c->kscratch_mask = (config4 >> 16) & 0xff;
455
456 return config4 & MIPS_CONF_M;
457}
458
8b8a7634
RB		 459static inline unsigned int decode_config5(struct cpuinfo_mips *c)
460{
461 unsigned int config5;
462
463 config5 = read_c0_config5();
464 config5 &= ~MIPS_CONF5_UFR;
465 write_c0_config5(config5);
466
49016748
MC		 467 if (config5 & MIPS_CONF5_EVA)
468 c->options |= MIPS_CPU_EVA;
1f6c52ff
PB		 469 if (config5 & MIPS_CONF5_MRP)
470 c->options |= MIPS_CPU_MAAR;
49016748 471
8b8a7634
RB		 472 return config5 & MIPS_CONF_M;
473}
474
078a55fc 475static void decode_configs(struct cpuinfo_mips *c)
2fa36399
KC		 476{
477 int ok;
478
479 /* MIPS32 or MIPS64 compliant CPU. */
480 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
481 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
482
483 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
484
97f4ad29
MC		 485 /* Enable FTLB if present and not disabled */
486 set_ftlb_enable(c, !mips_ftlb_disabled);
75b5b5e0 487
2fa36399 488 ok = decode_config0(c); /* Read Config registers. */
70342287 489 BUG_ON(!ok); /* Arch spec violation! */
2fa36399
KC		 490 if (ok)
491 ok = decode_config1(c);
492 if (ok)
493 ok = decode_config2(c);
494 if (ok)
495 ok = decode_config3(c);
496 if (ok)
497 ok = decode_config4(c);
8b8a7634
RB		 498 if (ok)
499 ok = decode_config5(c);
2fa36399
KC		 500
501 mips_probe_watch_registers(c);
502
6575b1d4
LY		 503 if (cpu_has_rixi) {
504 /* Enable the RIXI exceptions */
505 write_c0_pagegrain(read_c0_pagegrain() | PG_IEC);
506 back_to_back_c0_hazard();
507 /* Verify the IEC bit is set */
508 if (read_c0_pagegrain() & PG_IEC)
509 c->options |= MIPS_CPU_RIXIEX;
510 }
511
0ee958e1 512#ifndef CONFIG_MIPS_CPS
30ee615b 513 if (cpu_has_mips_r2) {
45b585c8 514 c->core = get_ebase_cpunum();
30ee615b
PB		 515 if (cpu_has_mipsmt)
516 c->core >>= fls(core_nvpes()) - 1;
517 }
0ee958e1 518#endif
2fa36399
KC		 519}
520
02cf2119 521#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 522 | MIPS_CPU_COUNTER)
523
cea7e2df 524static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 525{
8ff374b9 526 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 527 case PRID_IMP_R2000:
528 c->cputype = CPU_R2000;
cea7e2df 529 __cpu_name[cpu] = "R2000";
02cf2119 530 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 531 MIPS_CPU_NOFPUEX;
1da177e4
LT		 532 if (__cpu_has_fpu())
533 c->options |= MIPS_CPU_FPU;
534 c->tlbsize = 64;
535 break;
536 case PRID_IMP_R3000:
8ff374b9 537 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
cea7e2df 538 if (cpu_has_confreg()) {
1da177e4 539 c->cputype = CPU_R3081E;
cea7e2df
RB		 540 __cpu_name[cpu] = "R3081";
541 } else {
1da177e4 542 c->cputype = CPU_R3000A;
cea7e2df
RB		 543 __cpu_name[cpu] = "R3000A";
544 }
cea7e2df 545 } else {
1da177e4 546 c->cputype = CPU_R3000;
cea7e2df
RB		 547 __cpu_name[cpu] = "R3000";
548 }
02cf2119 549 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 550 MIPS_CPU_NOFPUEX;
1da177e4
LT		 551 if (__cpu_has_fpu())
552 c->options |= MIPS_CPU_FPU;
553 c->tlbsize = 64;
554 break;
555 case PRID_IMP_R4000:
556 if (read_c0_config() & CONF_SC) {
8ff374b9
MR		 557 if ((c->processor_id & PRID_REV_MASK) >=
558 PRID_REV_R4400) {
1da177e4 559 c->cputype = CPU_R4400PC;
cea7e2df
RB		 560 __cpu_name[cpu] = "R4400PC";
561 } else {
1da177e4 562 c->cputype = CPU_R4000PC;
cea7e2df
RB		 563 __cpu_name[cpu] = "R4000PC";
564 }
1da177e4 565 } else {
7f177a52
MR		 566 int cca = read_c0_config() & CONF_CM_CMASK;
567 int mc;
568
569 /*
570 * SC and MC versions can't be reliably told apart,
571 * but only the latter support coherent caching
572 * modes so assume the firmware has set the KSEG0
573 * coherency attribute reasonably (if uncached, we
574 * assume SC).
575 */
576 switch (cca) {
577 case CONF_CM_CACHABLE_CE:
578 case CONF_CM_CACHABLE_COW:
579 case CONF_CM_CACHABLE_CUW:
580 mc = 1;
581 break;
582 default:
583 mc = 0;
584 break;
585 }
8ff374b9
MR		 586 if ((c->processor_id & PRID_REV_MASK) >=
587 PRID_REV_R4400) {
7f177a52
MR		 588 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
589 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
cea7e2df 590 } else {
7f177a52
MR		 591 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
592 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
cea7e2df 593 }
1da177e4
LT		 594 }
595
a96102be 596 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 597 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 598 MIPS_CPU_WATCH | MIPS_CPU_VCE |
599 MIPS_CPU_LLSC;
1da177e4
LT		 600 c->tlbsize = 48;
601 break;
602 case PRID_IMP_VR41XX:
9f91e506
YY		 603 set_isa(c, MIPS_CPU_ISA_III);
604 c->options = R4K_OPTS;
605 c->tlbsize = 32;
1da177e4 606 switch (c->processor_id & 0xf0) {
1da177e4
LT		 607 case PRID_REV_VR4111:
608 c->cputype = CPU_VR4111;
cea7e2df 609 __cpu_name[cpu] = "NEC VR4111";
1da177e4 610 break;
1da177e4
LT		 611 case PRID_REV_VR4121:
612 c->cputype = CPU_VR4121;
cea7e2df 613 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 614 break;
615 case PRID_REV_VR4122:
cea7e2df 616 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 617 c->cputype = CPU_VR4122;
cea7e2df
RB		 618 __cpu_name[cpu] = "NEC VR4122";
619 } else {
1da177e4 620 c->cputype = CPU_VR4181A;
cea7e2df
RB		 621 __cpu_name[cpu] = "NEC VR4181A";
622 }
1da177e4
LT		 623 break;
624 case PRID_REV_VR4130:
cea7e2df 625 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 626 c->cputype = CPU_VR4131;
cea7e2df
RB		 627 __cpu_name[cpu] = "NEC VR4131";
628 } else {
1da177e4 629 c->cputype = CPU_VR4133;
9f91e506 630 c->options |= MIPS_CPU_LLSC;
cea7e2df
RB		 631 __cpu_name[cpu] = "NEC VR4133";
632 }
1da177e4
LT		 633 break;
634 default:
635 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
636 c->cputype = CPU_VR41XX;
cea7e2df 637 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 638 break;
639 }
1da177e4
LT		 640 break;
641 case PRID_IMP_R4300:
642 c->cputype = CPU_R4300;
cea7e2df 643 __cpu_name[cpu] = "R4300";
a96102be 644 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 645 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 646 MIPS_CPU_LLSC;
1da177e4
LT		 647 c->tlbsize = 32;
648 break;
649 case PRID_IMP_R4600:
650 c->cputype = CPU_R4600;
cea7e2df 651 __cpu_name[cpu] = "R4600";
a96102be 652 set_isa(c, MIPS_CPU_ISA_III);
075e7502
TS		 653 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
654 MIPS_CPU_LLSC;
1da177e4
LT		 655 c->tlbsize = 48;
656 break;
657 #if 0
03751e79 658 case PRID_IMP_R4650:
1da177e4
LT		 659 /*
660 * This processor doesn't have an MMU, so it's not
661 * "real easy" to run Linux on it. It is left purely
662 * for documentation. Commented out because it shares
663 * it's c0_prid id number with the TX3900.
664 */
a3dddd56 665 c->cputype = CPU_R4650;
cea7e2df 666 __cpu_name[cpu] = "R4650";
a96102be 667 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 668 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 669 c->tlbsize = 48;
1da177e4
LT		 670 break;
671 #endif
672 case PRID_IMP_TX39:
02cf2119 673 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 674
675 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
676 c->cputype = CPU_TX3927;
cea7e2df 677 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 678 c->tlbsize = 64;
679 } else {
8ff374b9 680 switch (c->processor_id & PRID_REV_MASK) {
1da177e4
LT		 681 case PRID_REV_TX3912:
682 c->cputype = CPU_TX3912;
cea7e2df 683 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 684 c->tlbsize = 32;
685 break;
686 case PRID_REV_TX3922:
687 c->cputype = CPU_TX3922;
cea7e2df 688 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 689 c->tlbsize = 64;
690 break;
1da177e4
LT		 691 }
692 }
693 break;
694 case PRID_IMP_R4700:
695 c->cputype = CPU_R4700;
cea7e2df 696 __cpu_name[cpu] = "R4700";
a96102be 697 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 698 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 699 MIPS_CPU_LLSC;
1da177e4
LT		 700 c->tlbsize = 48;
701 break;
702 case PRID_IMP_TX49:
703 c->cputype = CPU_TX49XX;
cea7e2df 704 __cpu_name[cpu] = "R49XX";
a96102be 705 set_isa(c, MIPS_CPU_ISA_III);
1da177e4
LT		 706 c->options = R4K_OPTS | MIPS_CPU_LLSC;
707 if (!(c->processor_id & 0x08))
708 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
709 c->tlbsize = 48;
710 break;
711 case PRID_IMP_R5000:
712 c->cputype = CPU_R5000;
cea7e2df 713 __cpu_name[cpu] = "R5000";
a96102be 714 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 715 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 716 MIPS_CPU_LLSC;
1da177e4
LT		 717 c->tlbsize = 48;
718 break;
719 case PRID_IMP_R5432:
720 c->cputype = CPU_R5432;
cea7e2df 721 __cpu_name[cpu] = "R5432";
a96102be 722 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 723 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 724 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 725 c->tlbsize = 48;
726 break;
727 case PRID_IMP_R5500:
728 c->cputype = CPU_R5500;
cea7e2df 729 __cpu_name[cpu] = "R5500";
a96102be 730 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 731 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 732 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 733 c->tlbsize = 48;
734 break;
735 case PRID_IMP_NEVADA:
736 c->cputype = CPU_NEVADA;
cea7e2df 737 __cpu_name[cpu] = "Nevada";
a96102be 738 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 739 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 740 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 741 c->tlbsize = 48;
742 break;
743 case PRID_IMP_R6000:
744 c->cputype = CPU_R6000;
cea7e2df 745 __cpu_name[cpu] = "R6000";
a96102be 746 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 747 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 748 MIPS_CPU_LLSC;
1da177e4
LT		 749 c->tlbsize = 32;
750 break;
751 case PRID_IMP_R6000A:
752 c->cputype = CPU_R6000A;
cea7e2df 753 __cpu_name[cpu] = "R6000A";
a96102be 754 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 755 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 756 MIPS_CPU_LLSC;
1da177e4
LT		 757 c->tlbsize = 32;
758 break;
759 case PRID_IMP_RM7000:
760 c->cputype = CPU_RM7000;
cea7e2df 761 __cpu_name[cpu] = "RM7000";
a96102be 762 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 763 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 764 MIPS_CPU_LLSC;
1da177e4 765 /*
70342287 766 * Undocumented RM7000: Bit 29 in the info register of
1da177e4
LT		 767 * the RM7000 v2.0 indicates if the TLB has 48 or 64
768 * entries.
769 *
70342287
RB		 770 * 29 1 => 64 entry JTLB
771 * 0 => 48 entry JTLB
1da177e4
LT		 772 */
773 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1da177e4
LT		 774 break;
775 case PRID_IMP_R8000:
776 c->cputype = CPU_R8000;
cea7e2df 777 __cpu_name[cpu] = "RM8000";
a96102be 778 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 779 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 780 MIPS_CPU_FPU | MIPS_CPU_32FPR |
781 MIPS_CPU_LLSC;
1da177e4
LT		 782 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
783 break;
784 case PRID_IMP_R10000:
785 c->cputype = CPU_R10000;
cea7e2df 786 __cpu_name[cpu] = "R10000";
a96102be 787 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 788 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 789 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 790 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 791 MIPS_CPU_LLSC;
1da177e4
LT		 792 c->tlbsize = 64;
793 break;
794 case PRID_IMP_R12000:
795 c->cputype = CPU_R12000;
cea7e2df 796 __cpu_name[cpu] = "R12000";
a96102be 797 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 798 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 799 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 800 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 801 MIPS_CPU_LLSC;
1da177e4
LT		 802 c->tlbsize = 64;
803 break;
44d921b2
K		 804 case PRID_IMP_R14000:
805 c->cputype = CPU_R14000;
cea7e2df 806 __cpu_name[cpu] = "R14000";
a96102be 807 set_isa(c, MIPS_CPU_ISA_IV);
44d921b2 808 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 809 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 810 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 811 MIPS_CPU_LLSC;
44d921b2
K		 812 c->tlbsize = 64;
813 break;
26859198 814 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
5aac1e8a
RM		 815 switch (c->processor_id & PRID_REV_MASK) {
816 case PRID_REV_LOONGSON2E:
c579d310
HC		 817 c->cputype = CPU_LOONGSON2;
818 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 819 set_elf_platform(cpu, "loongson2e");
7352c8b1 820 set_isa(c, MIPS_CPU_ISA_III);
5aac1e8a
RM		 821 break;
822 case PRID_REV_LOONGSON2F:
c579d310
HC		 823 c->cputype = CPU_LOONGSON2;
824 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 825 set_elf_platform(cpu, "loongson2f");
7352c8b1 826 set_isa(c, MIPS_CPU_ISA_III);
5aac1e8a 827 break;
c579d310
HC		 828 case PRID_REV_LOONGSON3A:
829 c->cputype = CPU_LOONGSON3;
830 __cpu_name[cpu] = "ICT Loongson-3";
831 set_elf_platform(cpu, "loongson3a");
7352c8b1 832 set_isa(c, MIPS_CPU_ISA_M64R1);
c579d310 833 break;
e7841be5
HC		 834 case PRID_REV_LOONGSON3B_R1:
835 case PRID_REV_LOONGSON3B_R2:
836 c->cputype = CPU_LOONGSON3;
837 __cpu_name[cpu] = "ICT Loongson-3";
838 set_elf_platform(cpu, "loongson3b");
7352c8b1 839 set_isa(c, MIPS_CPU_ISA_M64R1);
e7841be5 840 break;
5aac1e8a
RM		 841 }
842
2a21c730
FZ		 843 c->options = R4K_OPTS |
844 MIPS_CPU_FPU | MIPS_CPU_LLSC |
845 MIPS_CPU_32FPR;
846 c->tlbsize = 64;
cc94ea31 847 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2a21c730 848 break;
26859198 849 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
2fa36399 850 decode_configs(c);
b4672d37 851
2fa36399 852 c->cputype = CPU_LOONGSON1;
1da177e4 853
2fa36399
KC		 854 switch (c->processor_id & PRID_REV_MASK) {
855 case PRID_REV_LOONGSON1B:
856 __cpu_name[cpu] = "Loongson 1B";
b4672d37 857 break;
b4672d37 858 }
4194318c 859
2fa36399 860 break;
1da177e4 861 }
1da177e4
LT		 862}
863
cea7e2df 864static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 865{
4f12b91d 866 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 867 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 868 case PRID_IMP_4KC:
869 c->cputype = CPU_4KC;
4f12b91d 870 c->writecombine = _CACHE_UNCACHED;
cea7e2df 871 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 872 break;
873 case PRID_IMP_4KEC:
2b07bd02
RB		 874 case PRID_IMP_4KECR2:
875 c->cputype = CPU_4KEC;
4f12b91d 876 c->writecombine = _CACHE_UNCACHED;
cea7e2df 877 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 878 break;
1da177e4 879 case PRID_IMP_4KSC:
8afcb5d8 880 case PRID_IMP_4KSD:
1da177e4 881 c->cputype = CPU_4KSC;
4f12b91d 882 c->writecombine = _CACHE_UNCACHED;
cea7e2df 883 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 884 break;
885 case PRID_IMP_5KC:
886 c->cputype = CPU_5KC;
4f12b91d 887 c->writecombine = _CACHE_UNCACHED;
cea7e2df 888 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4 889 break;
78d4803f
LY		 890 case PRID_IMP_5KE:
891 c->cputype = CPU_5KE;
4f12b91d 892 c->writecombine = _CACHE_UNCACHED;
78d4803f
LY		 893 __cpu_name[cpu] = "MIPS 5KE";
894 break;
1da177e4
LT		 895 case PRID_IMP_20KC:
896 c->cputype = CPU_20KC;
4f12b91d 897 c->writecombine = _CACHE_UNCACHED;
cea7e2df 898 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 899 break;
900 case PRID_IMP_24K:
901 c->cputype = CPU_24K;
4f12b91d 902 c->writecombine = _CACHE_UNCACHED;
cea7e2df 903 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4 904 break;
42f3caef
JC		 905 case PRID_IMP_24KE:
906 c->cputype = CPU_24K;
4f12b91d 907 c->writecombine = _CACHE_UNCACHED;
42f3caef
JC		 908 __cpu_name[cpu] = "MIPS 24KEc";
909 break;
1da177e4
LT		 910 case PRID_IMP_25KF:
911 c->cputype = CPU_25KF;
4f12b91d 912 c->writecombine = _CACHE_UNCACHED;
cea7e2df 913 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 914 break;
bbc7f22f
RB		 915 case PRID_IMP_34K:
916 c->cputype = CPU_34K;
4f12b91d 917 c->writecombine = _CACHE_UNCACHED;
cea7e2df 918 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 919 break;
c620953c
CD		 920 case PRID_IMP_74K:
921 c->cputype = CPU_74K;
4f12b91d 922 c->writecombine = _CACHE_UNCACHED;
cea7e2df 923 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 924 break;
113c62d9
SH		 925 case PRID_IMP_M14KC:
926 c->cputype = CPU_M14KC;
4f12b91d 927 c->writecombine = _CACHE_UNCACHED;
113c62d9
SH		 928 __cpu_name[cpu] = "MIPS M14Kc";
929 break;
f8fa4811
SH		 930 case PRID_IMP_M14KEC:
931 c->cputype = CPU_M14KEC;
4f12b91d 932 c->writecombine = _CACHE_UNCACHED;
f8fa4811
SH		 933 __cpu_name[cpu] = "MIPS M14KEc";
934 break;
39b8d525
RB		 935 case PRID_IMP_1004K:
936 c->cputype = CPU_1004K;
4f12b91d 937 c->writecombine = _CACHE_UNCACHED;
cea7e2df 938 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 939 break;
006a851b 940 case PRID_IMP_1074K:
442e14a2 941 c->cputype = CPU_1074K;
4f12b91d 942 c->writecombine = _CACHE_UNCACHED;
006a851b
SH		 943 __cpu_name[cpu] = "MIPS 1074Kc";
944 break;
b5f065e7
LY		 945 case PRID_IMP_INTERAPTIV_UP:
946 c->cputype = CPU_INTERAPTIV;
947 __cpu_name[cpu] = "MIPS interAptiv";
948 break;
949 case PRID_IMP_INTERAPTIV_MP:
950 c->cputype = CPU_INTERAPTIV;
951 __cpu_name[cpu] = "MIPS interAptiv (multi)";
952 break;
b0d4d300
LY		 953 case PRID_IMP_PROAPTIV_UP:
954 c->cputype = CPU_PROAPTIV;
955 __cpu_name[cpu] = "MIPS proAptiv";
956 break;
957 case PRID_IMP_PROAPTIV_MP:
958 c->cputype = CPU_PROAPTIV;
959 __cpu_name[cpu] = "MIPS proAptiv (multi)";
960 break;
829dcc0a
JH		 961 case PRID_IMP_P5600:
962 c->cputype = CPU_P5600;
963 __cpu_name[cpu] = "MIPS P5600";
964 break;
9943ed92
LY		 965 case PRID_IMP_M5150:
966 c->cputype = CPU_M5150;
967 __cpu_name[cpu] = "MIPS M5150";
968 break;
1da177e4 969 }
0b6d497f 970
75b5b5e0
LY		 971 decode_configs(c);
972
0b6d497f 973 spram_config();
1da177e4
LT		 974}
975
cea7e2df 976static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 977{
4194318c 978 decode_configs(c);
8ff374b9 979 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 980 case PRID_IMP_AU1_REV1:
981 case PRID_IMP_AU1_REV2:
270717a8 982 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 983 switch ((c->processor_id >> 24) & 0xff) {
984 case 0:
cea7e2df 985 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 986 break;
987 case 1:
cea7e2df 988 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 989 break;
990 case 2:
cea7e2df 991 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 992 break;
993 case 3:
cea7e2df 994 __cpu_name[cpu] = "Au1550";
1da177e4 995 break;
e3ad1c23 996 case 4:
cea7e2df 997 __cpu_name[cpu] = "Au1200";
8ff374b9 998 if ((c->processor_id & PRID_REV_MASK) == 2)
cea7e2df 999 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 1000 break;
1001 case 5:
cea7e2df 1002 __cpu_name[cpu] = "Au1210";
e3ad1c23 1003 break;
1da177e4 1004 default:
270717a8 1005 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 1006 break;
1007 }
1da177e4
LT		 1008 break;
1009 }
1010}
1011
cea7e2df 1012static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1013{
4194318c 1014 decode_configs(c);
02cf2119 1015
4f12b91d 1016 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 1017 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1018 case PRID_IMP_SB1:
1019 c->cputype = CPU_SB1;
cea7e2df 1020 __cpu_name[cpu] = "SiByte SB1";
1da177e4 1021 /* FPU in pass1 is known to have issues. */
8ff374b9 1022 if ((c->processor_id & PRID_REV_MASK) < 0x02)
010b853b 1023 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 1024 break;
93ce2f52
AI		 1025 case PRID_IMP_SB1A:
1026 c->cputype = CPU_SB1A;
cea7e2df 1027 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 1028 break;
1da177e4
LT		 1029 }
1030}
1031
cea7e2df 1032static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1033{
4194318c 1034 decode_configs(c);
8ff374b9 1035 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1036 case PRID_IMP_SR71000:
1037 c->cputype = CPU_SR71000;
cea7e2df 1038 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 1039 c->scache.ways = 8;
1040 c->tlbsize = 64;
1041 break;
1042 }
1043}
1044
cea7e2df 1045static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 1046{
1047 decode_configs(c);
8ff374b9 1048 switch (c->processor_id & PRID_IMP_MASK) {
bdf21b18
PP		 1049 case PRID_IMP_PR4450:
1050 c->cputype = CPU_PR4450;
cea7e2df 1051 __cpu_name[cpu] = "Philips PR4450";
a96102be 1052 set_isa(c, MIPS_CPU_ISA_M32R1);
bdf21b18 1053 break;
bdf21b18
PP		 1054 }
1055}
1056
cea7e2df 1057static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 1058{
1059 decode_configs(c);
8ff374b9 1060 switch (c->processor_id & PRID_IMP_MASK) {
190fca3e
KC		 1061 case PRID_IMP_BMIPS32_REV4:
1062 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 1063 c->cputype = CPU_BMIPS32;
1064 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 1065 set_elf_platform(cpu, "bmips32");
602977b0
KC		 1066 break;
1067 case PRID_IMP_BMIPS3300:
1068 case PRID_IMP_BMIPS3300_ALT:
1069 case PRID_IMP_BMIPS3300_BUG:
1070 c->cputype = CPU_BMIPS3300;
1071 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 1072 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 1073 break;
1074 case PRID_IMP_BMIPS43XX: {
8ff374b9 1075 int rev = c->processor_id & PRID_REV_MASK;
602977b0
KC		 1076
1077 if (rev >= PRID_REV_BMIPS4380_LO &&
1078 rev <= PRID_REV_BMIPS4380_HI) {
1079 c->cputype = CPU_BMIPS4380;
1080 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 1081 set_elf_platform(cpu, "bmips4380");
602977b0
KC		 1082 } else {
1083 c->cputype = CPU_BMIPS4350;
1084 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 1085 set_elf_platform(cpu, "bmips4350");
602977b0 1086 }
0de663ef 1087 break;
602977b0
KC		 1088 }
1089 case PRID_IMP_BMIPS5000:
1090 c->cputype = CPU_BMIPS5000;
1091 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 1092 set_elf_platform(cpu, "bmips5000");
602977b0 1093 c->options |= MIPS_CPU_ULRI;
0de663ef 1094 break;
1c0c13eb
AJ		 1095 }
1096}
1097
0dd4781b
DD		 1098static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1099{
1100 decode_configs(c);
8ff374b9 1101 switch (c->processor_id & PRID_IMP_MASK) {
0dd4781b
DD		 1102 case PRID_IMP_CAVIUM_CN38XX:
1103 case PRID_IMP_CAVIUM_CN31XX:
1104 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 1105 c->cputype = CPU_CAVIUM_OCTEON;
1106 __cpu_name[cpu] = "Cavium Octeon";
1107 goto platform;
0dd4781b
DD		 1108 case PRID_IMP_CAVIUM_CN58XX:
1109 case PRID_IMP_CAVIUM_CN56XX:
1110 case PRID_IMP_CAVIUM_CN50XX:
1111 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 1112 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1113 __cpu_name[cpu] = "Cavium Octeon+";
1114platform:
c094c99e 1115 set_elf_platform(cpu, "octeon");
0dd4781b 1116 break;
a1431b61 1117 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 1118 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 1119 case PRID_IMP_CAVIUM_CN66XX:
1120 case PRID_IMP_CAVIUM_CN68XX:
af04bb85 1121 case PRID_IMP_CAVIUM_CNF71XX:
0e56b385
DD		 1122 c->cputype = CPU_CAVIUM_OCTEON2;
1123 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 1124 set_elf_platform(cpu, "octeon2");
0e56b385 1125 break;
af04bb85
DD		 1126 case PRID_IMP_CAVIUM_CN70XX:
1127 case PRID_IMP_CAVIUM_CN78XX:
1128 c->cputype = CPU_CAVIUM_OCTEON3;
1129 __cpu_name[cpu] = "Cavium Octeon III";
1130 set_elf_platform(cpu, "octeon3");
1131 break;
0dd4781b
DD		 1132 default:
1133 printk(KERN_INFO "Unknown Octeon chip!\n");
1134 c->cputype = CPU_UNKNOWN;
1135 break;
1136 }
1137}
1138
83ccf69d
LPC		 1139static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1140{
1141 decode_configs(c);
1142 /* JZRISC does not implement the CP0 counter. */
1143 c->options &= ~MIPS_CPU_COUNTER;
06947aaa 1144 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
8ff374b9 1145 switch (c->processor_id & PRID_IMP_MASK) {
83ccf69d
LPC		 1146 case PRID_IMP_JZRISC:
1147 c->cputype = CPU_JZRISC;
4f12b91d 1148 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
83ccf69d
LPC		 1149 __cpu_name[cpu] = "Ingenic JZRISC";
1150 break;
1151 default:
1152 panic("Unknown Ingenic Processor ID!");
1153 break;
1154 }
1155}
1156
a7117c6b
J		 1157static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1158{
1159 decode_configs(c);
1160
8ff374b9 1161 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
809f36c6
ML		 1162 c->cputype = CPU_ALCHEMY;
1163 __cpu_name[cpu] = "Au1300";
1164 /* following stuff is not for Alchemy */
1165 return;
1166 }
1167
70342287
RB		 1168 c->options = (MIPS_CPU_TLB |
1169 MIPS_CPU_4KEX |
a7117c6b 1170 MIPS_CPU_COUNTER |
70342287
RB		 1171 MIPS_CPU_DIVEC |
1172 MIPS_CPU_WATCH |
1173 MIPS_CPU_EJTAG |
a7117c6b
J		 1174 MIPS_CPU_LLSC);
1175
8ff374b9 1176 switch (c->processor_id & PRID_IMP_MASK) {
4ca86a2f 1177 case PRID_IMP_NETLOGIC_XLP2XX:
8907c55e 1178 case PRID_IMP_NETLOGIC_XLP9XX:
1c983986 1179 case PRID_IMP_NETLOGIC_XLP5XX:
4ca86a2f
J		 1180 c->cputype = CPU_XLP;
1181 __cpu_name[cpu] = "Broadcom XLPII";
1182 break;
1183
2aa54b20
J		 1184 case PRID_IMP_NETLOGIC_XLP8XX:
1185 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 1186 c->cputype = CPU_XLP;
1187 __cpu_name[cpu] = "Netlogic XLP";
1188 break;
1189
a7117c6b
J		 1190 case PRID_IMP_NETLOGIC_XLR732:
1191 case PRID_IMP_NETLOGIC_XLR716:
1192 case PRID_IMP_NETLOGIC_XLR532:
1193 case PRID_IMP_NETLOGIC_XLR308:
1194 case PRID_IMP_NETLOGIC_XLR532C:
1195 case PRID_IMP_NETLOGIC_XLR516C:
1196 case PRID_IMP_NETLOGIC_XLR508C:
1197 case PRID_IMP_NETLOGIC_XLR308C:
1198 c->cputype = CPU_XLR;
1199 __cpu_name[cpu] = "Netlogic XLR";
1200 break;
1201
1202 case PRID_IMP_NETLOGIC_XLS608:
1203 case PRID_IMP_NETLOGIC_XLS408:
1204 case PRID_IMP_NETLOGIC_XLS404:
1205 case PRID_IMP_NETLOGIC_XLS208:
1206 case PRID_IMP_NETLOGIC_XLS204:
1207 case PRID_IMP_NETLOGIC_XLS108:
1208 case PRID_IMP_NETLOGIC_XLS104:
1209 case PRID_IMP_NETLOGIC_XLS616B:
1210 case PRID_IMP_NETLOGIC_XLS608B:
1211 case PRID_IMP_NETLOGIC_XLS416B:
1212 case PRID_IMP_NETLOGIC_XLS412B:
1213 case PRID_IMP_NETLOGIC_XLS408B:
1214 case PRID_IMP_NETLOGIC_XLS404B:
1215 c->cputype = CPU_XLR;
1216 __cpu_name[cpu] = "Netlogic XLS";
1217 break;
1218
1219 default:
a3d4fb2d 1220 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 1221 c->processor_id);
1222 c->cputype = CPU_XLR;
1223 break;
1224 }
1225
a3d4fb2d 1226 if (c->cputype == CPU_XLP) {
a96102be 1227 set_isa(c, MIPS_CPU_ISA_M64R2);
a3d4fb2d
J		 1228 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1229 /* This will be updated again after all threads are woken up */
1230 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1231 } else {
a96102be 1232 set_isa(c, MIPS_CPU_ISA_M64R1);
a3d4fb2d
J		 1233 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1234 }
7777b939 1235 c->kscratch_mask = 0xf;
a7117c6b
J		 1236}
1237
949e51be
DD		 1238#ifdef CONFIG_64BIT
1239/* For use by uaccess.h */
1240u64 __ua_limit;
1241EXPORT_SYMBOL(__ua_limit);
1242#endif
1243
9966db25 1244const char *__cpu_name[NR_CPUS];
874fd3b5 1245const char *__elf_platform;
9966db25 1246
078a55fc 1247void cpu_probe(void)
1da177e4
LT		 1248{
1249 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 1250 unsigned int cpu = smp_processor_id();
1da177e4 1251
70342287 1252 c->processor_id = PRID_IMP_UNKNOWN;
1da177e4
LT		 1253 c->fpu_id = FPIR_IMP_NONE;
1254 c->cputype = CPU_UNKNOWN;
4f12b91d 1255 c->writecombine = _CACHE_UNCACHED;
1da177e4
LT		 1256
1257 c->processor_id = read_c0_prid();
8ff374b9 1258 switch (c->processor_id & PRID_COMP_MASK) {
1da177e4 1259 case PRID_COMP_LEGACY:
cea7e2df 1260 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1261 break;
1262 case PRID_COMP_MIPS:
cea7e2df 1263 cpu_probe_mips(c, cpu);
1da177e4
LT		 1264 break;
1265 case PRID_COMP_ALCHEMY:
cea7e2df 1266 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1267 break;
1268 case PRID_COMP_SIBYTE:
cea7e2df 1269 cpu_probe_sibyte(c, cpu);
1da177e4 1270 break;
1c0c13eb 1271 case PRID_COMP_BROADCOM:
cea7e2df 1272 cpu_probe_broadcom(c, cpu);
1c0c13eb 1273 break;
1da177e4 1274 case PRID_COMP_SANDCRAFT:
cea7e2df 1275 cpu_probe_sandcraft(c, cpu);
1da177e4 1276 break;
a92b0588 1277 case PRID_COMP_NXP:
cea7e2df 1278 cpu_probe_nxp(c, cpu);
a3dddd56 1279 break;
0dd4781b
DD		 1280 case PRID_COMP_CAVIUM:
1281 cpu_probe_cavium(c, cpu);
1282 break;
83ccf69d
LPC		 1283 case PRID_COMP_INGENIC:
1284 cpu_probe_ingenic(c, cpu);
1285 break;
a7117c6b
J		 1286 case PRID_COMP_NETLOGIC:
1287 cpu_probe_netlogic(c, cpu);
1288 break;
1da177e4 1289 }
dec8b1ca 1290
cea7e2df
RB		 1291 BUG_ON(!__cpu_name[cpu]);
1292 BUG_ON(c->cputype == CPU_UNKNOWN);
1293
dec8b1ca
FBH		 1294 /*
1295 * Platform code can force the cpu type to optimize code
1296 * generation. In that case be sure the cpu type is correctly
1297 * manually setup otherwise it could trigger some nasty bugs.
1298 */
1299 BUG_ON(current_cpu_type() != c->cputype);
1300
0103d23f
KC		 1301 if (mips_fpu_disabled)
1302 c->options &= ~MIPS_CPU_FPU;
1303
1304 if (mips_dsp_disabled)
ee80f7c7 1305 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f 1306
3d528b32
MC		 1307 if (mips_htw_disabled) {
1308 c->options &= ~MIPS_CPU_HTW;
1309 write_c0_pwctl(read_c0_pwctl() &
1310 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1311 }
1312
4194318c 1313 if (c->options & MIPS_CPU_FPU) {
1da177e4 1314 c->fpu_id = cpu_get_fpu_id();
4194318c 1315
adb37892
DCZ		 1316 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1317 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
4194318c
RB		 1318 if (c->fpu_id & MIPS_FPIR_3D)
1319 c->ases |= MIPS_ASE_MIPS3D;
adac5d53
PB		 1320 if (c->fpu_id & MIPS_FPIR_FREP)
1321 c->options |= MIPS_CPU_FRE;
4194318c
RB		 1322 }
1323 }
9966db25 1324
da4b62cd 1325 if (cpu_has_mips_r2) {
f6771dbb 1326 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
da4b62cd
AC		 1327 /* R2 has Performance Counter Interrupt indicator */
1328 c->options |= MIPS_CPU_PCI;
1329 }
f6771dbb
RB		 1330 else
1331 c->srsets = 1;
91dfc423 1332
a8ad1367 1333 if (cpu_has_msa) {
a5e9a69e 1334 c->msa_id = cpu_get_msa_id();
a8ad1367
PB		 1335 WARN(c->msa_id & MSA_IR_WRPF,
1336 "Vector register partitioning unimplemented!");
1337 }
a5e9a69e 1338
91dfc423 1339 cpu_probe_vmbits(c);
949e51be
DD		 1340
1341#ifdef CONFIG_64BIT
1342 if (cpu == 0)
1343 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1344#endif
1da177e4
LT		 1345}
1346
078a55fc 1347void cpu_report(void)
1da177e4
LT		 1348{
1349 struct cpuinfo_mips *c = &current_cpu_data;
1350
d9f897c9
LY		 1351 pr_info("CPU%d revision is: %08x (%s)\n",
1352 smp_processor_id(), c->processor_id, cpu_name_string());
1da177e4 1353 if (c->options & MIPS_CPU_FPU)
9966db25 1354 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
a5e9a69e
PB		 1355 if (cpu_has_msa)
1356 pr_info("MSA revision is: %08x\n", c->msa_id);
1da177e4 1357}
Linux 6.x block layer and io_uring tree(s)