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MIPS: Add cases for CPU_P5600
[linux-2.6-block.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
70342287 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4 22#include <asm/cpu.h>
69f24d17 23#include <asm/cpu-type.h>
1da177e4
LT		 24#include <asm/fpu.h>
25#include <asm/mipsregs.h>
a5e9a69e 26#include <asm/msa.h>
654f57bf 27#include <asm/watch.h>
06372a63 28#include <asm/elf.h>
a074f0e8 29#include <asm/spram.h>
949e51be
DD		 30#include <asm/uaccess.h>
31
078a55fc 32static int mips_fpu_disabled;
0103d23f
KC		 33
34static int __init fpu_disable(char *s)
35{
36 cpu_data[0].options &= ~MIPS_CPU_FPU;
37 mips_fpu_disabled = 1;
38
39 return 1;
40}
41
42__setup("nofpu", fpu_disable);
43
078a55fc 44int mips_dsp_disabled;
0103d23f
KC		 45
46static int __init dsp_disable(char *s)
47{
ee80f7c7 48 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f
KC		 49 mips_dsp_disabled = 1;
50
51 return 1;
52}
53
54__setup("nodsp", dsp_disable);
55
9267a30d
MSJ		 56static inline void check_errata(void)
57{
58 struct cpuinfo_mips *c = &current_cpu_data;
59
69f24d17 60 switch (current_cpu_type()) {
9267a30d
MSJ		 61 case CPU_34K:
62 /*
63 * Erratum "RPS May Cause Incorrect Instruction Execution"
64 * This code only handles VPE0, any SMP/SMTC/RTOS code
65 * making use of VPE1 will be responsable for that VPE.
66 */
67 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
68 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
69 break;
70 default:
71 break;
72 }
73}
74
1da177e4
LT		 75void __init check_bugs32(void)
76{
9267a30d 77 check_errata();
1da177e4
LT		 78}
79
80/*
81 * Probe whether cpu has config register by trying to play with
82 * alternate cache bit and see whether it matters.
83 * It's used by cpu_probe to distinguish between R3000A and R3081.
84 */
85static inline int cpu_has_confreg(void)
86{
87#ifdef CONFIG_CPU_R3000
88 extern unsigned long r3k_cache_size(unsigned long);
89 unsigned long size1, size2;
90 unsigned long cfg = read_c0_conf();
91
92 size1 = r3k_cache_size(ST0_ISC);
93 write_c0_conf(cfg ^ R30XX_CONF_AC);
94 size2 = r3k_cache_size(ST0_ISC);
95 write_c0_conf(cfg);
96 return size1 != size2;
97#else
98 return 0;
99#endif
100}
101
c094c99e
RM		 102static inline void set_elf_platform(int cpu, const char *plat)
103{
104 if (cpu == 0)
105 __elf_platform = plat;
106}
107
1da177e4
LT		 108/*
109 * Get the FPU Implementation/Revision.
110 */
111static inline unsigned long cpu_get_fpu_id(void)
112{
113 unsigned long tmp, fpu_id;
114
115 tmp = read_c0_status();
597ce172 116 __enable_fpu(FPU_AS_IS);
1da177e4
LT		 117 fpu_id = read_32bit_cp1_register(CP1_REVISION);
118 write_c0_status(tmp);
119 return fpu_id;
120}
121
122/*
123 * Check the CPU has an FPU the official way.
124 */
125static inline int __cpu_has_fpu(void)
126{
8ff374b9 127 return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
1da177e4
LT		 128}
129
a5e9a69e
PB		 130static inline unsigned long cpu_get_msa_id(void)
131{
132 unsigned long status, conf5, msa_id;
133
134 status = read_c0_status();
135 __enable_fpu(FPU_64BIT);
136 conf5 = read_c0_config5();
137 enable_msa();
138 msa_id = read_msa_ir();
139 write_c0_config5(conf5);
140 write_c0_status(status);
141 return msa_id;
142}
143
91dfc423
GR		 144static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
145{
146#ifdef __NEED_VMBITS_PROBE
5b7efa89 147 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 148 back_to_back_c0_hazard();
5b7efa89 149 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 150#endif
151}
152
078a55fc 153static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
a96102be
SH		 154{
155 switch (isa) {
156 case MIPS_CPU_ISA_M64R2:
157 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
158 case MIPS_CPU_ISA_M64R1:
159 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
160 case MIPS_CPU_ISA_V:
161 c->isa_level |= MIPS_CPU_ISA_V;
162 case MIPS_CPU_ISA_IV:
163 c->isa_level |= MIPS_CPU_ISA_IV;
164 case MIPS_CPU_ISA_III:
1990e542 165 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
a96102be
SH		 166 break;
167
168 case MIPS_CPU_ISA_M32R2:
169 c->isa_level |= MIPS_CPU_ISA_M32R2;
170 case MIPS_CPU_ISA_M32R1:
171 c->isa_level |= MIPS_CPU_ISA_M32R1;
172 case MIPS_CPU_ISA_II:
173 c->isa_level |= MIPS_CPU_ISA_II;
a96102be
SH		 174 break;
175 }
176}
177
078a55fc 178static char unknown_isa[] = KERN_ERR \
2fa36399
KC		 179 "Unsupported ISA type, c0.config0: %d.";
180
75b5b5e0
LY		 181static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
182{
183 unsigned int config6;
184 /*
185 * Config6 is implementation dependent and it's currently only
186 * used by proAptiv
187 */
188 if (c->cputype == CPU_PROAPTIV) {
189 config6 = read_c0_config6();
190 if (enable)
191 /* Enable FTLB */
192 write_c0_config6(config6 | MIPS_CONF6_FTLBEN);
193 else
194 /* Disable FTLB */
195 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
196 back_to_back_c0_hazard();
197 }
198}
199
2fa36399
KC		 200static inline unsigned int decode_config0(struct cpuinfo_mips *c)
201{
202 unsigned int config0;
203 int isa;
204
205 config0 = read_c0_config();
206
75b5b5e0
LY		 207 /*
208 * Look for Standard TLB or Dual VTLB and FTLB
209 */
210 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
211 (((config0 & MIPS_CONF_MT) >> 7) == 4))
2fa36399 212 c->options |= MIPS_CPU_TLB;
75b5b5e0 213
2fa36399
KC		 214 isa = (config0 & MIPS_CONF_AT) >> 13;
215 switch (isa) {
216 case 0:
217 switch ((config0 & MIPS_CONF_AR) >> 10) {
218 case 0:
a96102be 219 set_isa(c, MIPS_CPU_ISA_M32R1);
2fa36399
KC		 220 break;
221 case 1:
a96102be 222 set_isa(c, MIPS_CPU_ISA_M32R2);
2fa36399
KC		 223 break;
224 default:
225 goto unknown;
226 }
227 break;
228 case 2:
229 switch ((config0 & MIPS_CONF_AR) >> 10) {
230 case 0:
a96102be 231 set_isa(c, MIPS_CPU_ISA_M64R1);
2fa36399
KC		 232 break;
233 case 1:
a96102be 234 set_isa(c, MIPS_CPU_ISA_M64R2);
2fa36399
KC		 235 break;
236 default:
237 goto unknown;
238 }
239 break;
240 default:
241 goto unknown;
242 }
243
244 return config0 & MIPS_CONF_M;
245
246unknown:
247 panic(unknown_isa, config0);
248}
249
250static inline unsigned int decode_config1(struct cpuinfo_mips *c)
251{
252 unsigned int config1;
253
254 config1 = read_c0_config1();
255
256 if (config1 & MIPS_CONF1_MD)
257 c->ases |= MIPS_ASE_MDMX;
258 if (config1 & MIPS_CONF1_WR)
259 c->options |= MIPS_CPU_WATCH;
260 if (config1 & MIPS_CONF1_CA)
261 c->ases |= MIPS_ASE_MIPS16;
262 if (config1 & MIPS_CONF1_EP)
263 c->options |= MIPS_CPU_EJTAG;
264 if (config1 & MIPS_CONF1_FP) {
265 c->options |= MIPS_CPU_FPU;
266 c->options |= MIPS_CPU_32FPR;
267 }
75b5b5e0 268 if (cpu_has_tlb) {
2fa36399 269 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
75b5b5e0
LY		 270 c->tlbsizevtlb = c->tlbsize;
271 c->tlbsizeftlbsets = 0;
272 }
2fa36399
KC		 273
274 return config1 & MIPS_CONF_M;
275}
276
277static inline unsigned int decode_config2(struct cpuinfo_mips *c)
278{
279 unsigned int config2;
280
281 config2 = read_c0_config2();
282
283 if (config2 & MIPS_CONF2_SL)
284 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
285
286 return config2 & MIPS_CONF_M;
287}
288
289static inline unsigned int decode_config3(struct cpuinfo_mips *c)
290{
291 unsigned int config3;
292
293 config3 = read_c0_config3();
294
b2ab4f08 295 if (config3 & MIPS_CONF3_SM) {
2fa36399 296 c->ases |= MIPS_ASE_SMARTMIPS;
b2ab4f08
SH		 297 c->options |= MIPS_CPU_RIXI;
298 }
299 if (config3 & MIPS_CONF3_RXI)
300 c->options |= MIPS_CPU_RIXI;
2fa36399
KC		 301 if (config3 & MIPS_CONF3_DSP)
302 c->ases |= MIPS_ASE_DSP;
ee80f7c7
SH		 303 if (config3 & MIPS_CONF3_DSP2P)
304 c->ases |= MIPS_ASE_DSP2P;
2fa36399
KC		 305 if (config3 & MIPS_CONF3_VINT)
306 c->options |= MIPS_CPU_VINT;
307 if (config3 & MIPS_CONF3_VEIC)
308 c->options |= MIPS_CPU_VEIC;
309 if (config3 & MIPS_CONF3_MT)
310 c->ases |= MIPS_ASE_MIPSMT;
311 if (config3 & MIPS_CONF3_ULRI)
312 c->options |= MIPS_CPU_ULRI;
f8fa4811
SH		 313 if (config3 & MIPS_CONF3_ISA)
314 c->options |= MIPS_CPU_MICROMIPS;
1e7decdb
DD		 315 if (config3 & MIPS_CONF3_VZ)
316 c->ases |= MIPS_ASE_VZ;
4a0156fb
SH		 317 if (config3 & MIPS_CONF3_SC)
318 c->options |= MIPS_CPU_SEGMENTS;
a5e9a69e
PB		 319 if (config3 & MIPS_CONF3_MSA)
320 c->ases |= MIPS_ASE_MSA;
2fa36399
KC		 321
322 return config3 & MIPS_CONF_M;
323}
324
325static inline unsigned int decode_config4(struct cpuinfo_mips *c)
326{
327 unsigned int config4;
75b5b5e0
LY		 328 unsigned int newcf4;
329 unsigned int mmuextdef;
330 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
2fa36399
KC		 331
332 config4 = read_c0_config4();
333
1745c1ef
LY		 334 if (cpu_has_tlb) {
335 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
336 c->options |= MIPS_CPU_TLBINV;
75b5b5e0
LY		 337 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
338 switch (mmuextdef) {
339 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
340 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
341 c->tlbsizevtlb = c->tlbsize;
342 break;
343 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
344 c->tlbsizevtlb +=
345 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
346 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
347 c->tlbsize = c->tlbsizevtlb;
348 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
349 /* fall through */
350 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
351 newcf4 = (config4 & ~ftlb_page) |
352 (page_size_ftlb(mmuextdef) <<
353 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
354 write_c0_config4(newcf4);
355 back_to_back_c0_hazard();
356 config4 = read_c0_config4();
357 if (config4 != newcf4) {
358 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
359 PAGE_SIZE, config4);
360 /* Switch FTLB off */
361 set_ftlb_enable(c, 0);
362 break;
363 }
364 c->tlbsizeftlbsets = 1 <<
365 ((config4 & MIPS_CONF4_FTLBSETS) >>
366 MIPS_CONF4_FTLBSETS_SHIFT);
367 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
368 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
369 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
370 break;
371 }
1745c1ef
LY		 372 }
373
2fa36399
KC		 374 c->kscratch_mask = (config4 >> 16) & 0xff;
375
376 return config4 & MIPS_CONF_M;
377}
378
8b8a7634
RB		 379static inline unsigned int decode_config5(struct cpuinfo_mips *c)
380{
381 unsigned int config5;
382
383 config5 = read_c0_config5();
384 config5 &= ~MIPS_CONF5_UFR;
385 write_c0_config5(config5);
386
387 return config5 & MIPS_CONF_M;
388}
389
078a55fc 390static void decode_configs(struct cpuinfo_mips *c)
2fa36399
KC		 391{
392 int ok;
393
394 /* MIPS32 or MIPS64 compliant CPU. */
395 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
396 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
397
398 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
399
75b5b5e0
LY		 400 /* Enable FTLB if present */
401 set_ftlb_enable(c, 1);
402
2fa36399 403 ok = decode_config0(c); /* Read Config registers. */
70342287 404 BUG_ON(!ok); /* Arch spec violation! */
2fa36399
KC		 405 if (ok)
406 ok = decode_config1(c);
407 if (ok)
408 ok = decode_config2(c);
409 if (ok)
410 ok = decode_config3(c);
411 if (ok)
412 ok = decode_config4(c);
8b8a7634
RB		 413 if (ok)
414 ok = decode_config5(c);
2fa36399
KC		 415
416 mips_probe_watch_registers(c);
417
0ee958e1 418#ifndef CONFIG_MIPS_CPS
2fa36399
KC		 419 if (cpu_has_mips_r2)
420 c->core = read_c0_ebase() & 0x3ff;
0ee958e1 421#endif
2fa36399
KC		 422}
423
02cf2119 424#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 425 | MIPS_CPU_COUNTER)
426
cea7e2df 427static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 428{
8ff374b9 429 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 430 case PRID_IMP_R2000:
431 c->cputype = CPU_R2000;
cea7e2df 432 __cpu_name[cpu] = "R2000";
02cf2119 433 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 434 MIPS_CPU_NOFPUEX;
1da177e4
LT		 435 if (__cpu_has_fpu())
436 c->options |= MIPS_CPU_FPU;
437 c->tlbsize = 64;
438 break;
439 case PRID_IMP_R3000:
8ff374b9 440 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
cea7e2df 441 if (cpu_has_confreg()) {
1da177e4 442 c->cputype = CPU_R3081E;
cea7e2df
RB		 443 __cpu_name[cpu] = "R3081";
444 } else {
1da177e4 445 c->cputype = CPU_R3000A;
cea7e2df
RB		 446 __cpu_name[cpu] = "R3000A";
447 }
cea7e2df 448 } else {
1da177e4 449 c->cputype = CPU_R3000;
cea7e2df
RB		 450 __cpu_name[cpu] = "R3000";
451 }
02cf2119 452 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 453 MIPS_CPU_NOFPUEX;
1da177e4
LT		 454 if (__cpu_has_fpu())
455 c->options |= MIPS_CPU_FPU;
456 c->tlbsize = 64;
457 break;
458 case PRID_IMP_R4000:
459 if (read_c0_config() & CONF_SC) {
8ff374b9
MR		 460 if ((c->processor_id & PRID_REV_MASK) >=
461 PRID_REV_R4400) {
1da177e4 462 c->cputype = CPU_R4400PC;
cea7e2df
RB		 463 __cpu_name[cpu] = "R4400PC";
464 } else {
1da177e4 465 c->cputype = CPU_R4000PC;
cea7e2df
RB		 466 __cpu_name[cpu] = "R4000PC";
467 }
1da177e4 468 } else {
7f177a52
MR		 469 int cca = read_c0_config() & CONF_CM_CMASK;
470 int mc;
471
472 /*
473 * SC and MC versions can't be reliably told apart,
474 * but only the latter support coherent caching
475 * modes so assume the firmware has set the KSEG0
476 * coherency attribute reasonably (if uncached, we
477 * assume SC).
478 */
479 switch (cca) {
480 case CONF_CM_CACHABLE_CE:
481 case CONF_CM_CACHABLE_COW:
482 case CONF_CM_CACHABLE_CUW:
483 mc = 1;
484 break;
485 default:
486 mc = 0;
487 break;
488 }
8ff374b9
MR		 489 if ((c->processor_id & PRID_REV_MASK) >=
490 PRID_REV_R4400) {
7f177a52
MR		 491 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
492 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
cea7e2df 493 } else {
7f177a52
MR		 494 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
495 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
cea7e2df 496 }
1da177e4
LT		 497 }
498
a96102be 499 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 500 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 501 MIPS_CPU_WATCH | MIPS_CPU_VCE |
502 MIPS_CPU_LLSC;
1da177e4
LT		 503 c->tlbsize = 48;
504 break;
505 case PRID_IMP_VR41XX:
9f91e506
YY		 506 set_isa(c, MIPS_CPU_ISA_III);
507 c->options = R4K_OPTS;
508 c->tlbsize = 32;
1da177e4 509 switch (c->processor_id & 0xf0) {
1da177e4
LT		 510 case PRID_REV_VR4111:
511 c->cputype = CPU_VR4111;
cea7e2df 512 __cpu_name[cpu] = "NEC VR4111";
1da177e4 513 break;
1da177e4
LT		 514 case PRID_REV_VR4121:
515 c->cputype = CPU_VR4121;
cea7e2df 516 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 517 break;
518 case PRID_REV_VR4122:
cea7e2df 519 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 520 c->cputype = CPU_VR4122;
cea7e2df
RB		 521 __cpu_name[cpu] = "NEC VR4122";
522 } else {
1da177e4 523 c->cputype = CPU_VR4181A;
cea7e2df
RB		 524 __cpu_name[cpu] = "NEC VR4181A";
525 }
1da177e4
LT		 526 break;
527 case PRID_REV_VR4130:
cea7e2df 528 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 529 c->cputype = CPU_VR4131;
cea7e2df
RB		 530 __cpu_name[cpu] = "NEC VR4131";
531 } else {
1da177e4 532 c->cputype = CPU_VR4133;
9f91e506 533 c->options |= MIPS_CPU_LLSC;
cea7e2df
RB		 534 __cpu_name[cpu] = "NEC VR4133";
535 }
1da177e4
LT		 536 break;
537 default:
538 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
539 c->cputype = CPU_VR41XX;
cea7e2df 540 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 541 break;
542 }
1da177e4
LT		 543 break;
544 case PRID_IMP_R4300:
545 c->cputype = CPU_R4300;
cea7e2df 546 __cpu_name[cpu] = "R4300";
a96102be 547 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 548 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 549 MIPS_CPU_LLSC;
1da177e4
LT		 550 c->tlbsize = 32;
551 break;
552 case PRID_IMP_R4600:
553 c->cputype = CPU_R4600;
cea7e2df 554 __cpu_name[cpu] = "R4600";
a96102be 555 set_isa(c, MIPS_CPU_ISA_III);
075e7502
TS		 556 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
557 MIPS_CPU_LLSC;
1da177e4
LT		 558 c->tlbsize = 48;
559 break;
560 #if 0
03751e79 561 case PRID_IMP_R4650:
1da177e4
LT		 562 /*
563 * This processor doesn't have an MMU, so it's not
564 * "real easy" to run Linux on it. It is left purely
565 * for documentation. Commented out because it shares
566 * it's c0_prid id number with the TX3900.
567 */
a3dddd56 568 c->cputype = CPU_R4650;
cea7e2df 569 __cpu_name[cpu] = "R4650";
a96102be 570 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 571 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 572 c->tlbsize = 48;
1da177e4
LT		 573 break;
574 #endif
575 case PRID_IMP_TX39:
02cf2119 576 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 577
578 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
579 c->cputype = CPU_TX3927;
cea7e2df 580 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 581 c->tlbsize = 64;
582 } else {
8ff374b9 583 switch (c->processor_id & PRID_REV_MASK) {
1da177e4
LT		 584 case PRID_REV_TX3912:
585 c->cputype = CPU_TX3912;
cea7e2df 586 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 587 c->tlbsize = 32;
588 break;
589 case PRID_REV_TX3922:
590 c->cputype = CPU_TX3922;
cea7e2df 591 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 592 c->tlbsize = 64;
593 break;
1da177e4
LT		 594 }
595 }
596 break;
597 case PRID_IMP_R4700:
598 c->cputype = CPU_R4700;
cea7e2df 599 __cpu_name[cpu] = "R4700";
a96102be 600 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 601 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 602 MIPS_CPU_LLSC;
1da177e4
LT		 603 c->tlbsize = 48;
604 break;
605 case PRID_IMP_TX49:
606 c->cputype = CPU_TX49XX;
cea7e2df 607 __cpu_name[cpu] = "R49XX";
a96102be 608 set_isa(c, MIPS_CPU_ISA_III);
1da177e4
LT		 609 c->options = R4K_OPTS | MIPS_CPU_LLSC;
610 if (!(c->processor_id & 0x08))
611 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
612 c->tlbsize = 48;
613 break;
614 case PRID_IMP_R5000:
615 c->cputype = CPU_R5000;
cea7e2df 616 __cpu_name[cpu] = "R5000";
a96102be 617 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 618 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 619 MIPS_CPU_LLSC;
1da177e4
LT		 620 c->tlbsize = 48;
621 break;
622 case PRID_IMP_R5432:
623 c->cputype = CPU_R5432;
cea7e2df 624 __cpu_name[cpu] = "R5432";
a96102be 625 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 626 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 627 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 628 c->tlbsize = 48;
629 break;
630 case PRID_IMP_R5500:
631 c->cputype = CPU_R5500;
cea7e2df 632 __cpu_name[cpu] = "R5500";
a96102be 633 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 634 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 635 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 636 c->tlbsize = 48;
637 break;
638 case PRID_IMP_NEVADA:
639 c->cputype = CPU_NEVADA;
cea7e2df 640 __cpu_name[cpu] = "Nevada";
a96102be 641 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 642 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 643 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 644 c->tlbsize = 48;
645 break;
646 case PRID_IMP_R6000:
647 c->cputype = CPU_R6000;
cea7e2df 648 __cpu_name[cpu] = "R6000";
a96102be 649 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 650 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 651 MIPS_CPU_LLSC;
1da177e4
LT		 652 c->tlbsize = 32;
653 break;
654 case PRID_IMP_R6000A:
655 c->cputype = CPU_R6000A;
cea7e2df 656 __cpu_name[cpu] = "R6000A";
a96102be 657 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 658 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 659 MIPS_CPU_LLSC;
1da177e4
LT		 660 c->tlbsize = 32;
661 break;
662 case PRID_IMP_RM7000:
663 c->cputype = CPU_RM7000;
cea7e2df 664 __cpu_name[cpu] = "RM7000";
a96102be 665 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 666 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 667 MIPS_CPU_LLSC;
1da177e4 668 /*
70342287 669 * Undocumented RM7000: Bit 29 in the info register of
1da177e4
LT		 670 * the RM7000 v2.0 indicates if the TLB has 48 or 64
671 * entries.
672 *
70342287
RB		 673 * 29 1 => 64 entry JTLB
674 * 0 => 48 entry JTLB
1da177e4
LT		 675 */
676 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
677 break;
678 case PRID_IMP_RM9000:
679 c->cputype = CPU_RM9000;
cea7e2df 680 __cpu_name[cpu] = "RM9000";
a96102be 681 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 682 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 683 MIPS_CPU_LLSC;
1da177e4
LT		 684 /*
685 * Bit 29 in the info register of the RM9000
686 * indicates if the TLB has 48 or 64 entries.
687 *
70342287
RB		 688 * 29 1 => 64 entry JTLB
689 * 0 => 48 entry JTLB
1da177e4
LT		 690 */
691 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
692 break;
693 case PRID_IMP_R8000:
694 c->cputype = CPU_R8000;
cea7e2df 695 __cpu_name[cpu] = "RM8000";
a96102be 696 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 697 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 698 MIPS_CPU_FPU | MIPS_CPU_32FPR |
699 MIPS_CPU_LLSC;
1da177e4
LT		 700 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
701 break;
702 case PRID_IMP_R10000:
703 c->cputype = CPU_R10000;
cea7e2df 704 __cpu_name[cpu] = "R10000";
a96102be 705 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 706 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 707 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 708 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 709 MIPS_CPU_LLSC;
1da177e4
LT		 710 c->tlbsize = 64;
711 break;
712 case PRID_IMP_R12000:
713 c->cputype = CPU_R12000;
cea7e2df 714 __cpu_name[cpu] = "R12000";
a96102be 715 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 716 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 717 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 718 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 719 MIPS_CPU_LLSC;
1da177e4
LT		 720 c->tlbsize = 64;
721 break;
44d921b2
K		 722 case PRID_IMP_R14000:
723 c->cputype = CPU_R14000;
cea7e2df 724 __cpu_name[cpu] = "R14000";
a96102be 725 set_isa(c, MIPS_CPU_ISA_IV);
44d921b2 726 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 727 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 728 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 729 MIPS_CPU_LLSC;
44d921b2
K		 730 c->tlbsize = 64;
731 break;
2a21c730
FZ		 732 case PRID_IMP_LOONGSON2:
733 c->cputype = CPU_LOONGSON2;
cea7e2df 734 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a
RM		 735
736 switch (c->processor_id & PRID_REV_MASK) {
737 case PRID_REV_LOONGSON2E:
738 set_elf_platform(cpu, "loongson2e");
739 break;
740 case PRID_REV_LOONGSON2F:
741 set_elf_platform(cpu, "loongson2f");
742 break;
743 }
744
a96102be 745 set_isa(c, MIPS_CPU_ISA_III);
2a21c730
FZ		 746 c->options = R4K_OPTS |
747 MIPS_CPU_FPU | MIPS_CPU_LLSC |
748 MIPS_CPU_32FPR;
749 c->tlbsize = 64;
750 break;
2fa36399
KC		 751 case PRID_IMP_LOONGSON1:
752 decode_configs(c);
b4672d37 753
2fa36399 754 c->cputype = CPU_LOONGSON1;
1da177e4 755
2fa36399
KC		 756 switch (c->processor_id & PRID_REV_MASK) {
757 case PRID_REV_LOONGSON1B:
758 __cpu_name[cpu] = "Loongson 1B";
b4672d37 759 break;
b4672d37 760 }
4194318c 761
2fa36399 762 break;
1da177e4 763 }
1da177e4
LT		 764}
765
cea7e2df 766static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 767{
8ff374b9 768 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 769 case PRID_IMP_4KC:
770 c->cputype = CPU_4KC;
cea7e2df 771 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 772 break;
773 case PRID_IMP_4KEC:
2b07bd02
RB		 774 case PRID_IMP_4KECR2:
775 c->cputype = CPU_4KEC;
cea7e2df 776 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 777 break;
1da177e4 778 case PRID_IMP_4KSC:
8afcb5d8 779 case PRID_IMP_4KSD:
1da177e4 780 c->cputype = CPU_4KSC;
cea7e2df 781 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 782 break;
783 case PRID_IMP_5KC:
784 c->cputype = CPU_5KC;
cea7e2df 785 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4 786 break;
78d4803f
LY		 787 case PRID_IMP_5KE:
788 c->cputype = CPU_5KE;
789 __cpu_name[cpu] = "MIPS 5KE";
790 break;
1da177e4
LT		 791 case PRID_IMP_20KC:
792 c->cputype = CPU_20KC;
cea7e2df 793 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 794 break;
795 case PRID_IMP_24K:
796 c->cputype = CPU_24K;
cea7e2df 797 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4 798 break;
42f3caef
JC		 799 case PRID_IMP_24KE:
800 c->cputype = CPU_24K;
801 __cpu_name[cpu] = "MIPS 24KEc";
802 break;
1da177e4
LT		 803 case PRID_IMP_25KF:
804 c->cputype = CPU_25KF;
cea7e2df 805 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 806 break;
bbc7f22f
RB		 807 case PRID_IMP_34K:
808 c->cputype = CPU_34K;
cea7e2df 809 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 810 break;
c620953c
CD		 811 case PRID_IMP_74K:
812 c->cputype = CPU_74K;
cea7e2df 813 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 814 break;
113c62d9
SH		 815 case PRID_IMP_M14KC:
816 c->cputype = CPU_M14KC;
817 __cpu_name[cpu] = "MIPS M14Kc";
818 break;
f8fa4811
SH		 819 case PRID_IMP_M14KEC:
820 c->cputype = CPU_M14KEC;
821 __cpu_name[cpu] = "MIPS M14KEc";
822 break;
39b8d525
RB		 823 case PRID_IMP_1004K:
824 c->cputype = CPU_1004K;
cea7e2df 825 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 826 break;
006a851b 827 case PRID_IMP_1074K:
442e14a2 828 c->cputype = CPU_1074K;
006a851b
SH		 829 __cpu_name[cpu] = "MIPS 1074Kc";
830 break;
b5f065e7
LY		 831 case PRID_IMP_INTERAPTIV_UP:
832 c->cputype = CPU_INTERAPTIV;
833 __cpu_name[cpu] = "MIPS interAptiv";
834 break;
835 case PRID_IMP_INTERAPTIV_MP:
836 c->cputype = CPU_INTERAPTIV;
837 __cpu_name[cpu] = "MIPS interAptiv (multi)";
838 break;
b0d4d300
LY		 839 case PRID_IMP_PROAPTIV_UP:
840 c->cputype = CPU_PROAPTIV;
841 __cpu_name[cpu] = "MIPS proAptiv";
842 break;
843 case PRID_IMP_PROAPTIV_MP:
844 c->cputype = CPU_PROAPTIV;
845 __cpu_name[cpu] = "MIPS proAptiv (multi)";
846 break;
1da177e4 847 }
0b6d497f 848
75b5b5e0
LY		 849 decode_configs(c);
850
0b6d497f 851 spram_config();
1da177e4
LT		 852}
853
cea7e2df 854static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 855{
4194318c 856 decode_configs(c);
8ff374b9 857 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 858 case PRID_IMP_AU1_REV1:
859 case PRID_IMP_AU1_REV2:
270717a8 860 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 861 switch ((c->processor_id >> 24) & 0xff) {
862 case 0:
cea7e2df 863 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 864 break;
865 case 1:
cea7e2df 866 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 867 break;
868 case 2:
cea7e2df 869 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 870 break;
871 case 3:
cea7e2df 872 __cpu_name[cpu] = "Au1550";
1da177e4 873 break;
e3ad1c23 874 case 4:
cea7e2df 875 __cpu_name[cpu] = "Au1200";
8ff374b9 876 if ((c->processor_id & PRID_REV_MASK) == 2)
cea7e2df 877 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 878 break;
879 case 5:
cea7e2df 880 __cpu_name[cpu] = "Au1210";
e3ad1c23 881 break;
1da177e4 882 default:
270717a8 883 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 884 break;
885 }
1da177e4
LT		 886 break;
887 }
888}
889
cea7e2df 890static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 891{
4194318c 892 decode_configs(c);
02cf2119 893
8ff374b9 894 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 895 case PRID_IMP_SB1:
896 c->cputype = CPU_SB1;
cea7e2df 897 __cpu_name[cpu] = "SiByte SB1";
1da177e4 898 /* FPU in pass1 is known to have issues. */
8ff374b9 899 if ((c->processor_id & PRID_REV_MASK) < 0x02)
010b853b 900 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 901 break;
93ce2f52
AI		 902 case PRID_IMP_SB1A:
903 c->cputype = CPU_SB1A;
cea7e2df 904 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 905 break;
1da177e4
LT		 906 }
907}
908
cea7e2df 909static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 910{
4194318c 911 decode_configs(c);
8ff374b9 912 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 913 case PRID_IMP_SR71000:
914 c->cputype = CPU_SR71000;
cea7e2df 915 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 916 c->scache.ways = 8;
917 c->tlbsize = 64;
918 break;
919 }
920}
921
cea7e2df 922static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 923{
924 decode_configs(c);
8ff374b9 925 switch (c->processor_id & PRID_IMP_MASK) {
bdf21b18
PP		 926 case PRID_IMP_PR4450:
927 c->cputype = CPU_PR4450;
cea7e2df 928 __cpu_name[cpu] = "Philips PR4450";
a96102be 929 set_isa(c, MIPS_CPU_ISA_M32R1);
bdf21b18 930 break;
bdf21b18
PP		 931 }
932}
933
cea7e2df 934static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 935{
936 decode_configs(c);
8ff374b9 937 switch (c->processor_id & PRID_IMP_MASK) {
190fca3e
KC		 938 case PRID_IMP_BMIPS32_REV4:
939 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 940 c->cputype = CPU_BMIPS32;
941 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 942 set_elf_platform(cpu, "bmips32");
602977b0
KC		 943 break;
944 case PRID_IMP_BMIPS3300:
945 case PRID_IMP_BMIPS3300_ALT:
946 case PRID_IMP_BMIPS3300_BUG:
947 c->cputype = CPU_BMIPS3300;
948 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 949 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 950 break;
951 case PRID_IMP_BMIPS43XX: {
8ff374b9 952 int rev = c->processor_id & PRID_REV_MASK;
602977b0
KC		 953
954 if (rev >= PRID_REV_BMIPS4380_LO &&
955 rev <= PRID_REV_BMIPS4380_HI) {
956 c->cputype = CPU_BMIPS4380;
957 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 958 set_elf_platform(cpu, "bmips4380");
602977b0
KC		 959 } else {
960 c->cputype = CPU_BMIPS4350;
961 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 962 set_elf_platform(cpu, "bmips4350");
602977b0 963 }
0de663ef 964 break;
602977b0
KC		 965 }
966 case PRID_IMP_BMIPS5000:
967 c->cputype = CPU_BMIPS5000;
968 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 969 set_elf_platform(cpu, "bmips5000");
602977b0 970 c->options |= MIPS_CPU_ULRI;
0de663ef 971 break;
1c0c13eb
AJ		 972 }
973}
974
0dd4781b
DD		 975static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
976{
977 decode_configs(c);
8ff374b9 978 switch (c->processor_id & PRID_IMP_MASK) {
0dd4781b
DD		 979 case PRID_IMP_CAVIUM_CN38XX:
980 case PRID_IMP_CAVIUM_CN31XX:
981 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 982 c->cputype = CPU_CAVIUM_OCTEON;
983 __cpu_name[cpu] = "Cavium Octeon";
984 goto platform;
0dd4781b
DD		 985 case PRID_IMP_CAVIUM_CN58XX:
986 case PRID_IMP_CAVIUM_CN56XX:
987 case PRID_IMP_CAVIUM_CN50XX:
988 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 989 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
990 __cpu_name[cpu] = "Cavium Octeon+";
991platform:
c094c99e 992 set_elf_platform(cpu, "octeon");
0dd4781b 993 break;
a1431b61 994 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 995 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 996 case PRID_IMP_CAVIUM_CN66XX:
997 case PRID_IMP_CAVIUM_CN68XX:
af04bb85 998 case PRID_IMP_CAVIUM_CNF71XX:
0e56b385
DD		 999 c->cputype = CPU_CAVIUM_OCTEON2;
1000 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 1001 set_elf_platform(cpu, "octeon2");
0e56b385 1002 break;
af04bb85
DD		 1003 case PRID_IMP_CAVIUM_CN70XX:
1004 case PRID_IMP_CAVIUM_CN78XX:
1005 c->cputype = CPU_CAVIUM_OCTEON3;
1006 __cpu_name[cpu] = "Cavium Octeon III";
1007 set_elf_platform(cpu, "octeon3");
1008 break;
0dd4781b
DD		 1009 default:
1010 printk(KERN_INFO "Unknown Octeon chip!\n");
1011 c->cputype = CPU_UNKNOWN;
1012 break;
1013 }
1014}
1015
83ccf69d
LPC		 1016static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1017{
1018 decode_configs(c);
1019 /* JZRISC does not implement the CP0 counter. */
1020 c->options &= ~MIPS_CPU_COUNTER;
8ff374b9 1021 switch (c->processor_id & PRID_IMP_MASK) {
83ccf69d
LPC		 1022 case PRID_IMP_JZRISC:
1023 c->cputype = CPU_JZRISC;
1024 __cpu_name[cpu] = "Ingenic JZRISC";
1025 break;
1026 default:
1027 panic("Unknown Ingenic Processor ID!");
1028 break;
1029 }
1030}
1031
a7117c6b
J		 1032static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1033{
1034 decode_configs(c);
1035
8ff374b9 1036 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
809f36c6
ML		 1037 c->cputype = CPU_ALCHEMY;
1038 __cpu_name[cpu] = "Au1300";
1039 /* following stuff is not for Alchemy */
1040 return;
1041 }
1042
70342287
RB		 1043 c->options = (MIPS_CPU_TLB |
1044 MIPS_CPU_4KEX |
a7117c6b 1045 MIPS_CPU_COUNTER |
70342287
RB		 1046 MIPS_CPU_DIVEC |
1047 MIPS_CPU_WATCH |
1048 MIPS_CPU_EJTAG |
a7117c6b
J		 1049 MIPS_CPU_LLSC);
1050
8ff374b9 1051 switch (c->processor_id & PRID_IMP_MASK) {
4ca86a2f 1052 case PRID_IMP_NETLOGIC_XLP2XX:
8907c55e 1053 case PRID_IMP_NETLOGIC_XLP9XX:
4ca86a2f
J		 1054 c->cputype = CPU_XLP;
1055 __cpu_name[cpu] = "Broadcom XLPII";
1056 break;
1057
2aa54b20
J		 1058 case PRID_IMP_NETLOGIC_XLP8XX:
1059 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 1060 c->cputype = CPU_XLP;
1061 __cpu_name[cpu] = "Netlogic XLP";
1062 break;
1063
a7117c6b
J		 1064 case PRID_IMP_NETLOGIC_XLR732:
1065 case PRID_IMP_NETLOGIC_XLR716:
1066 case PRID_IMP_NETLOGIC_XLR532:
1067 case PRID_IMP_NETLOGIC_XLR308:
1068 case PRID_IMP_NETLOGIC_XLR532C:
1069 case PRID_IMP_NETLOGIC_XLR516C:
1070 case PRID_IMP_NETLOGIC_XLR508C:
1071 case PRID_IMP_NETLOGIC_XLR308C:
1072 c->cputype = CPU_XLR;
1073 __cpu_name[cpu] = "Netlogic XLR";
1074 break;
1075
1076 case PRID_IMP_NETLOGIC_XLS608:
1077 case PRID_IMP_NETLOGIC_XLS408:
1078 case PRID_IMP_NETLOGIC_XLS404:
1079 case PRID_IMP_NETLOGIC_XLS208:
1080 case PRID_IMP_NETLOGIC_XLS204:
1081 case PRID_IMP_NETLOGIC_XLS108:
1082 case PRID_IMP_NETLOGIC_XLS104:
1083 case PRID_IMP_NETLOGIC_XLS616B:
1084 case PRID_IMP_NETLOGIC_XLS608B:
1085 case PRID_IMP_NETLOGIC_XLS416B:
1086 case PRID_IMP_NETLOGIC_XLS412B:
1087 case PRID_IMP_NETLOGIC_XLS408B:
1088 case PRID_IMP_NETLOGIC_XLS404B:
1089 c->cputype = CPU_XLR;
1090 __cpu_name[cpu] = "Netlogic XLS";
1091 break;
1092
1093 default:
a3d4fb2d 1094 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 1095 c->processor_id);
1096 c->cputype = CPU_XLR;
1097 break;
1098 }
1099
a3d4fb2d 1100 if (c->cputype == CPU_XLP) {
a96102be 1101 set_isa(c, MIPS_CPU_ISA_M64R2);
a3d4fb2d
J		 1102 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1103 /* This will be updated again after all threads are woken up */
1104 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1105 } else {
a96102be 1106 set_isa(c, MIPS_CPU_ISA_M64R1);
a3d4fb2d
J		 1107 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1108 }
7777b939 1109 c->kscratch_mask = 0xf;
a7117c6b
J		 1110}
1111
949e51be
DD		 1112#ifdef CONFIG_64BIT
1113/* For use by uaccess.h */
1114u64 __ua_limit;
1115EXPORT_SYMBOL(__ua_limit);
1116#endif
1117
9966db25 1118const char *__cpu_name[NR_CPUS];
874fd3b5 1119const char *__elf_platform;
9966db25 1120
078a55fc 1121void cpu_probe(void)
1da177e4
LT		 1122{
1123 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 1124 unsigned int cpu = smp_processor_id();
1da177e4 1125
70342287 1126 c->processor_id = PRID_IMP_UNKNOWN;
1da177e4
LT		 1127 c->fpu_id = FPIR_IMP_NONE;
1128 c->cputype = CPU_UNKNOWN;
1129
1130 c->processor_id = read_c0_prid();
8ff374b9 1131 switch (c->processor_id & PRID_COMP_MASK) {
1da177e4 1132 case PRID_COMP_LEGACY:
cea7e2df 1133 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1134 break;
1135 case PRID_COMP_MIPS:
cea7e2df 1136 cpu_probe_mips(c, cpu);
1da177e4
LT		 1137 break;
1138 case PRID_COMP_ALCHEMY:
cea7e2df 1139 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1140 break;
1141 case PRID_COMP_SIBYTE:
cea7e2df 1142 cpu_probe_sibyte(c, cpu);
1da177e4 1143 break;
1c0c13eb 1144 case PRID_COMP_BROADCOM:
cea7e2df 1145 cpu_probe_broadcom(c, cpu);
1c0c13eb 1146 break;
1da177e4 1147 case PRID_COMP_SANDCRAFT:
cea7e2df 1148 cpu_probe_sandcraft(c, cpu);
1da177e4 1149 break;
a92b0588 1150 case PRID_COMP_NXP:
cea7e2df 1151 cpu_probe_nxp(c, cpu);
a3dddd56 1152 break;
0dd4781b
DD		 1153 case PRID_COMP_CAVIUM:
1154 cpu_probe_cavium(c, cpu);
1155 break;
83ccf69d
LPC		 1156 case PRID_COMP_INGENIC:
1157 cpu_probe_ingenic(c, cpu);
1158 break;
a7117c6b
J		 1159 case PRID_COMP_NETLOGIC:
1160 cpu_probe_netlogic(c, cpu);
1161 break;
1da177e4 1162 }
dec8b1ca 1163
cea7e2df
RB		 1164 BUG_ON(!__cpu_name[cpu]);
1165 BUG_ON(c->cputype == CPU_UNKNOWN);
1166
dec8b1ca
FBH		 1167 /*
1168 * Platform code can force the cpu type to optimize code
1169 * generation. In that case be sure the cpu type is correctly
1170 * manually setup otherwise it could trigger some nasty bugs.
1171 */
1172 BUG_ON(current_cpu_type() != c->cputype);
1173
0103d23f
KC		 1174 if (mips_fpu_disabled)
1175 c->options &= ~MIPS_CPU_FPU;
1176
1177 if (mips_dsp_disabled)
ee80f7c7 1178 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f 1179
4194318c 1180 if (c->options & MIPS_CPU_FPU) {
1da177e4 1181 c->fpu_id = cpu_get_fpu_id();
4194318c 1182
adb37892
DCZ		 1183 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1184 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
4194318c
RB		 1185 if (c->fpu_id & MIPS_FPIR_3D)
1186 c->ases |= MIPS_ASE_MIPS3D;
1187 }
1188 }
9966db25 1189
da4b62cd 1190 if (cpu_has_mips_r2) {
f6771dbb 1191 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
da4b62cd
AC		 1192 /* R2 has Performance Counter Interrupt indicator */
1193 c->options |= MIPS_CPU_PCI;
1194 }
f6771dbb
RB		 1195 else
1196 c->srsets = 1;
91dfc423 1197
a8ad1367 1198 if (cpu_has_msa) {
a5e9a69e 1199 c->msa_id = cpu_get_msa_id();
a8ad1367
PB		 1200 WARN(c->msa_id & MSA_IR_WRPF,
1201 "Vector register partitioning unimplemented!");
1202 }
a5e9a69e 1203
91dfc423 1204 cpu_probe_vmbits(c);
949e51be
DD		 1205
1206#ifdef CONFIG_64BIT
1207 if (cpu == 0)
1208 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1209#endif
1da177e4
LT		 1210}
1211
078a55fc 1212void cpu_report(void)
1da177e4
LT		 1213{
1214 struct cpuinfo_mips *c = &current_cpu_data;
1215
d9f897c9
LY		 1216 pr_info("CPU%d revision is: %08x (%s)\n",
1217 smp_processor_id(), c->processor_id, cpu_name_string());
1da177e4 1218 if (c->options & MIPS_CPU_FPU)
9966db25 1219 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
a5e9a69e
PB		 1220 if (cpu_has_msa)
1221 pr_info("MSA revision is: %08x\n", c->msa_id);
1da177e4 1222}
Linux 6.x block layer and io_uring tree(s)