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MIPS: 1004K: Enable SPRAM support.
[linux-2.6-block.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
4194318c 7 * Copyright (C) 2001, 2004 MIPS Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4
LT		 18#include <linux/stddef.h>
19
5759906c 20#include <asm/bugs.h>
1da177e4
LT		 21#include <asm/cpu.h>
22#include <asm/fpu.h>
23#include <asm/mipsregs.h>
24#include <asm/system.h>
654f57bf 25#include <asm/watch.h>
1da177e4
LT		 26
27/*
28 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
29 * the implementation of the "wait" feature differs between CPU families. This
30 * points to the function that implements CPU specific wait.
31 * The wait instruction stops the pipeline and reduces the power consumption of
32 * the CPU very much.
33 */
982f6ffe 34void (*cpu_wait)(void);
1da177e4
LT		 35
36static void r3081_wait(void)
37{
38 unsigned long cfg = read_c0_conf();
39 write_c0_conf(cfg | R30XX_CONF_HALT);
40}
41
42static void r39xx_wait(void)
43{
60a6c377
AN		 44 local_irq_disable();
45 if (!need_resched())
46 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
47 local_irq_enable();
1da177e4
LT		 48}
49
c65a5480 50extern void r4k_wait(void);
60a6c377
AN		 51
52/*
53 * This variant is preferable as it allows testing need_resched and going to
54 * sleep depending on the outcome atomically. Unfortunately the "It is
55 * implementation-dependent whether the pipeline restarts when a non-enabled
56 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
57 * using this version a gamble.
58 */
8531a35e 59void r4k_wait_irqoff(void)
60a6c377
AN		 60{
61 local_irq_disable();
62 if (!need_resched())
8531a35e
KK		 63 __asm__(" .set push \n"
64 " .set mips3 \n"
60a6c377 65 " wait \n"
8531a35e 66 " .set pop \n");
60a6c377 67 local_irq_enable();
8531a35e
KK		 68 __asm__(" .globl __pastwait \n"
69 "__pastwait: \n");
70 return;
1da177e4
LT		 71}
72
5a812999
RB		 73/*
74 * The RM7000 variant has to handle erratum 38. The workaround is to not
75 * have any pending stores when the WAIT instruction is executed.
76 */
77static void rm7k_wait_irqoff(void)
78{
79 local_irq_disable();
80 if (!need_resched())
81 __asm__(
82 " .set push \n"
83 " .set mips3 \n"
84 " .set noat \n"
85 " mfc0 $1, $12 \n"
86 " sync \n"
87 " mtc0 $1, $12 # stalls until W stage \n"
88 " wait \n"
89 " mtc0 $1, $12 # stalls until W stage \n"
90 " .set pop \n");
91 local_irq_enable();
92}
93
2882b0c6
ML		 94/*
95 * The Au1xxx wait is available only if using 32khz counter or
96 * external timer source, but specifically not CP0 Counter.
97 * alchemy/common/time.c may override cpu_wait!
98 */
494900af 99static void au1k_wait(void)
1da177e4 100{
60a6c377
AN		 101 __asm__(" .set mips3 \n"
102 " cache 0x14, 0(%0) \n"
103 " cache 0x14, 32(%0) \n"
104 " sync \n"
105 " nop \n"
106 " wait \n"
107 " nop \n"
108 " nop \n"
109 " nop \n"
110 " nop \n"
111 " .set mips0 \n"
10f650db 112 : : "r" (au1k_wait));
1da177e4
LT		 113}
114
982f6ffe 115static int __initdata nowait;
55d04dff 116
f49a747c 117static int __init wait_disable(char *s)
55d04dff
RB		 118{
119 nowait = 1;
120
121 return 1;
122}
123
124__setup("nowait", wait_disable);
125
c65a5480 126void __init check_wait(void)
1da177e4
LT		 127{
128 struct cpuinfo_mips *c = &current_cpu_data;
129
55d04dff 130 if (nowait) {
c2379230 131 printk("Wait instruction disabled.\n");
55d04dff
RB		 132 return;
133 }
134
1da177e4
LT		 135 switch (c->cputype) {
136 case CPU_R3081:
137 case CPU_R3081E:
138 cpu_wait = r3081_wait;
1da177e4
LT		 139 break;
140 case CPU_TX3927:
141 cpu_wait = r39xx_wait;
1da177e4
LT		 142 break;
143 case CPU_R4200:
144/* case CPU_R4300: */
145 case CPU_R4600:
146 case CPU_R4640:
147 case CPU_R4650:
148 case CPU_R4700:
149 case CPU_R5000:
a644b277 150 case CPU_R5500:
1da177e4 151 case CPU_NEVADA:
1da177e4
LT		 152 case CPU_4KC:
153 case CPU_4KEC:
154 case CPU_4KSC:
155 case CPU_5KC:
1da177e4 156 case CPU_25KF:
4b3e975e 157 case CPU_PR4450:
1c0c13eb 158 case CPU_BCM3302:
0de663ef
MB		 159 case CPU_BCM6338:
160 case CPU_BCM6348:
161 case CPU_BCM6358:
0dd4781b 162 case CPU_CAVIUM_OCTEON:
4b3e975e
RB		 163 cpu_wait = r4k_wait;
164 break;
165
5a812999
RB		 166 case CPU_RM7000:
167 cpu_wait = rm7k_wait_irqoff;
168 break;
169
4b3e975e 170 case CPU_24K:
bbc7f22f 171 case CPU_34K:
39b8d525 172 case CPU_1004K:
4b3e975e
RB		 173 cpu_wait = r4k_wait;
174 if (read_c0_config7() & MIPS_CONF7_WII)
175 cpu_wait = r4k_wait_irqoff;
176 break;
177
c620953c 178 case CPU_74K:
1da177e4 179 cpu_wait = r4k_wait;
4b3e975e
RB		 180 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
181 cpu_wait = r4k_wait_irqoff;
1da177e4 182 break;
4b3e975e 183
60a6c377
AN		 184 case CPU_TX49XX:
185 cpu_wait = r4k_wait_irqoff;
60a6c377 186 break;
270717a8 187 case CPU_ALCHEMY:
0c694de1 188 cpu_wait = au1k_wait;
1da177e4 189 break;
c8eae71d
RB		 190 case CPU_20KC:
191 /*
192 * WAIT on Rev1.0 has E1, E2, E3 and E16.
193 * WAIT on Rev2.0 and Rev3.0 has E16.
194 * Rev3.1 WAIT is nop, why bother
195 */
196 if ((c->processor_id & 0xff) <= 0x64)
197 break;
198
50da469a
RB		 199 /*
200 * Another rev is incremeting c0_count at a reduced clock
201 * rate while in WAIT mode. So we basically have the choice
202 * between using the cp0 timer as clocksource or avoiding
203 * the WAIT instruction. Until more details are known,
204 * disable the use of WAIT for 20Kc entirely.
205 cpu_wait = r4k_wait;
206 */
c8eae71d 207 break;
441ee341 208 case CPU_RM9000:
c2379230 209 if ((c->processor_id & 0x00ff) >= 0x40)
441ee341 210 cpu_wait = r4k_wait;
441ee341 211 break;
1da177e4 212 default:
1da177e4
LT		 213 break;
214 }
215}
216
9267a30d
MSJ		 217static inline void check_errata(void)
218{
219 struct cpuinfo_mips *c = &current_cpu_data;
220
221 switch (c->cputype) {
222 case CPU_34K:
223 /*
224 * Erratum "RPS May Cause Incorrect Instruction Execution"
225 * This code only handles VPE0, any SMP/SMTC/RTOS code
226 * making use of VPE1 will be responsable for that VPE.
227 */
228 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
229 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
230 break;
231 default:
232 break;
233 }
234}
235
1da177e4
LT		 236void __init check_bugs32(void)
237{
9267a30d 238 check_errata();
1da177e4
LT		 239}
240
241/*
242 * Probe whether cpu has config register by trying to play with
243 * alternate cache bit and see whether it matters.
244 * It's used by cpu_probe to distinguish between R3000A and R3081.
245 */
246static inline int cpu_has_confreg(void)
247{
248#ifdef CONFIG_CPU_R3000
249 extern unsigned long r3k_cache_size(unsigned long);
250 unsigned long size1, size2;
251 unsigned long cfg = read_c0_conf();
252
253 size1 = r3k_cache_size(ST0_ISC);
254 write_c0_conf(cfg ^ R30XX_CONF_AC);
255 size2 = r3k_cache_size(ST0_ISC);
256 write_c0_conf(cfg);
257 return size1 != size2;
258#else
259 return 0;
260#endif
261}
262
263/*
264 * Get the FPU Implementation/Revision.
265 */
266static inline unsigned long cpu_get_fpu_id(void)
267{
268 unsigned long tmp, fpu_id;
269
270 tmp = read_c0_status();
271 __enable_fpu();
272 fpu_id = read_32bit_cp1_register(CP1_REVISION);
273 write_c0_status(tmp);
274 return fpu_id;
275}
276
277/*
278 * Check the CPU has an FPU the official way.
279 */
280static inline int __cpu_has_fpu(void)
281{
282 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
283}
284
02cf2119 285#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 286 | MIPS_CPU_COUNTER)
287
cea7e2df 288static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4
LT		 289{
290 switch (c->processor_id & 0xff00) {
291 case PRID_IMP_R2000:
292 c->cputype = CPU_R2000;
cea7e2df 293 __cpu_name[cpu] = "R2000";
1da177e4 294 c->isa_level = MIPS_CPU_ISA_I;
02cf2119
RB		 295 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
296 MIPS_CPU_NOFPUEX;
1da177e4
LT		 297 if (__cpu_has_fpu())
298 c->options |= MIPS_CPU_FPU;
299 c->tlbsize = 64;
300 break;
301 case PRID_IMP_R3000:
cea7e2df
RB		 302 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
303 if (cpu_has_confreg()) {
1da177e4 304 c->cputype = CPU_R3081E;
cea7e2df
RB		 305 __cpu_name[cpu] = "R3081";
306 } else {
1da177e4 307 c->cputype = CPU_R3000A;
cea7e2df
RB		 308 __cpu_name[cpu] = "R3000A";
309 }
310 break;
311 } else {
1da177e4 312 c->cputype = CPU_R3000;
cea7e2df
RB		 313 __cpu_name[cpu] = "R3000";
314 }
1da177e4 315 c->isa_level = MIPS_CPU_ISA_I;
02cf2119
RB		 316 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
317 MIPS_CPU_NOFPUEX;
1da177e4
LT		 318 if (__cpu_has_fpu())
319 c->options |= MIPS_CPU_FPU;
320 c->tlbsize = 64;
321 break;
322 case PRID_IMP_R4000:
323 if (read_c0_config() & CONF_SC) {
cea7e2df 324 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
1da177e4 325 c->cputype = CPU_R4400PC;
cea7e2df
RB		 326 __cpu_name[cpu] = "R4400PC";
327 } else {
1da177e4 328 c->cputype = CPU_R4000PC;
cea7e2df
RB		 329 __cpu_name[cpu] = "R4000PC";
330 }
1da177e4 331 } else {
cea7e2df 332 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
1da177e4 333 c->cputype = CPU_R4400SC;
cea7e2df
RB		 334 __cpu_name[cpu] = "R4400SC";
335 } else {
1da177e4 336 c->cputype = CPU_R4000SC;
cea7e2df
RB		 337 __cpu_name[cpu] = "R4000SC";
338 }
1da177e4
LT		 339 }
340
341 c->isa_level = MIPS_CPU_ISA_III;
342 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
343 MIPS_CPU_WATCH | MIPS_CPU_VCE |
344 MIPS_CPU_LLSC;
345 c->tlbsize = 48;
346 break;
347 case PRID_IMP_VR41XX:
348 switch (c->processor_id & 0xf0) {
1da177e4
LT		 349 case PRID_REV_VR4111:
350 c->cputype = CPU_VR4111;
cea7e2df 351 __cpu_name[cpu] = "NEC VR4111";
1da177e4 352 break;
1da177e4
LT		 353 case PRID_REV_VR4121:
354 c->cputype = CPU_VR4121;
cea7e2df 355 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 356 break;
357 case PRID_REV_VR4122:
cea7e2df 358 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 359 c->cputype = CPU_VR4122;
cea7e2df
RB		 360 __cpu_name[cpu] = "NEC VR4122";
361 } else {
1da177e4 362 c->cputype = CPU_VR4181A;
cea7e2df
RB		 363 __cpu_name[cpu] = "NEC VR4181A";
364 }
1da177e4
LT		 365 break;
366 case PRID_REV_VR4130:
cea7e2df 367 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 368 c->cputype = CPU_VR4131;
cea7e2df
RB		 369 __cpu_name[cpu] = "NEC VR4131";
370 } else {
1da177e4 371 c->cputype = CPU_VR4133;
cea7e2df
RB		 372 __cpu_name[cpu] = "NEC VR4133";
373 }
1da177e4
LT		 374 break;
375 default:
376 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
377 c->cputype = CPU_VR41XX;
cea7e2df 378 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 379 break;
380 }
381 c->isa_level = MIPS_CPU_ISA_III;
382 c->options = R4K_OPTS;
383 c->tlbsize = 32;
384 break;
385 case PRID_IMP_R4300:
386 c->cputype = CPU_R4300;
cea7e2df 387 __cpu_name[cpu] = "R4300";
1da177e4
LT		 388 c->isa_level = MIPS_CPU_ISA_III;
389 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
390 MIPS_CPU_LLSC;
391 c->tlbsize = 32;
392 break;
393 case PRID_IMP_R4600:
394 c->cputype = CPU_R4600;
cea7e2df 395 __cpu_name[cpu] = "R4600";
1da177e4 396 c->isa_level = MIPS_CPU_ISA_III;
075e7502
TS		 397 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
398 MIPS_CPU_LLSC;
1da177e4
LT		 399 c->tlbsize = 48;
400 break;
401 #if 0
402 case PRID_IMP_R4650:
403 /*
404 * This processor doesn't have an MMU, so it's not
405 * "real easy" to run Linux on it. It is left purely
406 * for documentation. Commented out because it shares
407 * it's c0_prid id number with the TX3900.
408 */
a3dddd56 409 c->cputype = CPU_R4650;
cea7e2df 410 __cpu_name[cpu] = "R4650";
1da177e4
LT		 411 c->isa_level = MIPS_CPU_ISA_III;
412 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
413 c->tlbsize = 48;
414 break;
415 #endif
416 case PRID_IMP_TX39:
417 c->isa_level = MIPS_CPU_ISA_I;
02cf2119 418 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 419
420 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
421 c->cputype = CPU_TX3927;
cea7e2df 422 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 423 c->tlbsize = 64;
424 } else {
425 switch (c->processor_id & 0xff) {
426 case PRID_REV_TX3912:
427 c->cputype = CPU_TX3912;
cea7e2df 428 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 429 c->tlbsize = 32;
430 break;
431 case PRID_REV_TX3922:
432 c->cputype = CPU_TX3922;
cea7e2df 433 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 434 c->tlbsize = 64;
435 break;
1da177e4
LT		 436 }
437 }
438 break;
439 case PRID_IMP_R4700:
440 c->cputype = CPU_R4700;
cea7e2df 441 __cpu_name[cpu] = "R4700";
1da177e4
LT		 442 c->isa_level = MIPS_CPU_ISA_III;
443 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
444 MIPS_CPU_LLSC;
445 c->tlbsize = 48;
446 break;
447 case PRID_IMP_TX49:
448 c->cputype = CPU_TX49XX;
cea7e2df 449 __cpu_name[cpu] = "R49XX";
1da177e4
LT		 450 c->isa_level = MIPS_CPU_ISA_III;
451 c->options = R4K_OPTS | MIPS_CPU_LLSC;
452 if (!(c->processor_id & 0x08))
453 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
454 c->tlbsize = 48;
455 break;
456 case PRID_IMP_R5000:
457 c->cputype = CPU_R5000;
cea7e2df 458 __cpu_name[cpu] = "R5000";
1da177e4
LT		 459 c->isa_level = MIPS_CPU_ISA_IV;
460 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
461 MIPS_CPU_LLSC;
462 c->tlbsize = 48;
463 break;
464 case PRID_IMP_R5432:
465 c->cputype = CPU_R5432;
cea7e2df 466 __cpu_name[cpu] = "R5432";
1da177e4
LT		 467 c->isa_level = MIPS_CPU_ISA_IV;
468 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
469 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
470 c->tlbsize = 48;
471 break;
472 case PRID_IMP_R5500:
473 c->cputype = CPU_R5500;
cea7e2df 474 __cpu_name[cpu] = "R5500";
1da177e4
LT		 475 c->isa_level = MIPS_CPU_ISA_IV;
476 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
477 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
478 c->tlbsize = 48;
479 break;
480 case PRID_IMP_NEVADA:
481 c->cputype = CPU_NEVADA;
cea7e2df 482 __cpu_name[cpu] = "Nevada";
1da177e4
LT		 483 c->isa_level = MIPS_CPU_ISA_IV;
484 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
485 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
486 c->tlbsize = 48;
487 break;
488 case PRID_IMP_R6000:
489 c->cputype = CPU_R6000;
cea7e2df 490 __cpu_name[cpu] = "R6000";
1da177e4
LT		 491 c->isa_level = MIPS_CPU_ISA_II;
492 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
493 MIPS_CPU_LLSC;
494 c->tlbsize = 32;
495 break;
496 case PRID_IMP_R6000A:
497 c->cputype = CPU_R6000A;
cea7e2df 498 __cpu_name[cpu] = "R6000A";
1da177e4
LT		 499 c->isa_level = MIPS_CPU_ISA_II;
500 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
501 MIPS_CPU_LLSC;
502 c->tlbsize = 32;
503 break;
504 case PRID_IMP_RM7000:
505 c->cputype = CPU_RM7000;
cea7e2df 506 __cpu_name[cpu] = "RM7000";
1da177e4
LT		 507 c->isa_level = MIPS_CPU_ISA_IV;
508 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
509 MIPS_CPU_LLSC;
510 /*
511 * Undocumented RM7000: Bit 29 in the info register of
512 * the RM7000 v2.0 indicates if the TLB has 48 or 64
513 * entries.
514 *
515 * 29 1 => 64 entry JTLB
516 * 0 => 48 entry JTLB
517 */
518 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
519 break;
520 case PRID_IMP_RM9000:
521 c->cputype = CPU_RM9000;
cea7e2df 522 __cpu_name[cpu] = "RM9000";
1da177e4
LT		 523 c->isa_level = MIPS_CPU_ISA_IV;
524 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
525 MIPS_CPU_LLSC;
526 /*
527 * Bit 29 in the info register of the RM9000
528 * indicates if the TLB has 48 or 64 entries.
529 *
530 * 29 1 => 64 entry JTLB
531 * 0 => 48 entry JTLB
532 */
533 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
534 break;
535 case PRID_IMP_R8000:
536 c->cputype = CPU_R8000;
cea7e2df 537 __cpu_name[cpu] = "RM8000";
1da177e4
LT		 538 c->isa_level = MIPS_CPU_ISA_IV;
539 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
540 MIPS_CPU_FPU | MIPS_CPU_32FPR |
541 MIPS_CPU_LLSC;
542 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
543 break;
544 case PRID_IMP_R10000:
545 c->cputype = CPU_R10000;
cea7e2df 546 __cpu_name[cpu] = "R10000";
1da177e4 547 c->isa_level = MIPS_CPU_ISA_IV;
8b36612a 548 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1da177e4
LT		 549 MIPS_CPU_FPU | MIPS_CPU_32FPR |
550 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
551 MIPS_CPU_LLSC;
552 c->tlbsize = 64;
553 break;
554 case PRID_IMP_R12000:
555 c->cputype = CPU_R12000;
cea7e2df 556 __cpu_name[cpu] = "R12000";
1da177e4 557 c->isa_level = MIPS_CPU_ISA_IV;
8b36612a 558 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1da177e4
LT		 559 MIPS_CPU_FPU | MIPS_CPU_32FPR |
560 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
561 MIPS_CPU_LLSC;
562 c->tlbsize = 64;
563 break;
44d921b2
K		 564 case PRID_IMP_R14000:
565 c->cputype = CPU_R14000;
cea7e2df 566 __cpu_name[cpu] = "R14000";
44d921b2
K		 567 c->isa_level = MIPS_CPU_ISA_IV;
568 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
569 MIPS_CPU_FPU | MIPS_CPU_32FPR |
570 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
571 MIPS_CPU_LLSC;
572 c->tlbsize = 64;
573 break;
2a21c730
FZ		 574 case PRID_IMP_LOONGSON2:
575 c->cputype = CPU_LOONGSON2;
cea7e2df 576 __cpu_name[cpu] = "ICT Loongson-2";
2a21c730
FZ		 577 c->isa_level = MIPS_CPU_ISA_III;
578 c->options = R4K_OPTS |
579 MIPS_CPU_FPU | MIPS_CPU_LLSC |
580 MIPS_CPU_32FPR;
581 c->tlbsize = 64;
582 break;
1da177e4
LT		 583 }
584}
585
234fcd14 586static char unknown_isa[] __cpuinitdata = KERN_ERR \
b4672d37
RB		 587 "Unsupported ISA type, c0.config0: %d.";
588
4194318c 589static inline unsigned int decode_config0(struct cpuinfo_mips *c)
1da177e4 590{
4194318c
RB		 591 unsigned int config0;
592 int isa;
1da177e4 593
4194318c
RB		 594 config0 = read_c0_config();
595
596 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
02cf2119 597 c->options |= MIPS_CPU_TLB;
4194318c
RB		 598 isa = (config0 & MIPS_CONF_AT) >> 13;
599 switch (isa) {
600 case 0:
3a01c49a 601 switch ((config0 & MIPS_CONF_AR) >> 10) {
b4672d37
RB		 602 case 0:
603 c->isa_level = MIPS_CPU_ISA_M32R1;
604 break;
605 case 1:
606 c->isa_level = MIPS_CPU_ISA_M32R2;
607 break;
608 default:
609 goto unknown;
610 }
4194318c
RB		 611 break;
612 case 2:
3a01c49a 613 switch ((config0 & MIPS_CONF_AR) >> 10) {
b4672d37
RB		 614 case 0:
615 c->isa_level = MIPS_CPU_ISA_M64R1;
616 break;
617 case 1:
618 c->isa_level = MIPS_CPU_ISA_M64R2;
619 break;
620 default:
621 goto unknown;
622 }
4194318c
RB		 623 break;
624 default:
b4672d37 625 goto unknown;
4194318c
RB		 626 }
627
628 return config0 & MIPS_CONF_M;
b4672d37
RB		 629
630unknown:
631 panic(unknown_isa, config0);
4194318c
RB		 632}
633
634static inline unsigned int decode_config1(struct cpuinfo_mips *c)
635{
636 unsigned int config1;
1da177e4 637
1da177e4 638 config1 = read_c0_config1();
4194318c
RB		 639
640 if (config1 & MIPS_CONF1_MD)
641 c->ases |= MIPS_ASE_MDMX;
642 if (config1 & MIPS_CONF1_WR)
1da177e4 643 c->options |= MIPS_CPU_WATCH;
4194318c
RB		 644 if (config1 & MIPS_CONF1_CA)
645 c->ases |= MIPS_ASE_MIPS16;
646 if (config1 & MIPS_CONF1_EP)
1da177e4 647 c->options |= MIPS_CPU_EJTAG;
4194318c 648 if (config1 & MIPS_CONF1_FP) {
1da177e4
LT		 649 c->options |= MIPS_CPU_FPU;
650 c->options |= MIPS_CPU_32FPR;
651 }
4194318c
RB		 652 if (cpu_has_tlb)
653 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
654
655 return config1 & MIPS_CONF_M;
656}
657
658static inline unsigned int decode_config2(struct cpuinfo_mips *c)
659{
660 unsigned int config2;
661
662 config2 = read_c0_config2();
663
664 if (config2 & MIPS_CONF2_SL)
665 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
666
667 return config2 & MIPS_CONF_M;
668}
669
670static inline unsigned int decode_config3(struct cpuinfo_mips *c)
671{
672 unsigned int config3;
673
674 config3 = read_c0_config3();
675
676 if (config3 & MIPS_CONF3_SM)
677 c->ases |= MIPS_ASE_SMARTMIPS;
e50c0a8f
RB		 678 if (config3 & MIPS_CONF3_DSP)
679 c->ases |= MIPS_ASE_DSP;
8f40611d
RB		 680 if (config3 & MIPS_CONF3_VINT)
681 c->options |= MIPS_CPU_VINT;
682 if (config3 & MIPS_CONF3_VEIC)
683 c->options |= MIPS_CPU_VEIC;
684 if (config3 & MIPS_CONF3_MT)
e0daad44 685 c->ases |= MIPS_ASE_MIPSMT;
a3692020
RB		 686 if (config3 & MIPS_CONF3_ULRI)
687 c->options |= MIPS_CPU_ULRI;
4194318c
RB		 688
689 return config3 & MIPS_CONF_M;
690}
691
234fcd14 692static void __cpuinit decode_configs(struct cpuinfo_mips *c)
4194318c 693{
558ce124
RB		 694 int ok;
695
4194318c 696 /* MIPS32 or MIPS64 compliant CPU. */
02cf2119
RB		 697 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
698 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
4194318c 699
1da177e4
LT		 700 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
701
558ce124
RB		 702 ok = decode_config0(c); /* Read Config registers. */
703 BUG_ON(!ok); /* Arch spec violation! */
704 if (ok)
705 ok = decode_config1(c);
706 if (ok)
707 ok = decode_config2(c);
708 if (ok)
709 ok = decode_config3(c);
710
711 mips_probe_watch_registers(c);
1da177e4
LT		 712}
713
0b6d497f
CD		 714#ifdef CONFIG_CPU_MIPSR2
715extern void spram_config(void);
716#else
717static inline void spram_config(void) {}
718#endif
719
cea7e2df 720static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 721{
4194318c 722 decode_configs(c);
1da177e4
LT		 723 switch (c->processor_id & 0xff00) {
724 case PRID_IMP_4KC:
725 c->cputype = CPU_4KC;
cea7e2df 726 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 727 break;
728 case PRID_IMP_4KEC:
729 c->cputype = CPU_4KEC;
cea7e2df 730 __cpu_name[cpu] = "MIPS 4KEc";
1da177e4 731 break;
2b07bd02
RB		 732 case PRID_IMP_4KECR2:
733 c->cputype = CPU_4KEC;
cea7e2df 734 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 735 break;
1da177e4 736 case PRID_IMP_4KSC:
8afcb5d8 737 case PRID_IMP_4KSD:
1da177e4 738 c->cputype = CPU_4KSC;
cea7e2df 739 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 740 break;
741 case PRID_IMP_5KC:
742 c->cputype = CPU_5KC;
cea7e2df 743 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4
LT		 744 break;
745 case PRID_IMP_20KC:
746 c->cputype = CPU_20KC;
cea7e2df 747 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 748 break;
749 case PRID_IMP_24K:
e50c0a8f 750 case PRID_IMP_24KE:
1da177e4 751 c->cputype = CPU_24K;
cea7e2df 752 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4
LT		 753 break;
754 case PRID_IMP_25KF:
755 c->cputype = CPU_25KF;
cea7e2df 756 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 757 break;
bbc7f22f
RB		 758 case PRID_IMP_34K:
759 c->cputype = CPU_34K;
cea7e2df 760 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 761 break;
c620953c
CD		 762 case PRID_IMP_74K:
763 c->cputype = CPU_74K;
cea7e2df 764 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 765 break;
39b8d525
RB		 766 case PRID_IMP_1004K:
767 c->cputype = CPU_1004K;
cea7e2df 768 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 769 break;
1da177e4 770 }
0b6d497f
CD		 771
772 spram_config();
1da177e4
LT		 773}
774
cea7e2df 775static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 776{
4194318c 777 decode_configs(c);
1da177e4
LT		 778 switch (c->processor_id & 0xff00) {
779 case PRID_IMP_AU1_REV1:
780 case PRID_IMP_AU1_REV2:
270717a8 781 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 782 switch ((c->processor_id >> 24) & 0xff) {
783 case 0:
cea7e2df 784 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 785 break;
786 case 1:
cea7e2df 787 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 788 break;
789 case 2:
cea7e2df 790 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 791 break;
792 case 3:
cea7e2df 793 __cpu_name[cpu] = "Au1550";
1da177e4 794 break;
e3ad1c23 795 case 4:
cea7e2df 796 __cpu_name[cpu] = "Au1200";
270717a8 797 if ((c->processor_id & 0xff) == 2)
cea7e2df 798 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 799 break;
800 case 5:
cea7e2df 801 __cpu_name[cpu] = "Au1210";
e3ad1c23 802 break;
1da177e4 803 default:
270717a8 804 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 805 break;
806 }
1da177e4
LT		 807 break;
808 }
809}
810
cea7e2df 811static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 812{
4194318c 813 decode_configs(c);
02cf2119 814
1da177e4
LT		 815 switch (c->processor_id & 0xff00) {
816 case PRID_IMP_SB1:
817 c->cputype = CPU_SB1;
cea7e2df 818 __cpu_name[cpu] = "SiByte SB1";
1da177e4 819 /* FPU in pass1 is known to have issues. */
aa32374a 820 if ((c->processor_id & 0xff) < 0x02)
010b853b 821 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 822 break;
93ce2f52
AI		 823 case PRID_IMP_SB1A:
824 c->cputype = CPU_SB1A;
cea7e2df 825 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 826 break;
1da177e4
LT		 827 }
828}
829
cea7e2df 830static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 831{
4194318c 832 decode_configs(c);
1da177e4
LT		 833 switch (c->processor_id & 0xff00) {
834 case PRID_IMP_SR71000:
835 c->cputype = CPU_SR71000;
cea7e2df 836 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 837 c->scache.ways = 8;
838 c->tlbsize = 64;
839 break;
840 }
841}
842
cea7e2df 843static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 844{
845 decode_configs(c);
846 switch (c->processor_id & 0xff00) {
847 case PRID_IMP_PR4450:
848 c->cputype = CPU_PR4450;
cea7e2df 849 __cpu_name[cpu] = "Philips PR4450";
e7958bb9 850 c->isa_level = MIPS_CPU_ISA_M32R1;
bdf21b18 851 break;
bdf21b18
PP		 852 }
853}
854
cea7e2df 855static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 856{
857 decode_configs(c);
858 switch (c->processor_id & 0xff00) {
859 case PRID_IMP_BCM3302:
0de663ef 860 /* same as PRID_IMP_BCM6338 */
1c0c13eb 861 c->cputype = CPU_BCM3302;
cea7e2df 862 __cpu_name[cpu] = "Broadcom BCM3302";
1c0c13eb
AJ		 863 break;
864 case PRID_IMP_BCM4710:
865 c->cputype = CPU_BCM4710;
cea7e2df 866 __cpu_name[cpu] = "Broadcom BCM4710";
1c0c13eb 867 break;
0de663ef
MB		 868 case PRID_IMP_BCM6345:
869 c->cputype = CPU_BCM6345;
870 __cpu_name[cpu] = "Broadcom BCM6345";
871 break;
872 case PRID_IMP_BCM6348:
873 c->cputype = CPU_BCM6348;
874 __cpu_name[cpu] = "Broadcom BCM6348";
875 break;
876 case PRID_IMP_BCM4350:
877 switch (c->processor_id & 0xf0) {
878 case PRID_REV_BCM6358:
879 c->cputype = CPU_BCM6358;
880 __cpu_name[cpu] = "Broadcom BCM6358";
881 break;
882 default:
883 c->cputype = CPU_UNKNOWN;
884 break;
885 }
886 break;
1c0c13eb
AJ		 887 }
888}
889
0dd4781b
DD		 890static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
891{
892 decode_configs(c);
893 switch (c->processor_id & 0xff00) {
894 case PRID_IMP_CAVIUM_CN38XX:
895 case PRID_IMP_CAVIUM_CN31XX:
896 case PRID_IMP_CAVIUM_CN30XX:
897 case PRID_IMP_CAVIUM_CN58XX:
898 case PRID_IMP_CAVIUM_CN56XX:
899 case PRID_IMP_CAVIUM_CN50XX:
900 case PRID_IMP_CAVIUM_CN52XX:
901 c->cputype = CPU_CAVIUM_OCTEON;
902 __cpu_name[cpu] = "Cavium Octeon";
903 break;
904 default:
905 printk(KERN_INFO "Unknown Octeon chip!\n");
906 c->cputype = CPU_UNKNOWN;
907 break;
908 }
909}
910
9966db25
RB		 911const char *__cpu_name[NR_CPUS];
912
234fcd14 913__cpuinit void cpu_probe(void)
1da177e4
LT		 914{
915 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 916 unsigned int cpu = smp_processor_id();
1da177e4
LT		 917
918 c->processor_id = PRID_IMP_UNKNOWN;
919 c->fpu_id = FPIR_IMP_NONE;
920 c->cputype = CPU_UNKNOWN;
921
922 c->processor_id = read_c0_prid();
923 switch (c->processor_id & 0xff0000) {
924 case PRID_COMP_LEGACY:
cea7e2df 925 cpu_probe_legacy(c, cpu);
1da177e4
LT		 926 break;
927 case PRID_COMP_MIPS:
cea7e2df 928 cpu_probe_mips(c, cpu);
1da177e4
LT		 929 break;
930 case PRID_COMP_ALCHEMY:
cea7e2df 931 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 932 break;
933 case PRID_COMP_SIBYTE:
cea7e2df 934 cpu_probe_sibyte(c, cpu);
1da177e4 935 break;
1c0c13eb 936 case PRID_COMP_BROADCOM:
cea7e2df 937 cpu_probe_broadcom(c, cpu);
1c0c13eb 938 break;
1da177e4 939 case PRID_COMP_SANDCRAFT:
cea7e2df 940 cpu_probe_sandcraft(c, cpu);
1da177e4 941 break;
a92b0588 942 case PRID_COMP_NXP:
cea7e2df 943 cpu_probe_nxp(c, cpu);
a3dddd56 944 break;
0dd4781b
DD		 945 case PRID_COMP_CAVIUM:
946 cpu_probe_cavium(c, cpu);
947 break;
1da177e4 948 }
dec8b1ca 949
cea7e2df
RB		 950 BUG_ON(!__cpu_name[cpu]);
951 BUG_ON(c->cputype == CPU_UNKNOWN);
952
dec8b1ca
FBH		 953 /*
954 * Platform code can force the cpu type to optimize code
955 * generation. In that case be sure the cpu type is correctly
956 * manually setup otherwise it could trigger some nasty bugs.
957 */
958 BUG_ON(current_cpu_type() != c->cputype);
959
4194318c 960 if (c->options & MIPS_CPU_FPU) {
1da177e4 961 c->fpu_id = cpu_get_fpu_id();
4194318c 962
e7958bb9 963 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
b4672d37
RB		 964 c->isa_level == MIPS_CPU_ISA_M32R2 ||
965 c->isa_level == MIPS_CPU_ISA_M64R1 ||
966 c->isa_level == MIPS_CPU_ISA_M64R2) {
4194318c
RB		 967 if (c->fpu_id & MIPS_FPIR_3D)
968 c->ases |= MIPS_ASE_MIPS3D;
969 }
970 }
9966db25 971
f6771dbb
RB		 972 if (cpu_has_mips_r2)
973 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
974 else
975 c->srsets = 1;
1da177e4
LT		 976}
977
234fcd14 978__cpuinit void cpu_report(void)
1da177e4
LT		 979{
980 struct cpuinfo_mips *c = &current_cpu_data;
981
9966db25
RB		 982 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
983 c->processor_id, cpu_name_string());
1da177e4 984 if (c->options & MIPS_CPU_FPU)
9966db25 985 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1da177e4 986}
Linux 6.x block layer and io_uring tree(s)