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[MIPS] Add missing 34K processor IDs
[linux-2.6-block.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
4194318c 7 * Copyright (C) 2001, 2004 MIPS Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14#include <linux/config.h>
15#include <linux/init.h>
16#include <linux/kernel.h>
17#include <linux/ptrace.h>
18#include <linux/stddef.h>
19
1da177e4
LT		 20#include <asm/cpu.h>
21#include <asm/fpu.h>
22#include <asm/mipsregs.h>
23#include <asm/system.h>
24
25/*
26 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
27 * the implementation of the "wait" feature differs between CPU families. This
28 * points to the function that implements CPU specific wait.
29 * The wait instruction stops the pipeline and reduces the power consumption of
30 * the CPU very much.
31 */
32void (*cpu_wait)(void) = NULL;
33
34static void r3081_wait(void)
35{
36 unsigned long cfg = read_c0_conf();
37 write_c0_conf(cfg | R30XX_CONF_HALT);
38}
39
40static void r39xx_wait(void)
41{
42 unsigned long cfg = read_c0_conf();
43 write_c0_conf(cfg | TX39_CONF_HALT);
44}
45
46static void r4k_wait(void)
47{
48 __asm__(".set\tmips3\n\t"
49 "wait\n\t"
50 ".set\tmips0");
51}
52
494900af
PP		 53/* The Au1xxx wait is available only if using 32khz counter or
54 * external timer source, but specifically not CP0 Counter. */
fe359bf5 55int allow_au1k_wait;
10f650db 56
494900af 57static void au1k_wait(void)
1da177e4 58{
1da177e4 59 /* using the wait instruction makes CP0 counter unusable */
10f650db
RB		 60 __asm__(".set mips3\n\t"
61 "cache 0x14, 0(%0)\n\t"
62 "cache 0x14, 32(%0)\n\t"
494900af
PP		 63 "sync\n\t"
64 "nop\n\t"
1da177e4
LT		 65 "wait\n\t"
66 "nop\n\t"
67 "nop\n\t"
68 "nop\n\t"
69 "nop\n\t"
494900af 70 ".set mips0\n\t"
10f650db 71 : : "r" (au1k_wait));
1da177e4
LT		 72}
73
55d04dff
RB		 74static int __initdata nowait = 0;
75
76int __init wait_disable(char *s)
77{
78 nowait = 1;
79
80 return 1;
81}
82
83__setup("nowait", wait_disable);
84
1da177e4
LT		 85static inline void check_wait(void)
86{
87 struct cpuinfo_mips *c = &current_cpu_data;
88
89 printk("Checking for 'wait' instruction... ");
55d04dff
RB		 90 if (nowait) {
91 printk (" disabled.\n");
92 return;
93 }
94
1da177e4
LT		 95 switch (c->cputype) {
96 case CPU_R3081:
97 case CPU_R3081E:
98 cpu_wait = r3081_wait;
99 printk(" available.\n");
100 break;
101 case CPU_TX3927:
102 cpu_wait = r39xx_wait;
103 printk(" available.\n");
104 break;
105 case CPU_R4200:
106/* case CPU_R4300: */
107 case CPU_R4600:
108 case CPU_R4640:
109 case CPU_R4650:
110 case CPU_R4700:
111 case CPU_R5000:
112 case CPU_NEVADA:
113 case CPU_RM7000:
114 case CPU_RM9000:
115 case CPU_TX49XX:
116 case CPU_4KC:
117 case CPU_4KEC:
118 case CPU_4KSC:
119 case CPU_5KC:
120/* case CPU_20KC:*/
121 case CPU_24K:
122 case CPU_25KF:
bbc7f22f 123 case CPU_34K:
bdf21b18 124 case CPU_PR4450:
1da177e4
LT		 125 cpu_wait = r4k_wait;
126 printk(" available.\n");
127 break;
1da177e4
LT		 128 case CPU_AU1000:
129 case CPU_AU1100:
130 case CPU_AU1500:
e3ad1c23
PP		 131 case CPU_AU1550:
132 case CPU_AU1200:
fe359bf5
PP		 133 if (allow_au1k_wait) {
134 cpu_wait = au1k_wait;
135 printk(" available.\n");
136 } else
137 printk(" unavailable.\n");
1da177e4 138 break;
1da177e4
LT		 139 default:
140 printk(" unavailable.\n");
141 break;
142 }
143}
144
145void __init check_bugs32(void)
146{
147 check_wait();
148}
149
150/*
151 * Probe whether cpu has config register by trying to play with
152 * alternate cache bit and see whether it matters.
153 * It's used by cpu_probe to distinguish between R3000A and R3081.
154 */
155static inline int cpu_has_confreg(void)
156{
157#ifdef CONFIG_CPU_R3000
158 extern unsigned long r3k_cache_size(unsigned long);
159 unsigned long size1, size2;
160 unsigned long cfg = read_c0_conf();
161
162 size1 = r3k_cache_size(ST0_ISC);
163 write_c0_conf(cfg ^ R30XX_CONF_AC);
164 size2 = r3k_cache_size(ST0_ISC);
165 write_c0_conf(cfg);
166 return size1 != size2;
167#else
168 return 0;
169#endif
170}
171
172/*
173 * Get the FPU Implementation/Revision.
174 */
175static inline unsigned long cpu_get_fpu_id(void)
176{
177 unsigned long tmp, fpu_id;
178
179 tmp = read_c0_status();
180 __enable_fpu();
181 fpu_id = read_32bit_cp1_register(CP1_REVISION);
182 write_c0_status(tmp);
183 return fpu_id;
184}
185
186/*
187 * Check the CPU has an FPU the official way.
188 */
189static inline int __cpu_has_fpu(void)
190{
191 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
192}
193
02cf2119 194#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 195 | MIPS_CPU_COUNTER)
196
197static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
198{
199 switch (c->processor_id & 0xff00) {
200 case PRID_IMP_R2000:
201 c->cputype = CPU_R2000;
202 c->isa_level = MIPS_CPU_ISA_I;
02cf2119
RB		 203 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
204 MIPS_CPU_NOFPUEX;
1da177e4
LT		 205 if (__cpu_has_fpu())
206 c->options |= MIPS_CPU_FPU;
207 c->tlbsize = 64;
208 break;
209 case PRID_IMP_R3000:
210 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
211 if (cpu_has_confreg())
212 c->cputype = CPU_R3081E;
213 else
214 c->cputype = CPU_R3000A;
215 else
216 c->cputype = CPU_R3000;
217 c->isa_level = MIPS_CPU_ISA_I;
02cf2119
RB		 218 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
219 MIPS_CPU_NOFPUEX;
1da177e4
LT		 220 if (__cpu_has_fpu())
221 c->options |= MIPS_CPU_FPU;
222 c->tlbsize = 64;
223 break;
224 case PRID_IMP_R4000:
225 if (read_c0_config() & CONF_SC) {
226 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
227 c->cputype = CPU_R4400PC;
228 else
229 c->cputype = CPU_R4000PC;
230 } else {
231 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
232 c->cputype = CPU_R4400SC;
233 else
234 c->cputype = CPU_R4000SC;
235 }
236
237 c->isa_level = MIPS_CPU_ISA_III;
238 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
239 MIPS_CPU_WATCH | MIPS_CPU_VCE |
240 MIPS_CPU_LLSC;
241 c->tlbsize = 48;
242 break;
243 case PRID_IMP_VR41XX:
244 switch (c->processor_id & 0xf0) {
1da177e4
LT		 245 case PRID_REV_VR4111:
246 c->cputype = CPU_VR4111;
247 break;
1da177e4
LT		 248 case PRID_REV_VR4121:
249 c->cputype = CPU_VR4121;
250 break;
251 case PRID_REV_VR4122:
252 if ((c->processor_id & 0xf) < 0x3)
253 c->cputype = CPU_VR4122;
254 else
255 c->cputype = CPU_VR4181A;
256 break;
257 case PRID_REV_VR4130:
258 if ((c->processor_id & 0xf) < 0x4)
259 c->cputype = CPU_VR4131;
260 else
261 c->cputype = CPU_VR4133;
262 break;
263 default:
264 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
265 c->cputype = CPU_VR41XX;
266 break;
267 }
268 c->isa_level = MIPS_CPU_ISA_III;
269 c->options = R4K_OPTS;
270 c->tlbsize = 32;
271 break;
272 case PRID_IMP_R4300:
273 c->cputype = CPU_R4300;
274 c->isa_level = MIPS_CPU_ISA_III;
275 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
276 MIPS_CPU_LLSC;
277 c->tlbsize = 32;
278 break;
279 case PRID_IMP_R4600:
280 c->cputype = CPU_R4600;
281 c->isa_level = MIPS_CPU_ISA_III;
075e7502
TS		 282 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
283 MIPS_CPU_LLSC;
1da177e4
LT		 284 c->tlbsize = 48;
285 break;
286 #if 0
287 case PRID_IMP_R4650:
288 /*
289 * This processor doesn't have an MMU, so it's not
290 * "real easy" to run Linux on it. It is left purely
291 * for documentation. Commented out because it shares
292 * it's c0_prid id number with the TX3900.
293 */
a3dddd56 294 c->cputype = CPU_R4650;
1da177e4
LT		 295 c->isa_level = MIPS_CPU_ISA_III;
296 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
297 c->tlbsize = 48;
298 break;
299 #endif
300 case PRID_IMP_TX39:
301 c->isa_level = MIPS_CPU_ISA_I;
02cf2119 302 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 303
304 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
305 c->cputype = CPU_TX3927;
306 c->tlbsize = 64;
307 } else {
308 switch (c->processor_id & 0xff) {
309 case PRID_REV_TX3912:
310 c->cputype = CPU_TX3912;
311 c->tlbsize = 32;
312 break;
313 case PRID_REV_TX3922:
314 c->cputype = CPU_TX3922;
315 c->tlbsize = 64;
316 break;
317 default:
318 c->cputype = CPU_UNKNOWN;
319 break;
320 }
321 }
322 break;
323 case PRID_IMP_R4700:
324 c->cputype = CPU_R4700;
325 c->isa_level = MIPS_CPU_ISA_III;
326 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
327 MIPS_CPU_LLSC;
328 c->tlbsize = 48;
329 break;
330 case PRID_IMP_TX49:
331 c->cputype = CPU_TX49XX;
332 c->isa_level = MIPS_CPU_ISA_III;
333 c->options = R4K_OPTS | MIPS_CPU_LLSC;
334 if (!(c->processor_id & 0x08))
335 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
336 c->tlbsize = 48;
337 break;
338 case PRID_IMP_R5000:
339 c->cputype = CPU_R5000;
340 c->isa_level = MIPS_CPU_ISA_IV;
341 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
342 MIPS_CPU_LLSC;
343 c->tlbsize = 48;
344 break;
345 case PRID_IMP_R5432:
346 c->cputype = CPU_R5432;
347 c->isa_level = MIPS_CPU_ISA_IV;
348 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
349 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
350 c->tlbsize = 48;
351 break;
352 case PRID_IMP_R5500:
353 c->cputype = CPU_R5500;
354 c->isa_level = MIPS_CPU_ISA_IV;
355 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
356 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
357 c->tlbsize = 48;
358 break;
359 case PRID_IMP_NEVADA:
360 c->cputype = CPU_NEVADA;
361 c->isa_level = MIPS_CPU_ISA_IV;
362 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
363 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
364 c->tlbsize = 48;
365 break;
366 case PRID_IMP_R6000:
367 c->cputype = CPU_R6000;
368 c->isa_level = MIPS_CPU_ISA_II;
369 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
370 MIPS_CPU_LLSC;
371 c->tlbsize = 32;
372 break;
373 case PRID_IMP_R6000A:
374 c->cputype = CPU_R6000A;
375 c->isa_level = MIPS_CPU_ISA_II;
376 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
377 MIPS_CPU_LLSC;
378 c->tlbsize = 32;
379 break;
380 case PRID_IMP_RM7000:
381 c->cputype = CPU_RM7000;
382 c->isa_level = MIPS_CPU_ISA_IV;
383 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
384 MIPS_CPU_LLSC;
385 /*
386 * Undocumented RM7000: Bit 29 in the info register of
387 * the RM7000 v2.0 indicates if the TLB has 48 or 64
388 * entries.
389 *
390 * 29 1 => 64 entry JTLB
391 * 0 => 48 entry JTLB
392 */
393 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
394 break;
395 case PRID_IMP_RM9000:
396 c->cputype = CPU_RM9000;
397 c->isa_level = MIPS_CPU_ISA_IV;
398 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
399 MIPS_CPU_LLSC;
400 /*
401 * Bit 29 in the info register of the RM9000
402 * indicates if the TLB has 48 or 64 entries.
403 *
404 * 29 1 => 64 entry JTLB
405 * 0 => 48 entry JTLB
406 */
407 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
408 break;
409 case PRID_IMP_R8000:
410 c->cputype = CPU_R8000;
411 c->isa_level = MIPS_CPU_ISA_IV;
412 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
413 MIPS_CPU_FPU | MIPS_CPU_32FPR |
414 MIPS_CPU_LLSC;
415 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
416 break;
417 case PRID_IMP_R10000:
418 c->cputype = CPU_R10000;
419 c->isa_level = MIPS_CPU_ISA_IV;
8b36612a 420 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1da177e4
LT		 421 MIPS_CPU_FPU | MIPS_CPU_32FPR |
422 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
423 MIPS_CPU_LLSC;
424 c->tlbsize = 64;
425 break;
426 case PRID_IMP_R12000:
427 c->cputype = CPU_R12000;
428 c->isa_level = MIPS_CPU_ISA_IV;
8b36612a 429 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1da177e4
LT		 430 MIPS_CPU_FPU | MIPS_CPU_32FPR |
431 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
432 MIPS_CPU_LLSC;
433 c->tlbsize = 64;
434 break;
435 }
436}
437
b4672d37
RB		 438static char unknown_isa[] __initdata = KERN_ERR \
439 "Unsupported ISA type, c0.config0: %d.";
440
4194318c 441static inline unsigned int decode_config0(struct cpuinfo_mips *c)
1da177e4 442{
4194318c
RB		 443 unsigned int config0;
444 int isa;
1da177e4 445
4194318c
RB		 446 config0 = read_c0_config();
447
448 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
02cf2119 449 c->options |= MIPS_CPU_TLB;
4194318c
RB		 450 isa = (config0 & MIPS_CONF_AT) >> 13;
451 switch (isa) {
452 case 0:
b4672d37
RB		 453 switch ((config0 >> 10) & 7) {
454 case 0:
455 c->isa_level = MIPS_CPU_ISA_M32R1;
456 break;
457 case 1:
458 c->isa_level = MIPS_CPU_ISA_M32R2;
459 break;
460 default:
461 goto unknown;
462 }
4194318c
RB		 463 break;
464 case 2:
b4672d37
RB		 465 switch ((config0 >> 10) & 7) {
466 case 0:
467 c->isa_level = MIPS_CPU_ISA_M64R1;
468 break;
469 case 1:
470 c->isa_level = MIPS_CPU_ISA_M64R2;
471 break;
472 default:
473 goto unknown;
474 }
4194318c
RB		 475 break;
476 default:
b4672d37 477 goto unknown;
4194318c
RB		 478 }
479
480 return config0 & MIPS_CONF_M;
b4672d37
RB		 481
482unknown:
483 panic(unknown_isa, config0);
4194318c
RB		 484}
485
486static inline unsigned int decode_config1(struct cpuinfo_mips *c)
487{
488 unsigned int config1;
1da177e4 489
1da177e4 490 config1 = read_c0_config1();
4194318c
RB		 491
492 if (config1 & MIPS_CONF1_MD)
493 c->ases |= MIPS_ASE_MDMX;
494 if (config1 & MIPS_CONF1_WR)
1da177e4 495 c->options |= MIPS_CPU_WATCH;
4194318c
RB		 496 if (config1 & MIPS_CONF1_CA)
497 c->ases |= MIPS_ASE_MIPS16;
498 if (config1 & MIPS_CONF1_EP)
1da177e4 499 c->options |= MIPS_CPU_EJTAG;
4194318c 500 if (config1 & MIPS_CONF1_FP) {
1da177e4
LT		 501 c->options |= MIPS_CPU_FPU;
502 c->options |= MIPS_CPU_32FPR;
503 }
4194318c
RB		 504 if (cpu_has_tlb)
505 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
506
507 return config1 & MIPS_CONF_M;
508}
509
510static inline unsigned int decode_config2(struct cpuinfo_mips *c)
511{
512 unsigned int config2;
513
514 config2 = read_c0_config2();
515
516 if (config2 & MIPS_CONF2_SL)
517 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
518
519 return config2 & MIPS_CONF_M;
520}
521
522static inline unsigned int decode_config3(struct cpuinfo_mips *c)
523{
524 unsigned int config3;
525
526 config3 = read_c0_config3();
527
528 if (config3 & MIPS_CONF3_SM)
529 c->ases |= MIPS_ASE_SMARTMIPS;
e50c0a8f
RB		 530 if (config3 & MIPS_CONF3_DSP)
531 c->ases |= MIPS_ASE_DSP;
8f40611d
RB		 532 if (config3 & MIPS_CONF3_VINT)
533 c->options |= MIPS_CPU_VINT;
534 if (config3 & MIPS_CONF3_VEIC)
535 c->options |= MIPS_CPU_VEIC;
536 if (config3 & MIPS_CONF3_MT)
537 c->ases |= MIPS_ASE_MIPSMT;
4194318c
RB		 538
539 return config3 & MIPS_CONF_M;
540}
541
542static inline void decode_configs(struct cpuinfo_mips *c)
543{
544 /* MIPS32 or MIPS64 compliant CPU. */
02cf2119
RB		 545 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
546 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
4194318c 547
1da177e4
LT		 548 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
549
4194318c
RB		 550 /* Read Config registers. */
551 if (!decode_config0(c))
552 return; /* actually worth a panic() */
553 if (!decode_config1(c))
554 return;
555 if (!decode_config2(c))
556 return;
557 if (!decode_config3(c))
558 return;
1da177e4
LT		 559}
560
561static inline void cpu_probe_mips(struct cpuinfo_mips *c)
562{
4194318c 563 decode_configs(c);
1da177e4
LT		 564 switch (c->processor_id & 0xff00) {
565 case PRID_IMP_4KC:
566 c->cputype = CPU_4KC;
1da177e4
LT		 567 break;
568 case PRID_IMP_4KEC:
569 c->cputype = CPU_4KEC;
1da177e4 570 break;
2b07bd02
RB		 571 case PRID_IMP_4KECR2:
572 c->cputype = CPU_4KEC;
2b07bd02 573 break;
1da177e4 574 case PRID_IMP_4KSC:
8afcb5d8 575 case PRID_IMP_4KSD:
1da177e4 576 c->cputype = CPU_4KSC;
1da177e4
LT		 577 break;
578 case PRID_IMP_5KC:
579 c->cputype = CPU_5KC;
1da177e4
LT		 580 break;
581 case PRID_IMP_20KC:
582 c->cputype = CPU_20KC;
1da177e4
LT		 583 break;
584 case PRID_IMP_24K:
e50c0a8f 585 case PRID_IMP_24KE:
1da177e4 586 c->cputype = CPU_24K;
1da177e4
LT		 587 break;
588 case PRID_IMP_25KF:
589 c->cputype = CPU_25KF;
1da177e4
LT		 590 /* Probe for L2 cache */
591 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
592 break;
bbc7f22f
RB		 593 case PRID_IMP_34K:
594 c->cputype = CPU_34K;
bbc7f22f 595 break;
1da177e4
LT		 596 }
597}
598
599static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
600{
4194318c 601 decode_configs(c);
1da177e4
LT		 602 switch (c->processor_id & 0xff00) {
603 case PRID_IMP_AU1_REV1:
604 case PRID_IMP_AU1_REV2:
605 switch ((c->processor_id >> 24) & 0xff) {
606 case 0:
a3dddd56 607 c->cputype = CPU_AU1000;
1da177e4
LT		 608 break;
609 case 1:
610 c->cputype = CPU_AU1500;
611 break;
612 case 2:
613 c->cputype = CPU_AU1100;
614 break;
615 case 3:
616 c->cputype = CPU_AU1550;
617 break;
e3ad1c23
PP		 618 case 4:
619 c->cputype = CPU_AU1200;
620 break;
1da177e4
LT		 621 default:
622 panic("Unknown Au Core!");
623 break;
624 }
1da177e4
LT		 625 break;
626 }
627}
628
629static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
630{
4194318c 631 decode_configs(c);
02cf2119
RB		 632
633 /*
634 * For historical reasons the SB1 comes with it's own variant of
635 * cache code which eventually will be folded into c-r4k.c. Until
636 * then we pretend it's got it's own cache architecture.
637 */
d121ced2 638 c->options &= ~MIPS_CPU_4K_CACHE;
02cf2119
RB		 639 c->options |= MIPS_CPU_SB1_CACHE;
640
1da177e4
LT		 641 switch (c->processor_id & 0xff00) {
642 case PRID_IMP_SB1:
643 c->cputype = CPU_SB1;
1da177e4 644 /* FPU in pass1 is known to have issues. */
010b853b
RB		 645 if ((c->processor_id & 0xff) < 0x20)
646 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 647 break;
93ce2f52
AI		 648 case PRID_IMP_SB1A:
649 c->cputype = CPU_SB1A;
650 break;
1da177e4
LT		 651 }
652}
653
654static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
655{
4194318c 656 decode_configs(c);
1da177e4
LT		 657 switch (c->processor_id & 0xff00) {
658 case PRID_IMP_SR71000:
659 c->cputype = CPU_SR71000;
1da177e4
LT		 660 c->scache.ways = 8;
661 c->tlbsize = 64;
662 break;
663 }
664}
665
bdf21b18
PP		 666static inline void cpu_probe_philips(struct cpuinfo_mips *c)
667{
668 decode_configs(c);
669 switch (c->processor_id & 0xff00) {
670 case PRID_IMP_PR4450:
671 c->cputype = CPU_PR4450;
e7958bb9 672 c->isa_level = MIPS_CPU_ISA_M32R1;
bdf21b18
PP		 673 break;
674 default:
675 panic("Unknown Philips Core!"); /* REVISIT: die? */
676 break;
677 }
678}
679
680
1da177e4
LT		 681__init void cpu_probe(void)
682{
683 struct cpuinfo_mips *c = &current_cpu_data;
684
685 c->processor_id = PRID_IMP_UNKNOWN;
686 c->fpu_id = FPIR_IMP_NONE;
687 c->cputype = CPU_UNKNOWN;
688
689 c->processor_id = read_c0_prid();
690 switch (c->processor_id & 0xff0000) {
691 case PRID_COMP_LEGACY:
692 cpu_probe_legacy(c);
693 break;
694 case PRID_COMP_MIPS:
695 cpu_probe_mips(c);
696 break;
697 case PRID_COMP_ALCHEMY:
698 cpu_probe_alchemy(c);
699 break;
700 case PRID_COMP_SIBYTE:
701 cpu_probe_sibyte(c);
702 break;
1da177e4
LT		 703 case PRID_COMP_SANDCRAFT:
704 cpu_probe_sandcraft(c);
705 break;
bdf21b18
PP		 706 case PRID_COMP_PHILIPS:
707 cpu_probe_philips(c);
a3dddd56 708 break;
1da177e4
LT		 709 default:
710 c->cputype = CPU_UNKNOWN;
711 }
4194318c 712 if (c->options & MIPS_CPU_FPU) {
1da177e4 713 c->fpu_id = cpu_get_fpu_id();
4194318c 714
e7958bb9 715 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
b4672d37
RB		 716 c->isa_level == MIPS_CPU_ISA_M32R2 ||
717 c->isa_level == MIPS_CPU_ISA_M64R1 ||
718 c->isa_level == MIPS_CPU_ISA_M64R2) {
4194318c
RB		 719 if (c->fpu_id & MIPS_FPIR_3D)
720 c->ases |= MIPS_ASE_MIPS3D;
721 }
722 }
1da177e4
LT		 723}
724
725__init void cpu_report(void)
726{
727 struct cpuinfo_mips *c = &current_cpu_data;
728
729 printk("CPU revision is: %08x\n", c->processor_id);
730 if (c->options & MIPS_CPU_FPU)
731 printk("FPU revision is: %08x\n", c->fpu_id);
732}
Linux 6.x block layer and io_uring tree(s)