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MIPS: Add default case for the FTLB enable/disable code
[linux-2.6-block.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
70342287 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4 22#include <asm/cpu.h>
f6843626 23#include <asm/cpu-features.h>
69f24d17 24#include <asm/cpu-type.h>
1da177e4
LT		 25#include <asm/fpu.h>
26#include <asm/mipsregs.h>
30ee615b 27#include <asm/mipsmtregs.h>
a5e9a69e 28#include <asm/msa.h>
654f57bf 29#include <asm/watch.h>
06372a63 30#include <asm/elf.h>
4f12b91d 31#include <asm/pgtable-bits.h>
a074f0e8 32#include <asm/spram.h>
949e51be
DD		 33#include <asm/uaccess.h>
34
7aecd5ca
MR		 35/*
36 * Get the FPU Implementation/Revision.
37 */
38static inline unsigned long cpu_get_fpu_id(void)
39{
40 unsigned long tmp, fpu_id;
41
42 tmp = read_c0_status();
43 __enable_fpu(FPU_AS_IS);
44 fpu_id = read_32bit_cp1_register(CP1_REVISION);
45 write_c0_status(tmp);
46 return fpu_id;
47}
48
49/*
50 * Check if the CPU has an external FPU.
51 */
52static inline int __cpu_has_fpu(void)
53{
54 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
55}
56
57static inline unsigned long cpu_get_msa_id(void)
58{
59 unsigned long status, msa_id;
60
61 status = read_c0_status();
62 __enable_fpu(FPU_64BIT);
63 enable_msa();
64 msa_id = read_msa_ir();
65 disable_msa();
66 write_c0_status(status);
67 return msa_id;
68}
69
9b26616c
MR		 70/*
71 * Determine the FCSR mask for FPU hardware.
72 */
73static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
74{
75 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
76
90b712dd 77 fcsr = c->fpu_csr31;
9b26616c
MR		 78 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
79
80 sr = read_c0_status();
81 __enable_fpu(FPU_AS_IS);
82
9b26616c
MR		 83 fcsr0 = fcsr & mask;
84 write_32bit_cp1_register(CP1_STATUS, fcsr0);
85 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
86
87 fcsr1 = fcsr | ~mask;
88 write_32bit_cp1_register(CP1_STATUS, fcsr1);
89 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
90
91 write_32bit_cp1_register(CP1_STATUS, fcsr);
92
93 write_c0_status(sr);
94
95 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
96}
97
f6843626
MR		 98/*
99 * Set the FIR feature flags for the FPU emulator.
100 */
101static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
102{
103 u32 value;
104
105 value = 0;
106 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
107 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
108 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
109 value |= MIPS_FPIR_D | MIPS_FPIR_S;
110 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
111 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
112 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
113 c->fpu_id = value;
114}
115
9b26616c
MR		 116/* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
117static unsigned int mips_nofpu_msk31;
118
7aecd5ca
MR		 119/*
120 * Set options for FPU hardware.
121 */
122static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
123{
124 c->fpu_id = cpu_get_fpu_id();
125 mips_nofpu_msk31 = c->fpu_msk31;
126
127 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
128 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
129 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
130 if (c->fpu_id & MIPS_FPIR_3D)
131 c->ases |= MIPS_ASE_MIPS3D;
132 if (c->fpu_id & MIPS_FPIR_FREP)
133 c->options |= MIPS_CPU_FRE;
134 }
135
136 cpu_set_fpu_fcsr_mask(c);
137}
138
139/*
140 * Set options for the FPU emulator.
141 */
142static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
143{
144 c->options &= ~MIPS_CPU_FPU;
145 c->fpu_msk31 = mips_nofpu_msk31;
146
147 cpu_set_nofpu_id(c);
148}
149
078a55fc 150static int mips_fpu_disabled;
0103d23f
KC		 151
152static int __init fpu_disable(char *s)
153{
7aecd5ca 154 cpu_set_nofpu_opts(&boot_cpu_data);
0103d23f
KC		 155 mips_fpu_disabled = 1;
156
157 return 1;
158}
159
160__setup("nofpu", fpu_disable);
161
078a55fc 162int mips_dsp_disabled;
0103d23f
KC		 163
164static int __init dsp_disable(char *s)
165{
ee80f7c7 166 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f
KC		 167 mips_dsp_disabled = 1;
168
169 return 1;
170}
171
172__setup("nodsp", dsp_disable);
173
3d528b32
MC		 174static int mips_htw_disabled;
175
176static int __init htw_disable(char *s)
177{
178 mips_htw_disabled = 1;
179 cpu_data[0].options &= ~MIPS_CPU_HTW;
180 write_c0_pwctl(read_c0_pwctl() &
181 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
182
183 return 1;
184}
185
186__setup("nohtw", htw_disable);
187
97f4ad29
MC		 188static int mips_ftlb_disabled;
189static int mips_has_ftlb_configured;
190
912708c2 191static int set_ftlb_enable(struct cpuinfo_mips *c, int enable);
97f4ad29
MC		 192
193static int __init ftlb_disable(char *s)
194{
195 unsigned int config4, mmuextdef;
196
197 /*
198 * If the core hasn't done any FTLB configuration, there is nothing
199 * for us to do here.
200 */
201 if (!mips_has_ftlb_configured)
202 return 1;
203
204 /* Disable it in the boot cpu */
912708c2
MC		 205 if (set_ftlb_enable(&cpu_data[0], 0)) {
206 pr_warn("Can't turn FTLB off\n");
207 return 1;
208 }
97f4ad29
MC		 209
210 back_to_back_c0_hazard();
211
212 config4 = read_c0_config4();
213
214 /* Check that FTLB has been disabled */
215 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
216 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
217 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
218 /* This should never happen */
219 pr_warn("FTLB could not be disabled!\n");
220 return 1;
221 }
222
223 mips_ftlb_disabled = 1;
224 mips_has_ftlb_configured = 0;
225
226 /*
227 * noftlb is mainly used for debug purposes so print
228 * an informative message instead of using pr_debug()
229 */
230 pr_info("FTLB has been disabled\n");
231
232 /*
233 * Some of these bits are duplicated in the decode_config4.
234 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
235 * once FTLB has been disabled so undo what decode_config4 did.
236 */
237 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
238 cpu_data[0].tlbsizeftlbsets;
239 cpu_data[0].tlbsizeftlbsets = 0;
240 cpu_data[0].tlbsizeftlbways = 0;
241
242 return 1;
243}
244
245__setup("noftlb", ftlb_disable);
246
247
9267a30d
MSJ		 248static inline void check_errata(void)
249{
250 struct cpuinfo_mips *c = &current_cpu_data;
251
69f24d17 252 switch (current_cpu_type()) {
9267a30d
MSJ		 253 case CPU_34K:
254 /*
255 * Erratum "RPS May Cause Incorrect Instruction Execution"
b633648c 256 * This code only handles VPE0, any SMP/RTOS code
9267a30d
MSJ		 257 * making use of VPE1 will be responsable for that VPE.
258 */
259 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
260 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
261 break;
262 default:
263 break;
264 }
265}
266
1da177e4
LT		 267void __init check_bugs32(void)
268{
9267a30d 269 check_errata();
1da177e4
LT		 270}
271
272/*
273 * Probe whether cpu has config register by trying to play with
274 * alternate cache bit and see whether it matters.
275 * It's used by cpu_probe to distinguish between R3000A and R3081.
276 */
277static inline int cpu_has_confreg(void)
278{
279#ifdef CONFIG_CPU_R3000
280 extern unsigned long r3k_cache_size(unsigned long);
281 unsigned long size1, size2;
282 unsigned long cfg = read_c0_conf();
283
284 size1 = r3k_cache_size(ST0_ISC);
285 write_c0_conf(cfg ^ R30XX_CONF_AC);
286 size2 = r3k_cache_size(ST0_ISC);
287 write_c0_conf(cfg);
288 return size1 != size2;
289#else
290 return 0;
291#endif
292}
293
c094c99e
RM		 294static inline void set_elf_platform(int cpu, const char *plat)
295{
296 if (cpu == 0)
297 __elf_platform = plat;
298}
299
91dfc423
GR		 300static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
301{
302#ifdef __NEED_VMBITS_PROBE
5b7efa89 303 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 304 back_to_back_c0_hazard();
5b7efa89 305 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 306#endif
307}
308
078a55fc 309static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
a96102be
SH		 310{
311 switch (isa) {
312 case MIPS_CPU_ISA_M64R2:
313 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
314 case MIPS_CPU_ISA_M64R1:
315 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
316 case MIPS_CPU_ISA_V:
317 c->isa_level |= MIPS_CPU_ISA_V;
318 case MIPS_CPU_ISA_IV:
319 c->isa_level |= MIPS_CPU_ISA_IV;
320 case MIPS_CPU_ISA_III:
1990e542 321 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
a96102be
SH		 322 break;
323
8b8aa636
LY		 324 /* R6 incompatible with everything else */
325 case MIPS_CPU_ISA_M64R6:
326 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
327 case MIPS_CPU_ISA_M32R6:
328 c->isa_level |= MIPS_CPU_ISA_M32R6;
329 /* Break here so we don't add incompatible ISAs */
330 break;
a96102be
SH		 331 case MIPS_CPU_ISA_M32R2:
332 c->isa_level |= MIPS_CPU_ISA_M32R2;
333 case MIPS_CPU_ISA_M32R1:
334 c->isa_level |= MIPS_CPU_ISA_M32R1;
335 case MIPS_CPU_ISA_II:
336 c->isa_level |= MIPS_CPU_ISA_II;
a96102be
SH		 337 break;
338 }
339}
340
078a55fc 341static char unknown_isa[] = KERN_ERR \
2fa36399
KC		 342 "Unsupported ISA type, c0.config0: %d.";
343
cf0a8aa0
MC		 344static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
345{
346
347 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
348
349 /*
350 * 0 = All TLBWR instructions go to FTLB
351 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
352 * FTLB and 1 goes to the VTLB.
353 * 2 = 7:1: As above with 7:1 ratio.
354 * 3 = 3:1: As above with 3:1 ratio.
355 *
356 * Use the linear midpoint as the probability threshold.
357 */
358 if (probability >= 12)
359 return 1;
360 else if (probability >= 6)
361 return 2;
362 else
363 /*
364 * So FTLB is less than 4 times bigger than VTLB.
365 * A 3:1 ratio can still be useful though.
366 */
367 return 3;
368}
369
912708c2 370static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
75b5b5e0
LY		 371{
372 unsigned int config6;
d83b0e82
JH		 373
374 /* It's implementation dependent how the FTLB can be enabled */
375 switch (c->cputype) {
376 case CPU_PROAPTIV:
377 case CPU_P5600:
378 /* proAptiv & related cores use Config6 to enable the FTLB */
75b5b5e0 379 config6 = read_c0_config6();
cf0a8aa0
MC		 380 /* Clear the old probability value */
381 config6 &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
75b5b5e0
LY		 382 if (enable)
383 /* Enable FTLB */
cf0a8aa0
MC		 384 write_c0_config6(config6 |
385 (calculate_ftlb_probability(c)
386 << MIPS_CONF6_FTLBP_SHIFT)
387 | MIPS_CONF6_FTLBEN);
75b5b5e0
LY		 388 else
389 /* Disable FTLB */
390 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
d83b0e82 391 break;
912708c2
MC		 392 default:
393 return 1;
75b5b5e0 394 }
912708c2
MC		 395
396 return 0;
75b5b5e0
LY		 397}
398
2fa36399
KC		 399static inline unsigned int decode_config0(struct cpuinfo_mips *c)
400{
401 unsigned int config0;
402 int isa;
403
404 config0 = read_c0_config();
405
75b5b5e0
LY		 406 /*
407 * Look for Standard TLB or Dual VTLB and FTLB
408 */
409 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
410 (((config0 & MIPS_CONF_MT) >> 7) == 4))
2fa36399 411 c->options |= MIPS_CPU_TLB;
75b5b5e0 412
2fa36399
KC		 413 isa = (config0 & MIPS_CONF_AT) >> 13;
414 switch (isa) {
415 case 0:
416 switch ((config0 & MIPS_CONF_AR) >> 10) {
417 case 0:
a96102be 418 set_isa(c, MIPS_CPU_ISA_M32R1);
2fa36399
KC		 419 break;
420 case 1:
a96102be 421 set_isa(c, MIPS_CPU_ISA_M32R2);
2fa36399 422 break;
8b8aa636
LY		 423 case 2:
424 set_isa(c, MIPS_CPU_ISA_M32R6);
425 break;
2fa36399
KC		 426 default:
427 goto unknown;
428 }
429 break;
430 case 2:
431 switch ((config0 & MIPS_CONF_AR) >> 10) {
432 case 0:
a96102be 433 set_isa(c, MIPS_CPU_ISA_M64R1);
2fa36399
KC		 434 break;
435 case 1:
a96102be 436 set_isa(c, MIPS_CPU_ISA_M64R2);
2fa36399 437 break;
8b8aa636
LY		 438 case 2:
439 set_isa(c, MIPS_CPU_ISA_M64R6);
440 break;
2fa36399
KC		 441 default:
442 goto unknown;
443 }
444 break;
445 default:
446 goto unknown;
447 }
448
449 return config0 & MIPS_CONF_M;
450
451unknown:
452 panic(unknown_isa, config0);
453}
454
455static inline unsigned int decode_config1(struct cpuinfo_mips *c)
456{
457 unsigned int config1;
458
459 config1 = read_c0_config1();
460
461 if (config1 & MIPS_CONF1_MD)
462 c->ases |= MIPS_ASE_MDMX;
463 if (config1 & MIPS_CONF1_WR)
464 c->options |= MIPS_CPU_WATCH;
465 if (config1 & MIPS_CONF1_CA)
466 c->ases |= MIPS_ASE_MIPS16;
467 if (config1 & MIPS_CONF1_EP)
468 c->options |= MIPS_CPU_EJTAG;
469 if (config1 & MIPS_CONF1_FP) {
470 c->options |= MIPS_CPU_FPU;
471 c->options |= MIPS_CPU_32FPR;
472 }
75b5b5e0 473 if (cpu_has_tlb) {
2fa36399 474 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
75b5b5e0
LY		 475 c->tlbsizevtlb = c->tlbsize;
476 c->tlbsizeftlbsets = 0;
477 }
2fa36399
KC		 478
479 return config1 & MIPS_CONF_M;
480}
481
482static inline unsigned int decode_config2(struct cpuinfo_mips *c)
483{
484 unsigned int config2;
485
486 config2 = read_c0_config2();
487
488 if (config2 & MIPS_CONF2_SL)
489 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
490
491 return config2 & MIPS_CONF_M;
492}
493
494static inline unsigned int decode_config3(struct cpuinfo_mips *c)
495{
496 unsigned int config3;
497
498 config3 = read_c0_config3();
499
b2ab4f08 500 if (config3 & MIPS_CONF3_SM) {
2fa36399 501 c->ases |= MIPS_ASE_SMARTMIPS;
b2ab4f08
SH		 502 c->options |= MIPS_CPU_RIXI;
503 }
504 if (config3 & MIPS_CONF3_RXI)
505 c->options |= MIPS_CPU_RIXI;
2fa36399
KC		 506 if (config3 & MIPS_CONF3_DSP)
507 c->ases |= MIPS_ASE_DSP;
ee80f7c7
SH		 508 if (config3 & MIPS_CONF3_DSP2P)
509 c->ases |= MIPS_ASE_DSP2P;
2fa36399
KC		 510 if (config3 & MIPS_CONF3_VINT)
511 c->options |= MIPS_CPU_VINT;
512 if (config3 & MIPS_CONF3_VEIC)
513 c->options |= MIPS_CPU_VEIC;
514 if (config3 & MIPS_CONF3_MT)
515 c->ases |= MIPS_ASE_MIPSMT;
516 if (config3 & MIPS_CONF3_ULRI)
517 c->options |= MIPS_CPU_ULRI;
f8fa4811
SH		 518 if (config3 & MIPS_CONF3_ISA)
519 c->options |= MIPS_CPU_MICROMIPS;
1e7decdb
DD		 520 if (config3 & MIPS_CONF3_VZ)
521 c->ases |= MIPS_ASE_VZ;
4a0156fb
SH		 522 if (config3 & MIPS_CONF3_SC)
523 c->options |= MIPS_CPU_SEGMENTS;
a5e9a69e
PB		 524 if (config3 & MIPS_CONF3_MSA)
525 c->ases |= MIPS_ASE_MSA;
3d528b32 526 /* Only tested on 32-bit cores */
ed4cbc81
MC		 527 if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) {
528 c->htw_seq = 0;
3d528b32 529 c->options |= MIPS_CPU_HTW;
ed4cbc81 530 }
9b3274bd
JH		 531 if (config3 & MIPS_CONF3_CDMM)
532 c->options |= MIPS_CPU_CDMM;
2fa36399
KC		 533
534 return config3 & MIPS_CONF_M;
535}
536
537static inline unsigned int decode_config4(struct cpuinfo_mips *c)
538{
539 unsigned int config4;
75b5b5e0
LY		 540 unsigned int newcf4;
541 unsigned int mmuextdef;
542 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
2fa36399
KC		 543
544 config4 = read_c0_config4();
545
1745c1ef
LY		 546 if (cpu_has_tlb) {
547 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
548 c->options |= MIPS_CPU_TLBINV;
75b5b5e0
LY		 549 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
550 switch (mmuextdef) {
551 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
552 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
553 c->tlbsizevtlb = c->tlbsize;
554 break;
555 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
556 c->tlbsizevtlb +=
557 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
558 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
559 c->tlbsize = c->tlbsizevtlb;
560 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
561 /* fall through */
562 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
97f4ad29
MC		 563 if (mips_ftlb_disabled)
564 break;
75b5b5e0
LY		 565 newcf4 = (config4 & ~ftlb_page) |
566 (page_size_ftlb(mmuextdef) <<
567 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
568 write_c0_config4(newcf4);
569 back_to_back_c0_hazard();
570 config4 = read_c0_config4();
571 if (config4 != newcf4) {
572 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
573 PAGE_SIZE, config4);
574 /* Switch FTLB off */
575 set_ftlb_enable(c, 0);
576 break;
577 }
578 c->tlbsizeftlbsets = 1 <<
579 ((config4 & MIPS_CONF4_FTLBSETS) >>
580 MIPS_CONF4_FTLBSETS_SHIFT);
581 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
582 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
583 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
97f4ad29 584 mips_has_ftlb_configured = 1;
75b5b5e0
LY		 585 break;
586 }
1745c1ef
LY		 587 }
588
2fa36399
KC		 589 c->kscratch_mask = (config4 >> 16) & 0xff;
590
591 return config4 & MIPS_CONF_M;
592}
593
8b8a7634
RB		 594static inline unsigned int decode_config5(struct cpuinfo_mips *c)
595{
596 unsigned int config5;
597
598 config5 = read_c0_config5();
d175ed2b 599 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
8b8a7634
RB		 600 write_c0_config5(config5);
601
49016748
MC		 602 if (config5 & MIPS_CONF5_EVA)
603 c->options |= MIPS_CPU_EVA;
1f6c52ff
PB		 604 if (config5 & MIPS_CONF5_MRP)
605 c->options |= MIPS_CPU_MAAR;
5aed9da1
MC		 606 if (config5 & MIPS_CONF5_LLB)
607 c->options |= MIPS_CPU_RW_LLB;
c5b36783
SH		 608#ifdef CONFIG_XPA
609 if (config5 & MIPS_CONF5_MVH)
610 c->options |= MIPS_CPU_XPA;
611#endif
49016748 612
8b8a7634
RB		 613 return config5 & MIPS_CONF_M;
614}
615
078a55fc 616static void decode_configs(struct cpuinfo_mips *c)
2fa36399
KC		 617{
618 int ok;
619
620 /* MIPS32 or MIPS64 compliant CPU. */
621 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
622 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
623
624 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
625
97f4ad29
MC		 626 /* Enable FTLB if present and not disabled */
627 set_ftlb_enable(c, !mips_ftlb_disabled);
75b5b5e0 628
2fa36399 629 ok = decode_config0(c); /* Read Config registers. */
70342287 630 BUG_ON(!ok); /* Arch spec violation! */
2fa36399
KC		 631 if (ok)
632 ok = decode_config1(c);
633 if (ok)
634 ok = decode_config2(c);
635 if (ok)
636 ok = decode_config3(c);
637 if (ok)
638 ok = decode_config4(c);
8b8a7634
RB		 639 if (ok)
640 ok = decode_config5(c);
2fa36399
KC		 641
642 mips_probe_watch_registers(c);
643
6575b1d4
LY		 644 if (cpu_has_rixi) {
645 /* Enable the RIXI exceptions */
a5770df0 646 set_c0_pagegrain(PG_IEC);
6575b1d4
LY		 647 back_to_back_c0_hazard();
648 /* Verify the IEC bit is set */
649 if (read_c0_pagegrain() & PG_IEC)
650 c->options |= MIPS_CPU_RIXIEX;
651 }
652
0ee958e1 653#ifndef CONFIG_MIPS_CPS
8b8aa636 654 if (cpu_has_mips_r2_r6) {
45b585c8 655 c->core = get_ebase_cpunum();
30ee615b
PB		 656 if (cpu_has_mipsmt)
657 c->core >>= fls(core_nvpes()) - 1;
658 }
0ee958e1 659#endif
2fa36399
KC		 660}
661
02cf2119 662#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 663 | MIPS_CPU_COUNTER)
664
cea7e2df 665static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 666{
8ff374b9 667 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 668 case PRID_IMP_R2000:
669 c->cputype = CPU_R2000;
cea7e2df 670 __cpu_name[cpu] = "R2000";
9b26616c 671 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 672 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 673 MIPS_CPU_NOFPUEX;
1da177e4
LT		 674 if (__cpu_has_fpu())
675 c->options |= MIPS_CPU_FPU;
676 c->tlbsize = 64;
677 break;
678 case PRID_IMP_R3000:
8ff374b9 679 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
cea7e2df 680 if (cpu_has_confreg()) {
1da177e4 681 c->cputype = CPU_R3081E;
cea7e2df
RB		 682 __cpu_name[cpu] = "R3081";
683 } else {
1da177e4 684 c->cputype = CPU_R3000A;
cea7e2df
RB		 685 __cpu_name[cpu] = "R3000A";
686 }
cea7e2df 687 } else {
1da177e4 688 c->cputype = CPU_R3000;
cea7e2df
RB		 689 __cpu_name[cpu] = "R3000";
690 }
9b26616c 691 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 692 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 693 MIPS_CPU_NOFPUEX;
1da177e4
LT		 694 if (__cpu_has_fpu())
695 c->options |= MIPS_CPU_FPU;
696 c->tlbsize = 64;
697 break;
698 case PRID_IMP_R4000:
699 if (read_c0_config() & CONF_SC) {
8ff374b9
MR		 700 if ((c->processor_id & PRID_REV_MASK) >=
701 PRID_REV_R4400) {
1da177e4 702 c->cputype = CPU_R4400PC;
cea7e2df
RB		 703 __cpu_name[cpu] = "R4400PC";
704 } else {
1da177e4 705 c->cputype = CPU_R4000PC;
cea7e2df
RB		 706 __cpu_name[cpu] = "R4000PC";
707 }
1da177e4 708 } else {
7f177a52
MR		 709 int cca = read_c0_config() & CONF_CM_CMASK;
710 int mc;
711
712 /*
713 * SC and MC versions can't be reliably told apart,
714 * but only the latter support coherent caching
715 * modes so assume the firmware has set the KSEG0
716 * coherency attribute reasonably (if uncached, we
717 * assume SC).
718 */
719 switch (cca) {
720 case CONF_CM_CACHABLE_CE:
721 case CONF_CM_CACHABLE_COW:
722 case CONF_CM_CACHABLE_CUW:
723 mc = 1;
724 break;
725 default:
726 mc = 0;
727 break;
728 }
8ff374b9
MR		 729 if ((c->processor_id & PRID_REV_MASK) >=
730 PRID_REV_R4400) {
7f177a52
MR		 731 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
732 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
cea7e2df 733 } else {
7f177a52
MR		 734 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
735 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
cea7e2df 736 }
1da177e4
LT		 737 }
738
a96102be 739 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 740 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 741 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 742 MIPS_CPU_WATCH | MIPS_CPU_VCE |
743 MIPS_CPU_LLSC;
1da177e4
LT		 744 c->tlbsize = 48;
745 break;
746 case PRID_IMP_VR41XX:
9f91e506 747 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 748 c->fpu_msk31 |= FPU_CSR_CONDX;
9f91e506
YY		 749 c->options = R4K_OPTS;
750 c->tlbsize = 32;
1da177e4 751 switch (c->processor_id & 0xf0) {
1da177e4
LT		 752 case PRID_REV_VR4111:
753 c->cputype = CPU_VR4111;
cea7e2df 754 __cpu_name[cpu] = "NEC VR4111";
1da177e4 755 break;
1da177e4
LT		 756 case PRID_REV_VR4121:
757 c->cputype = CPU_VR4121;
cea7e2df 758 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 759 break;
760 case PRID_REV_VR4122:
cea7e2df 761 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 762 c->cputype = CPU_VR4122;
cea7e2df
RB		 763 __cpu_name[cpu] = "NEC VR4122";
764 } else {
1da177e4 765 c->cputype = CPU_VR4181A;
cea7e2df
RB		 766 __cpu_name[cpu] = "NEC VR4181A";
767 }
1da177e4
LT		 768 break;
769 case PRID_REV_VR4130:
cea7e2df 770 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 771 c->cputype = CPU_VR4131;
cea7e2df
RB		 772 __cpu_name[cpu] = "NEC VR4131";
773 } else {
1da177e4 774 c->cputype = CPU_VR4133;
9f91e506 775 c->options |= MIPS_CPU_LLSC;
cea7e2df
RB		 776 __cpu_name[cpu] = "NEC VR4133";
777 }
1da177e4
LT		 778 break;
779 default:
780 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
781 c->cputype = CPU_VR41XX;
cea7e2df 782 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 783 break;
784 }
1da177e4
LT		 785 break;
786 case PRID_IMP_R4300:
787 c->cputype = CPU_R4300;
cea7e2df 788 __cpu_name[cpu] = "R4300";
a96102be 789 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 790 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 791 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 792 MIPS_CPU_LLSC;
1da177e4
LT		 793 c->tlbsize = 32;
794 break;
795 case PRID_IMP_R4600:
796 c->cputype = CPU_R4600;
cea7e2df 797 __cpu_name[cpu] = "R4600";
a96102be 798 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 799 c->fpu_msk31 |= FPU_CSR_CONDX;
075e7502
TS		 800 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
801 MIPS_CPU_LLSC;
1da177e4
LT		 802 c->tlbsize = 48;
803 break;
804 #if 0
03751e79 805 case PRID_IMP_R4650:
1da177e4
LT		 806 /*
807 * This processor doesn't have an MMU, so it's not
808 * "real easy" to run Linux on it. It is left purely
809 * for documentation. Commented out because it shares
810 * it's c0_prid id number with the TX3900.
811 */
a3dddd56 812 c->cputype = CPU_R4650;
cea7e2df 813 __cpu_name[cpu] = "R4650";
a96102be 814 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 815 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 816 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 817 c->tlbsize = 48;
1da177e4
LT		 818 break;
819 #endif
820 case PRID_IMP_TX39:
9b26616c 821 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 822 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 823
824 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
825 c->cputype = CPU_TX3927;
cea7e2df 826 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 827 c->tlbsize = 64;
828 } else {
8ff374b9 829 switch (c->processor_id & PRID_REV_MASK) {
1da177e4
LT		 830 case PRID_REV_TX3912:
831 c->cputype = CPU_TX3912;
cea7e2df 832 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 833 c->tlbsize = 32;
834 break;
835 case PRID_REV_TX3922:
836 c->cputype = CPU_TX3922;
cea7e2df 837 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 838 c->tlbsize = 64;
839 break;
1da177e4
LT		 840 }
841 }
842 break;
843 case PRID_IMP_R4700:
844 c->cputype = CPU_R4700;
cea7e2df 845 __cpu_name[cpu] = "R4700";
a96102be 846 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 847 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 848 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 849 MIPS_CPU_LLSC;
1da177e4
LT		 850 c->tlbsize = 48;
851 break;
852 case PRID_IMP_TX49:
853 c->cputype = CPU_TX49XX;
cea7e2df 854 __cpu_name[cpu] = "R49XX";
a96102be 855 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 856 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4
LT		 857 c->options = R4K_OPTS | MIPS_CPU_LLSC;
858 if (!(c->processor_id & 0x08))
859 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
860 c->tlbsize = 48;
861 break;
862 case PRID_IMP_R5000:
863 c->cputype = CPU_R5000;
cea7e2df 864 __cpu_name[cpu] = "R5000";
a96102be 865 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 866 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 867 MIPS_CPU_LLSC;
1da177e4
LT		 868 c->tlbsize = 48;
869 break;
870 case PRID_IMP_R5432:
871 c->cputype = CPU_R5432;
cea7e2df 872 __cpu_name[cpu] = "R5432";
a96102be 873 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 874 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 875 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 876 c->tlbsize = 48;
877 break;
878 case PRID_IMP_R5500:
879 c->cputype = CPU_R5500;
cea7e2df 880 __cpu_name[cpu] = "R5500";
a96102be 881 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 882 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 883 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 884 c->tlbsize = 48;
885 break;
886 case PRID_IMP_NEVADA:
887 c->cputype = CPU_NEVADA;
cea7e2df 888 __cpu_name[cpu] = "Nevada";
a96102be 889 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 890 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 891 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 892 c->tlbsize = 48;
893 break;
894 case PRID_IMP_R6000:
895 c->cputype = CPU_R6000;
cea7e2df 896 __cpu_name[cpu] = "R6000";
a96102be 897 set_isa(c, MIPS_CPU_ISA_II);
9b26616c 898 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1da177e4 899 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 900 MIPS_CPU_LLSC;
1da177e4
LT		 901 c->tlbsize = 32;
902 break;
903 case PRID_IMP_R6000A:
904 c->cputype = CPU_R6000A;
cea7e2df 905 __cpu_name[cpu] = "R6000A";
a96102be 906 set_isa(c, MIPS_CPU_ISA_II);
9b26616c 907 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1da177e4 908 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 909 MIPS_CPU_LLSC;
1da177e4
LT		 910 c->tlbsize = 32;
911 break;
912 case PRID_IMP_RM7000:
913 c->cputype = CPU_RM7000;
cea7e2df 914 __cpu_name[cpu] = "RM7000";
a96102be 915 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 916 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 917 MIPS_CPU_LLSC;
1da177e4 918 /*
70342287 919 * Undocumented RM7000: Bit 29 in the info register of
1da177e4
LT		 920 * the RM7000 v2.0 indicates if the TLB has 48 or 64
921 * entries.
922 *
70342287
RB		 923 * 29 1 => 64 entry JTLB
924 * 0 => 48 entry JTLB
1da177e4
LT		 925 */
926 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1da177e4
LT		 927 break;
928 case PRID_IMP_R8000:
929 c->cputype = CPU_R8000;
cea7e2df 930 __cpu_name[cpu] = "RM8000";
a96102be 931 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 932 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 933 MIPS_CPU_FPU | MIPS_CPU_32FPR |
934 MIPS_CPU_LLSC;
1da177e4
LT		 935 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
936 break;
937 case PRID_IMP_R10000:
938 c->cputype = CPU_R10000;
cea7e2df 939 __cpu_name[cpu] = "R10000";
a96102be 940 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 941 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 942 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 943 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 944 MIPS_CPU_LLSC;
1da177e4
LT		 945 c->tlbsize = 64;
946 break;
947 case PRID_IMP_R12000:
948 c->cputype = CPU_R12000;
cea7e2df 949 __cpu_name[cpu] = "R12000";
a96102be 950 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 951 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 952 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 953 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
8d5ded16 954 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1da177e4
LT		 955 c->tlbsize = 64;
956 break;
44d921b2 957 case PRID_IMP_R14000:
30577391
JK		 958 if (((c->processor_id >> 4) & 0x0f) > 2) {
959 c->cputype = CPU_R16000;
960 __cpu_name[cpu] = "R16000";
961 } else {
962 c->cputype = CPU_R14000;
963 __cpu_name[cpu] = "R14000";
964 }
a96102be 965 set_isa(c, MIPS_CPU_ISA_IV);
44d921b2 966 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 967 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 968 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
8d5ded16 969 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
44d921b2
K		 970 c->tlbsize = 64;
971 break;
26859198 972 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
5aac1e8a
RM		 973 switch (c->processor_id & PRID_REV_MASK) {
974 case PRID_REV_LOONGSON2E:
c579d310
HC		 975 c->cputype = CPU_LOONGSON2;
976 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 977 set_elf_platform(cpu, "loongson2e");
7352c8b1 978 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 979 c->fpu_msk31 |= FPU_CSR_CONDX;
5aac1e8a
RM		 980 break;
981 case PRID_REV_LOONGSON2F:
c579d310
HC		 982 c->cputype = CPU_LOONGSON2;
983 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 984 set_elf_platform(cpu, "loongson2f");
7352c8b1 985 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 986 c->fpu_msk31 |= FPU_CSR_CONDX;
5aac1e8a 987 break;
c579d310
HC		 988 case PRID_REV_LOONGSON3A:
989 c->cputype = CPU_LOONGSON3;
990 __cpu_name[cpu] = "ICT Loongson-3";
991 set_elf_platform(cpu, "loongson3a");
7352c8b1 992 set_isa(c, MIPS_CPU_ISA_M64R1);
c579d310 993 break;
e7841be5
HC		 994 case PRID_REV_LOONGSON3B_R1:
995 case PRID_REV_LOONGSON3B_R2:
996 c->cputype = CPU_LOONGSON3;
997 __cpu_name[cpu] = "ICT Loongson-3";
998 set_elf_platform(cpu, "loongson3b");
7352c8b1 999 set_isa(c, MIPS_CPU_ISA_M64R1);
e7841be5 1000 break;
5aac1e8a
RM		 1001 }
1002
2a21c730
FZ		 1003 c->options = R4K_OPTS |
1004 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1005 MIPS_CPU_32FPR;
1006 c->tlbsize = 64;
cc94ea31 1007 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2a21c730 1008 break;
26859198 1009 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
2fa36399 1010 decode_configs(c);
b4672d37 1011
2fa36399 1012 c->cputype = CPU_LOONGSON1;
1da177e4 1013
2fa36399
KC		 1014 switch (c->processor_id & PRID_REV_MASK) {
1015 case PRID_REV_LOONGSON1B:
1016 __cpu_name[cpu] = "Loongson 1B";
b4672d37 1017 break;
b4672d37 1018 }
4194318c 1019
2fa36399 1020 break;
1da177e4 1021 }
1da177e4
LT		 1022}
1023
cea7e2df 1024static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1025{
4f12b91d 1026 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 1027 switch (c->processor_id & PRID_IMP_MASK) {
b2498af5
LY		 1028 case PRID_IMP_QEMU_GENERIC:
1029 c->writecombine = _CACHE_UNCACHED;
1030 c->cputype = CPU_QEMU_GENERIC;
1031 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1032 break;
1da177e4
LT		 1033 case PRID_IMP_4KC:
1034 c->cputype = CPU_4KC;
4f12b91d 1035 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1036 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 1037 break;
1038 case PRID_IMP_4KEC:
2b07bd02
RB		 1039 case PRID_IMP_4KECR2:
1040 c->cputype = CPU_4KEC;
4f12b91d 1041 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1042 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 1043 break;
1da177e4 1044 case PRID_IMP_4KSC:
8afcb5d8 1045 case PRID_IMP_4KSD:
1da177e4 1046 c->cputype = CPU_4KSC;
4f12b91d 1047 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1048 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 1049 break;
1050 case PRID_IMP_5KC:
1051 c->cputype = CPU_5KC;
4f12b91d 1052 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1053 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4 1054 break;
78d4803f
LY		 1055 case PRID_IMP_5KE:
1056 c->cputype = CPU_5KE;
4f12b91d 1057 c->writecombine = _CACHE_UNCACHED;
78d4803f
LY		 1058 __cpu_name[cpu] = "MIPS 5KE";
1059 break;
1da177e4
LT		 1060 case PRID_IMP_20KC:
1061 c->cputype = CPU_20KC;
4f12b91d 1062 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1063 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 1064 break;
1065 case PRID_IMP_24K:
1066 c->cputype = CPU_24K;
4f12b91d 1067 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1068 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4 1069 break;
42f3caef
JC		 1070 case PRID_IMP_24KE:
1071 c->cputype = CPU_24K;
4f12b91d 1072 c->writecombine = _CACHE_UNCACHED;
42f3caef
JC		 1073 __cpu_name[cpu] = "MIPS 24KEc";
1074 break;
1da177e4
LT		 1075 case PRID_IMP_25KF:
1076 c->cputype = CPU_25KF;
4f12b91d 1077 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1078 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 1079 break;
bbc7f22f
RB		 1080 case PRID_IMP_34K:
1081 c->cputype = CPU_34K;
4f12b91d 1082 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1083 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 1084 break;
c620953c
CD		 1085 case PRID_IMP_74K:
1086 c->cputype = CPU_74K;
4f12b91d 1087 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1088 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 1089 break;
113c62d9
SH		 1090 case PRID_IMP_M14KC:
1091 c->cputype = CPU_M14KC;
4f12b91d 1092 c->writecombine = _CACHE_UNCACHED;
113c62d9
SH		 1093 __cpu_name[cpu] = "MIPS M14Kc";
1094 break;
f8fa4811
SH		 1095 case PRID_IMP_M14KEC:
1096 c->cputype = CPU_M14KEC;
4f12b91d 1097 c->writecombine = _CACHE_UNCACHED;
f8fa4811
SH		 1098 __cpu_name[cpu] = "MIPS M14KEc";
1099 break;
39b8d525
RB		 1100 case PRID_IMP_1004K:
1101 c->cputype = CPU_1004K;
4f12b91d 1102 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1103 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 1104 break;
006a851b 1105 case PRID_IMP_1074K:
442e14a2 1106 c->cputype = CPU_1074K;
4f12b91d 1107 c->writecombine = _CACHE_UNCACHED;
006a851b
SH		 1108 __cpu_name[cpu] = "MIPS 1074Kc";
1109 break;
b5f065e7
LY		 1110 case PRID_IMP_INTERAPTIV_UP:
1111 c->cputype = CPU_INTERAPTIV;
1112 __cpu_name[cpu] = "MIPS interAptiv";
1113 break;
1114 case PRID_IMP_INTERAPTIV_MP:
1115 c->cputype = CPU_INTERAPTIV;
1116 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1117 break;
b0d4d300
LY		 1118 case PRID_IMP_PROAPTIV_UP:
1119 c->cputype = CPU_PROAPTIV;
1120 __cpu_name[cpu] = "MIPS proAptiv";
1121 break;
1122 case PRID_IMP_PROAPTIV_MP:
1123 c->cputype = CPU_PROAPTIV;
1124 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1125 break;
829dcc0a
JH		 1126 case PRID_IMP_P5600:
1127 c->cputype = CPU_P5600;
1128 __cpu_name[cpu] = "MIPS P5600";
1129 break;
e57f9a2d
MC		 1130 case PRID_IMP_I6400:
1131 c->cputype = CPU_I6400;
1132 __cpu_name[cpu] = "MIPS I6400";
1133 break;
9943ed92
LY		 1134 case PRID_IMP_M5150:
1135 c->cputype = CPU_M5150;
1136 __cpu_name[cpu] = "MIPS M5150";
1137 break;
1da177e4 1138 }
0b6d497f 1139
75b5b5e0
LY		 1140 decode_configs(c);
1141
0b6d497f 1142 spram_config();
1da177e4
LT		 1143}
1144
cea7e2df 1145static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1146{
4194318c 1147 decode_configs(c);
8ff374b9 1148 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1149 case PRID_IMP_AU1_REV1:
1150 case PRID_IMP_AU1_REV2:
270717a8 1151 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 1152 switch ((c->processor_id >> 24) & 0xff) {
1153 case 0:
cea7e2df 1154 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 1155 break;
1156 case 1:
cea7e2df 1157 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 1158 break;
1159 case 2:
cea7e2df 1160 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 1161 break;
1162 case 3:
cea7e2df 1163 __cpu_name[cpu] = "Au1550";
1da177e4 1164 break;
e3ad1c23 1165 case 4:
cea7e2df 1166 __cpu_name[cpu] = "Au1200";
8ff374b9 1167 if ((c->processor_id & PRID_REV_MASK) == 2)
cea7e2df 1168 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 1169 break;
1170 case 5:
cea7e2df 1171 __cpu_name[cpu] = "Au1210";
e3ad1c23 1172 break;
1da177e4 1173 default:
270717a8 1174 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 1175 break;
1176 }
1da177e4
LT		 1177 break;
1178 }
1179}
1180
cea7e2df 1181static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1182{
4194318c 1183 decode_configs(c);
02cf2119 1184
4f12b91d 1185 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 1186 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1187 case PRID_IMP_SB1:
1188 c->cputype = CPU_SB1;
cea7e2df 1189 __cpu_name[cpu] = "SiByte SB1";
1da177e4 1190 /* FPU in pass1 is known to have issues. */
8ff374b9 1191 if ((c->processor_id & PRID_REV_MASK) < 0x02)
010b853b 1192 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 1193 break;
93ce2f52
AI		 1194 case PRID_IMP_SB1A:
1195 c->cputype = CPU_SB1A;
cea7e2df 1196 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 1197 break;
1da177e4
LT		 1198 }
1199}
1200
cea7e2df 1201static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1202{
4194318c 1203 decode_configs(c);
8ff374b9 1204 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1205 case PRID_IMP_SR71000:
1206 c->cputype = CPU_SR71000;
cea7e2df 1207 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 1208 c->scache.ways = 8;
1209 c->tlbsize = 64;
1210 break;
1211 }
1212}
1213
cea7e2df 1214static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 1215{
1216 decode_configs(c);
8ff374b9 1217 switch (c->processor_id & PRID_IMP_MASK) {
bdf21b18
PP		 1218 case PRID_IMP_PR4450:
1219 c->cputype = CPU_PR4450;
cea7e2df 1220 __cpu_name[cpu] = "Philips PR4450";
a96102be 1221 set_isa(c, MIPS_CPU_ISA_M32R1);
bdf21b18 1222 break;
bdf21b18
PP		 1223 }
1224}
1225
cea7e2df 1226static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 1227{
1228 decode_configs(c);
8ff374b9 1229 switch (c->processor_id & PRID_IMP_MASK) {
190fca3e
KC		 1230 case PRID_IMP_BMIPS32_REV4:
1231 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 1232 c->cputype = CPU_BMIPS32;
1233 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 1234 set_elf_platform(cpu, "bmips32");
602977b0
KC		 1235 break;
1236 case PRID_IMP_BMIPS3300:
1237 case PRID_IMP_BMIPS3300_ALT:
1238 case PRID_IMP_BMIPS3300_BUG:
1239 c->cputype = CPU_BMIPS3300;
1240 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 1241 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 1242 break;
1243 case PRID_IMP_BMIPS43XX: {
8ff374b9 1244 int rev = c->processor_id & PRID_REV_MASK;
602977b0
KC		 1245
1246 if (rev >= PRID_REV_BMIPS4380_LO &&
1247 rev <= PRID_REV_BMIPS4380_HI) {
1248 c->cputype = CPU_BMIPS4380;
1249 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 1250 set_elf_platform(cpu, "bmips4380");
602977b0
KC		 1251 } else {
1252 c->cputype = CPU_BMIPS4350;
1253 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 1254 set_elf_platform(cpu, "bmips4350");
602977b0 1255 }
0de663ef 1256 break;
602977b0
KC		 1257 }
1258 case PRID_IMP_BMIPS5000:
68e6a783 1259 case PRID_IMP_BMIPS5200:
602977b0
KC		 1260 c->cputype = CPU_BMIPS5000;
1261 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 1262 set_elf_platform(cpu, "bmips5000");
602977b0 1263 c->options |= MIPS_CPU_ULRI;
0de663ef 1264 break;
1c0c13eb
AJ		 1265 }
1266}
1267
0dd4781b
DD		 1268static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1269{
1270 decode_configs(c);
8ff374b9 1271 switch (c->processor_id & PRID_IMP_MASK) {
0dd4781b
DD		 1272 case PRID_IMP_CAVIUM_CN38XX:
1273 case PRID_IMP_CAVIUM_CN31XX:
1274 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 1275 c->cputype = CPU_CAVIUM_OCTEON;
1276 __cpu_name[cpu] = "Cavium Octeon";
1277 goto platform;
0dd4781b
DD		 1278 case PRID_IMP_CAVIUM_CN58XX:
1279 case PRID_IMP_CAVIUM_CN56XX:
1280 case PRID_IMP_CAVIUM_CN50XX:
1281 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 1282 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1283 __cpu_name[cpu] = "Cavium Octeon+";
1284platform:
c094c99e 1285 set_elf_platform(cpu, "octeon");
0dd4781b 1286 break;
a1431b61 1287 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 1288 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 1289 case PRID_IMP_CAVIUM_CN66XX:
1290 case PRID_IMP_CAVIUM_CN68XX:
af04bb85 1291 case PRID_IMP_CAVIUM_CNF71XX:
0e56b385
DD		 1292 c->cputype = CPU_CAVIUM_OCTEON2;
1293 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 1294 set_elf_platform(cpu, "octeon2");
0e56b385 1295 break;
af04bb85
DD		 1296 case PRID_IMP_CAVIUM_CN70XX:
1297 case PRID_IMP_CAVIUM_CN78XX:
1298 c->cputype = CPU_CAVIUM_OCTEON3;
1299 __cpu_name[cpu] = "Cavium Octeon III";
1300 set_elf_platform(cpu, "octeon3");
1301 break;
0dd4781b
DD		 1302 default:
1303 printk(KERN_INFO "Unknown Octeon chip!\n");
1304 c->cputype = CPU_UNKNOWN;
1305 break;
1306 }
1307}
1308
83ccf69d
LPC		 1309static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1310{
1311 decode_configs(c);
1312 /* JZRISC does not implement the CP0 counter. */
1313 c->options &= ~MIPS_CPU_COUNTER;
06947aaa 1314 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
8ff374b9 1315 switch (c->processor_id & PRID_IMP_MASK) {
83ccf69d
LPC		 1316 case PRID_IMP_JZRISC:
1317 c->cputype = CPU_JZRISC;
4f12b91d 1318 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
83ccf69d
LPC		 1319 __cpu_name[cpu] = "Ingenic JZRISC";
1320 break;
1321 default:
1322 panic("Unknown Ingenic Processor ID!");
1323 break;
1324 }
1325}
1326
a7117c6b
J		 1327static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1328{
1329 decode_configs(c);
1330
8ff374b9 1331 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
809f36c6
ML		 1332 c->cputype = CPU_ALCHEMY;
1333 __cpu_name[cpu] = "Au1300";
1334 /* following stuff is not for Alchemy */
1335 return;
1336 }
1337
70342287
RB		 1338 c->options = (MIPS_CPU_TLB |
1339 MIPS_CPU_4KEX |
a7117c6b 1340 MIPS_CPU_COUNTER |
70342287
RB		 1341 MIPS_CPU_DIVEC |
1342 MIPS_CPU_WATCH |
1343 MIPS_CPU_EJTAG |
a7117c6b
J		 1344 MIPS_CPU_LLSC);
1345
8ff374b9 1346 switch (c->processor_id & PRID_IMP_MASK) {
4ca86a2f 1347 case PRID_IMP_NETLOGIC_XLP2XX:
8907c55e 1348 case PRID_IMP_NETLOGIC_XLP9XX:
1c983986 1349 case PRID_IMP_NETLOGIC_XLP5XX:
4ca86a2f
J		 1350 c->cputype = CPU_XLP;
1351 __cpu_name[cpu] = "Broadcom XLPII";
1352 break;
1353
2aa54b20
J		 1354 case PRID_IMP_NETLOGIC_XLP8XX:
1355 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 1356 c->cputype = CPU_XLP;
1357 __cpu_name[cpu] = "Netlogic XLP";
1358 break;
1359
a7117c6b
J		 1360 case PRID_IMP_NETLOGIC_XLR732:
1361 case PRID_IMP_NETLOGIC_XLR716:
1362 case PRID_IMP_NETLOGIC_XLR532:
1363 case PRID_IMP_NETLOGIC_XLR308:
1364 case PRID_IMP_NETLOGIC_XLR532C:
1365 case PRID_IMP_NETLOGIC_XLR516C:
1366 case PRID_IMP_NETLOGIC_XLR508C:
1367 case PRID_IMP_NETLOGIC_XLR308C:
1368 c->cputype = CPU_XLR;
1369 __cpu_name[cpu] = "Netlogic XLR";
1370 break;
1371
1372 case PRID_IMP_NETLOGIC_XLS608:
1373 case PRID_IMP_NETLOGIC_XLS408:
1374 case PRID_IMP_NETLOGIC_XLS404:
1375 case PRID_IMP_NETLOGIC_XLS208:
1376 case PRID_IMP_NETLOGIC_XLS204:
1377 case PRID_IMP_NETLOGIC_XLS108:
1378 case PRID_IMP_NETLOGIC_XLS104:
1379 case PRID_IMP_NETLOGIC_XLS616B:
1380 case PRID_IMP_NETLOGIC_XLS608B:
1381 case PRID_IMP_NETLOGIC_XLS416B:
1382 case PRID_IMP_NETLOGIC_XLS412B:
1383 case PRID_IMP_NETLOGIC_XLS408B:
1384 case PRID_IMP_NETLOGIC_XLS404B:
1385 c->cputype = CPU_XLR;
1386 __cpu_name[cpu] = "Netlogic XLS";
1387 break;
1388
1389 default:
a3d4fb2d 1390 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 1391 c->processor_id);
1392 c->cputype = CPU_XLR;
1393 break;
1394 }
1395
a3d4fb2d 1396 if (c->cputype == CPU_XLP) {
a96102be 1397 set_isa(c, MIPS_CPU_ISA_M64R2);
a3d4fb2d
J		 1398 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1399 /* This will be updated again after all threads are woken up */
1400 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1401 } else {
a96102be 1402 set_isa(c, MIPS_CPU_ISA_M64R1);
a3d4fb2d
J		 1403 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1404 }
7777b939 1405 c->kscratch_mask = 0xf;
a7117c6b
J		 1406}
1407
949e51be
DD		 1408#ifdef CONFIG_64BIT
1409/* For use by uaccess.h */
1410u64 __ua_limit;
1411EXPORT_SYMBOL(__ua_limit);
1412#endif
1413
9966db25 1414const char *__cpu_name[NR_CPUS];
874fd3b5 1415const char *__elf_platform;
9966db25 1416
078a55fc 1417void cpu_probe(void)
1da177e4
LT		 1418{
1419 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 1420 unsigned int cpu = smp_processor_id();
1da177e4 1421
70342287 1422 c->processor_id = PRID_IMP_UNKNOWN;
1da177e4
LT		 1423 c->fpu_id = FPIR_IMP_NONE;
1424 c->cputype = CPU_UNKNOWN;
4f12b91d 1425 c->writecombine = _CACHE_UNCACHED;
1da177e4 1426
9b26616c
MR		 1427 c->fpu_csr31 = FPU_CSR_RN;
1428 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1429
1da177e4 1430 c->processor_id = read_c0_prid();
8ff374b9 1431 switch (c->processor_id & PRID_COMP_MASK) {
1da177e4 1432 case PRID_COMP_LEGACY:
cea7e2df 1433 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1434 break;
1435 case PRID_COMP_MIPS:
cea7e2df 1436 cpu_probe_mips(c, cpu);
1da177e4
LT		 1437 break;
1438 case PRID_COMP_ALCHEMY:
cea7e2df 1439 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1440 break;
1441 case PRID_COMP_SIBYTE:
cea7e2df 1442 cpu_probe_sibyte(c, cpu);
1da177e4 1443 break;
1c0c13eb 1444 case PRID_COMP_BROADCOM:
cea7e2df 1445 cpu_probe_broadcom(c, cpu);
1c0c13eb 1446 break;
1da177e4 1447 case PRID_COMP_SANDCRAFT:
cea7e2df 1448 cpu_probe_sandcraft(c, cpu);
1da177e4 1449 break;
a92b0588 1450 case PRID_COMP_NXP:
cea7e2df 1451 cpu_probe_nxp(c, cpu);
a3dddd56 1452 break;
0dd4781b
DD		 1453 case PRID_COMP_CAVIUM:
1454 cpu_probe_cavium(c, cpu);
1455 break;
252617a4
PB		 1456 case PRID_COMP_INGENIC_D0:
1457 case PRID_COMP_INGENIC_D1:
1458 case PRID_COMP_INGENIC_E1:
83ccf69d
LPC		 1459 cpu_probe_ingenic(c, cpu);
1460 break;
a7117c6b
J		 1461 case PRID_COMP_NETLOGIC:
1462 cpu_probe_netlogic(c, cpu);
1463 break;
1da177e4 1464 }
dec8b1ca 1465
cea7e2df
RB		 1466 BUG_ON(!__cpu_name[cpu]);
1467 BUG_ON(c->cputype == CPU_UNKNOWN);
1468
dec8b1ca
FBH		 1469 /*
1470 * Platform code can force the cpu type to optimize code
1471 * generation. In that case be sure the cpu type is correctly
1472 * manually setup otherwise it could trigger some nasty bugs.
1473 */
1474 BUG_ON(current_cpu_type() != c->cputype);
1475
0103d23f
KC		 1476 if (mips_fpu_disabled)
1477 c->options &= ~MIPS_CPU_FPU;
1478
1479 if (mips_dsp_disabled)
ee80f7c7 1480 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f 1481
3d528b32
MC		 1482 if (mips_htw_disabled) {
1483 c->options &= ~MIPS_CPU_HTW;
1484 write_c0_pwctl(read_c0_pwctl() &
1485 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1486 }
1487
7aecd5ca
MR		 1488 if (c->options & MIPS_CPU_FPU)
1489 cpu_set_fpu_opts(c);
1490 else
1491 cpu_set_nofpu_opts(c);
9966db25 1492
8d5ded16
JK		 1493 if (cpu_has_bp_ghist)
1494 write_c0_r10k_diag(read_c0_r10k_diag() |
1495 R10K_DIAG_E_GHIST);
1496
8b8aa636 1497 if (cpu_has_mips_r2_r6) {
f6771dbb 1498 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
da4b62cd
AC		 1499 /* R2 has Performance Counter Interrupt indicator */
1500 c->options |= MIPS_CPU_PCI;
1501 }
f6771dbb
RB		 1502 else
1503 c->srsets = 1;
91dfc423 1504
a8ad1367 1505 if (cpu_has_msa) {
a5e9a69e 1506 c->msa_id = cpu_get_msa_id();
a8ad1367
PB		 1507 WARN(c->msa_id & MSA_IR_WRPF,
1508 "Vector register partitioning unimplemented!");
1509 }
a5e9a69e 1510
91dfc423 1511 cpu_probe_vmbits(c);
949e51be
DD		 1512
1513#ifdef CONFIG_64BIT
1514 if (cpu == 0)
1515 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1516#endif
1da177e4
LT		 1517}
1518
078a55fc 1519void cpu_report(void)
1da177e4
LT		 1520{
1521 struct cpuinfo_mips *c = &current_cpu_data;
1522
d9f897c9
LY		 1523 pr_info("CPU%d revision is: %08x (%s)\n",
1524 smp_processor_id(), c->processor_id, cpu_name_string());
1da177e4 1525 if (c->options & MIPS_CPU_FPU)
9966db25 1526 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
a5e9a69e
PB		 1527 if (cpu_has_msa)
1528 pr_info("MSA revision is: %08x\n", c->msa_id);
1da177e4 1529}
Linux 6.x block layer and io_uring tree(s)