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MIPS: kernel: cevt-r4k: Add MIPS R6 to the c0_compare_interrupt handler
[linux-2.6-block.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
70342287 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4 22#include <asm/cpu.h>
69f24d17 23#include <asm/cpu-type.h>
1da177e4
LT		 24#include <asm/fpu.h>
25#include <asm/mipsregs.h>
30ee615b 26#include <asm/mipsmtregs.h>
a5e9a69e 27#include <asm/msa.h>
654f57bf 28#include <asm/watch.h>
06372a63 29#include <asm/elf.h>
4f12b91d 30#include <asm/pgtable-bits.h>
a074f0e8 31#include <asm/spram.h>
949e51be
DD		 32#include <asm/uaccess.h>
33
078a55fc 34static int mips_fpu_disabled;
0103d23f
KC		 35
36static int __init fpu_disable(char *s)
37{
38 cpu_data[0].options &= ~MIPS_CPU_FPU;
39 mips_fpu_disabled = 1;
40
41 return 1;
42}
43
44__setup("nofpu", fpu_disable);
45
078a55fc 46int mips_dsp_disabled;
0103d23f
KC		 47
48static int __init dsp_disable(char *s)
49{
ee80f7c7 50 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f
KC		 51 mips_dsp_disabled = 1;
52
53 return 1;
54}
55
56__setup("nodsp", dsp_disable);
57
3d528b32
MC		 58static int mips_htw_disabled;
59
60static int __init htw_disable(char *s)
61{
62 mips_htw_disabled = 1;
63 cpu_data[0].options &= ~MIPS_CPU_HTW;
64 write_c0_pwctl(read_c0_pwctl() &
65 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
66
67 return 1;
68}
69
70__setup("nohtw", htw_disable);
71
97f4ad29
MC		 72static int mips_ftlb_disabled;
73static int mips_has_ftlb_configured;
74
75static void set_ftlb_enable(struct cpuinfo_mips *c, int enable);
76
77static int __init ftlb_disable(char *s)
78{
79 unsigned int config4, mmuextdef;
80
81 /*
82 * If the core hasn't done any FTLB configuration, there is nothing
83 * for us to do here.
84 */
85 if (!mips_has_ftlb_configured)
86 return 1;
87
88 /* Disable it in the boot cpu */
89 set_ftlb_enable(&cpu_data[0], 0);
90
91 back_to_back_c0_hazard();
92
93 config4 = read_c0_config4();
94
95 /* Check that FTLB has been disabled */
96 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
97 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
98 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
99 /* This should never happen */
100 pr_warn("FTLB could not be disabled!\n");
101 return 1;
102 }
103
104 mips_ftlb_disabled = 1;
105 mips_has_ftlb_configured = 0;
106
107 /*
108 * noftlb is mainly used for debug purposes so print
109 * an informative message instead of using pr_debug()
110 */
111 pr_info("FTLB has been disabled\n");
112
113 /*
114 * Some of these bits are duplicated in the decode_config4.
115 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
116 * once FTLB has been disabled so undo what decode_config4 did.
117 */
118 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
119 cpu_data[0].tlbsizeftlbsets;
120 cpu_data[0].tlbsizeftlbsets = 0;
121 cpu_data[0].tlbsizeftlbways = 0;
122
123 return 1;
124}
125
126__setup("noftlb", ftlb_disable);
127
128
9267a30d
MSJ		 129static inline void check_errata(void)
130{
131 struct cpuinfo_mips *c = &current_cpu_data;
132
69f24d17 133 switch (current_cpu_type()) {
9267a30d
MSJ		 134 case CPU_34K:
135 /*
136 * Erratum "RPS May Cause Incorrect Instruction Execution"
b633648c 137 * This code only handles VPE0, any SMP/RTOS code
9267a30d
MSJ		 138 * making use of VPE1 will be responsable for that VPE.
139 */
140 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
141 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
142 break;
143 default:
144 break;
145 }
146}
147
1da177e4
LT		 148void __init check_bugs32(void)
149{
9267a30d 150 check_errata();
1da177e4
LT		 151}
152
153/*
154 * Probe whether cpu has config register by trying to play with
155 * alternate cache bit and see whether it matters.
156 * It's used by cpu_probe to distinguish between R3000A and R3081.
157 */
158static inline int cpu_has_confreg(void)
159{
160#ifdef CONFIG_CPU_R3000
161 extern unsigned long r3k_cache_size(unsigned long);
162 unsigned long size1, size2;
163 unsigned long cfg = read_c0_conf();
164
165 size1 = r3k_cache_size(ST0_ISC);
166 write_c0_conf(cfg ^ R30XX_CONF_AC);
167 size2 = r3k_cache_size(ST0_ISC);
168 write_c0_conf(cfg);
169 return size1 != size2;
170#else
171 return 0;
172#endif
173}
174
c094c99e
RM		 175static inline void set_elf_platform(int cpu, const char *plat)
176{
177 if (cpu == 0)
178 __elf_platform = plat;
179}
180
1da177e4
LT		 181/*
182 * Get the FPU Implementation/Revision.
183 */
184static inline unsigned long cpu_get_fpu_id(void)
185{
186 unsigned long tmp, fpu_id;
187
188 tmp = read_c0_status();
597ce172 189 __enable_fpu(FPU_AS_IS);
1da177e4
LT		 190 fpu_id = read_32bit_cp1_register(CP1_REVISION);
191 write_c0_status(tmp);
192 return fpu_id;
193}
194
195/*
196 * Check the CPU has an FPU the official way.
197 */
198static inline int __cpu_has_fpu(void)
199{
635c9907 200 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
1da177e4
LT		 201}
202
a5e9a69e
PB		 203static inline unsigned long cpu_get_msa_id(void)
204{
3587ea88 205 unsigned long status, msa_id;
a5e9a69e
PB		 206
207 status = read_c0_status();
208 __enable_fpu(FPU_64BIT);
a5e9a69e
PB		 209 enable_msa();
210 msa_id = read_msa_ir();
3587ea88 211 disable_msa();
a5e9a69e
PB		 212 write_c0_status(status);
213 return msa_id;
214}
215
91dfc423
GR		 216static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
217{
218#ifdef __NEED_VMBITS_PROBE
5b7efa89 219 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 220 back_to_back_c0_hazard();
5b7efa89 221 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 222#endif
223}
224
078a55fc 225static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
a96102be
SH		 226{
227 switch (isa) {
228 case MIPS_CPU_ISA_M64R2:
229 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
230 case MIPS_CPU_ISA_M64R1:
231 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
232 case MIPS_CPU_ISA_V:
233 c->isa_level |= MIPS_CPU_ISA_V;
234 case MIPS_CPU_ISA_IV:
235 c->isa_level |= MIPS_CPU_ISA_IV;
236 case MIPS_CPU_ISA_III:
1990e542 237 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
a96102be
SH		 238 break;
239
240 case MIPS_CPU_ISA_M32R2:
241 c->isa_level |= MIPS_CPU_ISA_M32R2;
242 case MIPS_CPU_ISA_M32R1:
243 c->isa_level |= MIPS_CPU_ISA_M32R1;
244 case MIPS_CPU_ISA_II:
245 c->isa_level |= MIPS_CPU_ISA_II;
a96102be
SH		 246 break;
247 }
248}
249
078a55fc 250static char unknown_isa[] = KERN_ERR \
2fa36399
KC		 251 "Unsupported ISA type, c0.config0: %d.";
252
cf0a8aa0
MC		 253static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
254{
255
256 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
257
258 /*
259 * 0 = All TLBWR instructions go to FTLB
260 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
261 * FTLB and 1 goes to the VTLB.
262 * 2 = 7:1: As above with 7:1 ratio.
263 * 3 = 3:1: As above with 3:1 ratio.
264 *
265 * Use the linear midpoint as the probability threshold.
266 */
267 if (probability >= 12)
268 return 1;
269 else if (probability >= 6)
270 return 2;
271 else
272 /*
273 * So FTLB is less than 4 times bigger than VTLB.
274 * A 3:1 ratio can still be useful though.
275 */
276 return 3;
277}
278
75b5b5e0
LY		 279static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
280{
281 unsigned int config6;
d83b0e82
JH		 282
283 /* It's implementation dependent how the FTLB can be enabled */
284 switch (c->cputype) {
285 case CPU_PROAPTIV:
286 case CPU_P5600:
287 /* proAptiv & related cores use Config6 to enable the FTLB */
75b5b5e0 288 config6 = read_c0_config6();
cf0a8aa0
MC		 289 /* Clear the old probability value */
290 config6 &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
75b5b5e0
LY		 291 if (enable)
292 /* Enable FTLB */
cf0a8aa0
MC		 293 write_c0_config6(config6 |
294 (calculate_ftlb_probability(c)
295 << MIPS_CONF6_FTLBP_SHIFT)
296 | MIPS_CONF6_FTLBEN);
75b5b5e0
LY		 297 else
298 /* Disable FTLB */
299 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
300 back_to_back_c0_hazard();
d83b0e82 301 break;
75b5b5e0
LY		 302 }
303}
304
2fa36399
KC		 305static inline unsigned int decode_config0(struct cpuinfo_mips *c)
306{
307 unsigned int config0;
308 int isa;
309
310 config0 = read_c0_config();
311
75b5b5e0
LY		 312 /*
313 * Look for Standard TLB or Dual VTLB and FTLB
314 */
315 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
316 (((config0 & MIPS_CONF_MT) >> 7) == 4))
2fa36399 317 c->options |= MIPS_CPU_TLB;
75b5b5e0 318
2fa36399
KC		 319 isa = (config0 & MIPS_CONF_AT) >> 13;
320 switch (isa) {
321 case 0:
322 switch ((config0 & MIPS_CONF_AR) >> 10) {
323 case 0:
a96102be 324 set_isa(c, MIPS_CPU_ISA_M32R1);
2fa36399
KC		 325 break;
326 case 1:
a96102be 327 set_isa(c, MIPS_CPU_ISA_M32R2);
2fa36399
KC		 328 break;
329 default:
330 goto unknown;
331 }
332 break;
333 case 2:
334 switch ((config0 & MIPS_CONF_AR) >> 10) {
335 case 0:
a96102be 336 set_isa(c, MIPS_CPU_ISA_M64R1);
2fa36399
KC		 337 break;
338 case 1:
a96102be 339 set_isa(c, MIPS_CPU_ISA_M64R2);
2fa36399
KC		 340 break;
341 default:
342 goto unknown;
343 }
344 break;
345 default:
346 goto unknown;
347 }
348
349 return config0 & MIPS_CONF_M;
350
351unknown:
352 panic(unknown_isa, config0);
353}
354
355static inline unsigned int decode_config1(struct cpuinfo_mips *c)
356{
357 unsigned int config1;
358
359 config1 = read_c0_config1();
360
361 if (config1 & MIPS_CONF1_MD)
362 c->ases |= MIPS_ASE_MDMX;
363 if (config1 & MIPS_CONF1_WR)
364 c->options |= MIPS_CPU_WATCH;
365 if (config1 & MIPS_CONF1_CA)
366 c->ases |= MIPS_ASE_MIPS16;
367 if (config1 & MIPS_CONF1_EP)
368 c->options |= MIPS_CPU_EJTAG;
369 if (config1 & MIPS_CONF1_FP) {
370 c->options |= MIPS_CPU_FPU;
371 c->options |= MIPS_CPU_32FPR;
372 }
75b5b5e0 373 if (cpu_has_tlb) {
2fa36399 374 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
75b5b5e0
LY		 375 c->tlbsizevtlb = c->tlbsize;
376 c->tlbsizeftlbsets = 0;
377 }
2fa36399
KC		 378
379 return config1 & MIPS_CONF_M;
380}
381
382static inline unsigned int decode_config2(struct cpuinfo_mips *c)
383{
384 unsigned int config2;
385
386 config2 = read_c0_config2();
387
388 if (config2 & MIPS_CONF2_SL)
389 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
390
391 return config2 & MIPS_CONF_M;
392}
393
394static inline unsigned int decode_config3(struct cpuinfo_mips *c)
395{
396 unsigned int config3;
397
398 config3 = read_c0_config3();
399
b2ab4f08 400 if (config3 & MIPS_CONF3_SM) {
2fa36399 401 c->ases |= MIPS_ASE_SMARTMIPS;
b2ab4f08
SH		 402 c->options |= MIPS_CPU_RIXI;
403 }
404 if (config3 & MIPS_CONF3_RXI)
405 c->options |= MIPS_CPU_RIXI;
2fa36399
KC		 406 if (config3 & MIPS_CONF3_DSP)
407 c->ases |= MIPS_ASE_DSP;
ee80f7c7
SH		 408 if (config3 & MIPS_CONF3_DSP2P)
409 c->ases |= MIPS_ASE_DSP2P;
2fa36399
KC		 410 if (config3 & MIPS_CONF3_VINT)
411 c->options |= MIPS_CPU_VINT;
412 if (config3 & MIPS_CONF3_VEIC)
413 c->options |= MIPS_CPU_VEIC;
414 if (config3 & MIPS_CONF3_MT)
415 c->ases |= MIPS_ASE_MIPSMT;
416 if (config3 & MIPS_CONF3_ULRI)
417 c->options |= MIPS_CPU_ULRI;
f8fa4811
SH		 418 if (config3 & MIPS_CONF3_ISA)
419 c->options |= MIPS_CPU_MICROMIPS;
1e7decdb
DD		 420 if (config3 & MIPS_CONF3_VZ)
421 c->ases |= MIPS_ASE_VZ;
4a0156fb
SH		 422 if (config3 & MIPS_CONF3_SC)
423 c->options |= MIPS_CPU_SEGMENTS;
a5e9a69e
PB		 424 if (config3 & MIPS_CONF3_MSA)
425 c->ases |= MIPS_ASE_MSA;
3d528b32 426 /* Only tested on 32-bit cores */
ed4cbc81
MC		 427 if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) {
428 c->htw_seq = 0;
3d528b32 429 c->options |= MIPS_CPU_HTW;
ed4cbc81 430 }
2fa36399
KC		 431
432 return config3 & MIPS_CONF_M;
433}
434
435static inline unsigned int decode_config4(struct cpuinfo_mips *c)
436{
437 unsigned int config4;
75b5b5e0
LY		 438 unsigned int newcf4;
439 unsigned int mmuextdef;
440 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
2fa36399
KC		 441
442 config4 = read_c0_config4();
443
1745c1ef
LY		 444 if (cpu_has_tlb) {
445 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
446 c->options |= MIPS_CPU_TLBINV;
75b5b5e0
LY		 447 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
448 switch (mmuextdef) {
449 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
450 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
451 c->tlbsizevtlb = c->tlbsize;
452 break;
453 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
454 c->tlbsizevtlb +=
455 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
456 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
457 c->tlbsize = c->tlbsizevtlb;
458 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
459 /* fall through */
460 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
97f4ad29
MC		 461 if (mips_ftlb_disabled)
462 break;
75b5b5e0
LY		 463 newcf4 = (config4 & ~ftlb_page) |
464 (page_size_ftlb(mmuextdef) <<
465 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
466 write_c0_config4(newcf4);
467 back_to_back_c0_hazard();
468 config4 = read_c0_config4();
469 if (config4 != newcf4) {
470 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
471 PAGE_SIZE, config4);
472 /* Switch FTLB off */
473 set_ftlb_enable(c, 0);
474 break;
475 }
476 c->tlbsizeftlbsets = 1 <<
477 ((config4 & MIPS_CONF4_FTLBSETS) >>
478 MIPS_CONF4_FTLBSETS_SHIFT);
479 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
480 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
481 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
97f4ad29 482 mips_has_ftlb_configured = 1;
75b5b5e0
LY		 483 break;
484 }
1745c1ef
LY		 485 }
486
2fa36399
KC		 487 c->kscratch_mask = (config4 >> 16) & 0xff;
488
489 return config4 & MIPS_CONF_M;
490}
491
8b8a7634
RB		 492static inline unsigned int decode_config5(struct cpuinfo_mips *c)
493{
494 unsigned int config5;
495
496 config5 = read_c0_config5();
d175ed2b 497 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
8b8a7634
RB		 498 write_c0_config5(config5);
499
49016748
MC		 500 if (config5 & MIPS_CONF5_EVA)
501 c->options |= MIPS_CPU_EVA;
1f6c52ff
PB		 502 if (config5 & MIPS_CONF5_MRP)
503 c->options |= MIPS_CPU_MAAR;
49016748 504
8b8a7634
RB		 505 return config5 & MIPS_CONF_M;
506}
507
078a55fc 508static void decode_configs(struct cpuinfo_mips *c)
2fa36399
KC		 509{
510 int ok;
511
512 /* MIPS32 or MIPS64 compliant CPU. */
513 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
514 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
515
516 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
517
97f4ad29
MC		 518 /* Enable FTLB if present and not disabled */
519 set_ftlb_enable(c, !mips_ftlb_disabled);
75b5b5e0 520
2fa36399 521 ok = decode_config0(c); /* Read Config registers. */
70342287 522 BUG_ON(!ok); /* Arch spec violation! */
2fa36399
KC		 523 if (ok)
524 ok = decode_config1(c);
525 if (ok)
526 ok = decode_config2(c);
527 if (ok)
528 ok = decode_config3(c);
529 if (ok)
530 ok = decode_config4(c);
8b8a7634
RB		 531 if (ok)
532 ok = decode_config5(c);
2fa36399
KC		 533
534 mips_probe_watch_registers(c);
535
6575b1d4
LY		 536 if (cpu_has_rixi) {
537 /* Enable the RIXI exceptions */
538 write_c0_pagegrain(read_c0_pagegrain() | PG_IEC);
539 back_to_back_c0_hazard();
540 /* Verify the IEC bit is set */
541 if (read_c0_pagegrain() & PG_IEC)
542 c->options |= MIPS_CPU_RIXIEX;
543 }
544
0ee958e1 545#ifndef CONFIG_MIPS_CPS
30ee615b 546 if (cpu_has_mips_r2) {
45b585c8 547 c->core = get_ebase_cpunum();
30ee615b
PB		 548 if (cpu_has_mipsmt)
549 c->core >>= fls(core_nvpes()) - 1;
550 }
0ee958e1 551#endif
2fa36399
KC		 552}
553
02cf2119 554#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 555 | MIPS_CPU_COUNTER)
556
cea7e2df 557static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 558{
8ff374b9 559 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 560 case PRID_IMP_R2000:
561 c->cputype = CPU_R2000;
cea7e2df 562 __cpu_name[cpu] = "R2000";
02cf2119 563 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 564 MIPS_CPU_NOFPUEX;
1da177e4
LT		 565 if (__cpu_has_fpu())
566 c->options |= MIPS_CPU_FPU;
567 c->tlbsize = 64;
568 break;
569 case PRID_IMP_R3000:
8ff374b9 570 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
cea7e2df 571 if (cpu_has_confreg()) {
1da177e4 572 c->cputype = CPU_R3081E;
cea7e2df
RB		 573 __cpu_name[cpu] = "R3081";
574 } else {
1da177e4 575 c->cputype = CPU_R3000A;
cea7e2df
RB		 576 __cpu_name[cpu] = "R3000A";
577 }
cea7e2df 578 } else {
1da177e4 579 c->cputype = CPU_R3000;
cea7e2df
RB		 580 __cpu_name[cpu] = "R3000";
581 }
02cf2119 582 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 583 MIPS_CPU_NOFPUEX;
1da177e4
LT		 584 if (__cpu_has_fpu())
585 c->options |= MIPS_CPU_FPU;
586 c->tlbsize = 64;
587 break;
588 case PRID_IMP_R4000:
589 if (read_c0_config() & CONF_SC) {
8ff374b9
MR		 590 if ((c->processor_id & PRID_REV_MASK) >=
591 PRID_REV_R4400) {
1da177e4 592 c->cputype = CPU_R4400PC;
cea7e2df
RB		 593 __cpu_name[cpu] = "R4400PC";
594 } else {
1da177e4 595 c->cputype = CPU_R4000PC;
cea7e2df
RB		 596 __cpu_name[cpu] = "R4000PC";
597 }
1da177e4 598 } else {
7f177a52
MR		 599 int cca = read_c0_config() & CONF_CM_CMASK;
600 int mc;
601
602 /*
603 * SC and MC versions can't be reliably told apart,
604 * but only the latter support coherent caching
605 * modes so assume the firmware has set the KSEG0
606 * coherency attribute reasonably (if uncached, we
607 * assume SC).
608 */
609 switch (cca) {
610 case CONF_CM_CACHABLE_CE:
611 case CONF_CM_CACHABLE_COW:
612 case CONF_CM_CACHABLE_CUW:
613 mc = 1;
614 break;
615 default:
616 mc = 0;
617 break;
618 }
8ff374b9
MR		 619 if ((c->processor_id & PRID_REV_MASK) >=
620 PRID_REV_R4400) {
7f177a52
MR		 621 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
622 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
cea7e2df 623 } else {
7f177a52
MR		 624 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
625 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
cea7e2df 626 }
1da177e4
LT		 627 }
628
a96102be 629 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 630 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 631 MIPS_CPU_WATCH | MIPS_CPU_VCE |
632 MIPS_CPU_LLSC;
1da177e4
LT		 633 c->tlbsize = 48;
634 break;
635 case PRID_IMP_VR41XX:
9f91e506
YY		 636 set_isa(c, MIPS_CPU_ISA_III);
637 c->options = R4K_OPTS;
638 c->tlbsize = 32;
1da177e4 639 switch (c->processor_id & 0xf0) {
1da177e4
LT		 640 case PRID_REV_VR4111:
641 c->cputype = CPU_VR4111;
cea7e2df 642 __cpu_name[cpu] = "NEC VR4111";
1da177e4 643 break;
1da177e4
LT		 644 case PRID_REV_VR4121:
645 c->cputype = CPU_VR4121;
cea7e2df 646 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 647 break;
648 case PRID_REV_VR4122:
cea7e2df 649 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 650 c->cputype = CPU_VR4122;
cea7e2df
RB		 651 __cpu_name[cpu] = "NEC VR4122";
652 } else {
1da177e4 653 c->cputype = CPU_VR4181A;
cea7e2df
RB		 654 __cpu_name[cpu] = "NEC VR4181A";
655 }
1da177e4
LT		 656 break;
657 case PRID_REV_VR4130:
cea7e2df 658 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 659 c->cputype = CPU_VR4131;
cea7e2df
RB		 660 __cpu_name[cpu] = "NEC VR4131";
661 } else {
1da177e4 662 c->cputype = CPU_VR4133;
9f91e506 663 c->options |= MIPS_CPU_LLSC;
cea7e2df
RB		 664 __cpu_name[cpu] = "NEC VR4133";
665 }
1da177e4
LT		 666 break;
667 default:
668 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
669 c->cputype = CPU_VR41XX;
cea7e2df 670 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 671 break;
672 }
1da177e4
LT		 673 break;
674 case PRID_IMP_R4300:
675 c->cputype = CPU_R4300;
cea7e2df 676 __cpu_name[cpu] = "R4300";
a96102be 677 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 678 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 679 MIPS_CPU_LLSC;
1da177e4
LT		 680 c->tlbsize = 32;
681 break;
682 case PRID_IMP_R4600:
683 c->cputype = CPU_R4600;
cea7e2df 684 __cpu_name[cpu] = "R4600";
a96102be 685 set_isa(c, MIPS_CPU_ISA_III);
075e7502
TS		 686 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
687 MIPS_CPU_LLSC;
1da177e4
LT		 688 c->tlbsize = 48;
689 break;
690 #if 0
03751e79 691 case PRID_IMP_R4650:
1da177e4
LT		 692 /*
693 * This processor doesn't have an MMU, so it's not
694 * "real easy" to run Linux on it. It is left purely
695 * for documentation. Commented out because it shares
696 * it's c0_prid id number with the TX3900.
697 */
a3dddd56 698 c->cputype = CPU_R4650;
cea7e2df 699 __cpu_name[cpu] = "R4650";
a96102be 700 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 701 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 702 c->tlbsize = 48;
1da177e4
LT		 703 break;
704 #endif
705 case PRID_IMP_TX39:
02cf2119 706 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 707
708 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
709 c->cputype = CPU_TX3927;
cea7e2df 710 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 711 c->tlbsize = 64;
712 } else {
8ff374b9 713 switch (c->processor_id & PRID_REV_MASK) {
1da177e4
LT		 714 case PRID_REV_TX3912:
715 c->cputype = CPU_TX3912;
cea7e2df 716 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 717 c->tlbsize = 32;
718 break;
719 case PRID_REV_TX3922:
720 c->cputype = CPU_TX3922;
cea7e2df 721 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 722 c->tlbsize = 64;
723 break;
1da177e4
LT		 724 }
725 }
726 break;
727 case PRID_IMP_R4700:
728 c->cputype = CPU_R4700;
cea7e2df 729 __cpu_name[cpu] = "R4700";
a96102be 730 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 731 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 732 MIPS_CPU_LLSC;
1da177e4
LT		 733 c->tlbsize = 48;
734 break;
735 case PRID_IMP_TX49:
736 c->cputype = CPU_TX49XX;
cea7e2df 737 __cpu_name[cpu] = "R49XX";
a96102be 738 set_isa(c, MIPS_CPU_ISA_III);
1da177e4
LT		 739 c->options = R4K_OPTS | MIPS_CPU_LLSC;
740 if (!(c->processor_id & 0x08))
741 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
742 c->tlbsize = 48;
743 break;
744 case PRID_IMP_R5000:
745 c->cputype = CPU_R5000;
cea7e2df 746 __cpu_name[cpu] = "R5000";
a96102be 747 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 748 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 749 MIPS_CPU_LLSC;
1da177e4
LT		 750 c->tlbsize = 48;
751 break;
752 case PRID_IMP_R5432:
753 c->cputype = CPU_R5432;
cea7e2df 754 __cpu_name[cpu] = "R5432";
a96102be 755 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 756 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 757 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 758 c->tlbsize = 48;
759 break;
760 case PRID_IMP_R5500:
761 c->cputype = CPU_R5500;
cea7e2df 762 __cpu_name[cpu] = "R5500";
a96102be 763 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 764 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 765 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 766 c->tlbsize = 48;
767 break;
768 case PRID_IMP_NEVADA:
769 c->cputype = CPU_NEVADA;
cea7e2df 770 __cpu_name[cpu] = "Nevada";
a96102be 771 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 772 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 773 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 774 c->tlbsize = 48;
775 break;
776 case PRID_IMP_R6000:
777 c->cputype = CPU_R6000;
cea7e2df 778 __cpu_name[cpu] = "R6000";
a96102be 779 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 780 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 781 MIPS_CPU_LLSC;
1da177e4
LT		 782 c->tlbsize = 32;
783 break;
784 case PRID_IMP_R6000A:
785 c->cputype = CPU_R6000A;
cea7e2df 786 __cpu_name[cpu] = "R6000A";
a96102be 787 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 788 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 789 MIPS_CPU_LLSC;
1da177e4
LT		 790 c->tlbsize = 32;
791 break;
792 case PRID_IMP_RM7000:
793 c->cputype = CPU_RM7000;
cea7e2df 794 __cpu_name[cpu] = "RM7000";
a96102be 795 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 796 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 797 MIPS_CPU_LLSC;
1da177e4 798 /*
70342287 799 * Undocumented RM7000: Bit 29 in the info register of
1da177e4
LT		 800 * the RM7000 v2.0 indicates if the TLB has 48 or 64
801 * entries.
802 *
70342287
RB		 803 * 29 1 => 64 entry JTLB
804 * 0 => 48 entry JTLB
1da177e4
LT		 805 */
806 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1da177e4
LT		 807 break;
808 case PRID_IMP_R8000:
809 c->cputype = CPU_R8000;
cea7e2df 810 __cpu_name[cpu] = "RM8000";
a96102be 811 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 812 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 813 MIPS_CPU_FPU | MIPS_CPU_32FPR |
814 MIPS_CPU_LLSC;
1da177e4
LT		 815 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
816 break;
817 case PRID_IMP_R10000:
818 c->cputype = CPU_R10000;
cea7e2df 819 __cpu_name[cpu] = "R10000";
a96102be 820 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 821 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 822 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 823 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 824 MIPS_CPU_LLSC;
1da177e4
LT		 825 c->tlbsize = 64;
826 break;
827 case PRID_IMP_R12000:
828 c->cputype = CPU_R12000;
cea7e2df 829 __cpu_name[cpu] = "R12000";
a96102be 830 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 831 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 832 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 833 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 834 MIPS_CPU_LLSC;
1da177e4
LT		 835 c->tlbsize = 64;
836 break;
44d921b2
K		 837 case PRID_IMP_R14000:
838 c->cputype = CPU_R14000;
cea7e2df 839 __cpu_name[cpu] = "R14000";
a96102be 840 set_isa(c, MIPS_CPU_ISA_IV);
44d921b2 841 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 842 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 843 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 844 MIPS_CPU_LLSC;
44d921b2
K		 845 c->tlbsize = 64;
846 break;
26859198 847 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
5aac1e8a
RM		 848 switch (c->processor_id & PRID_REV_MASK) {
849 case PRID_REV_LOONGSON2E:
c579d310
HC		 850 c->cputype = CPU_LOONGSON2;
851 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 852 set_elf_platform(cpu, "loongson2e");
7352c8b1 853 set_isa(c, MIPS_CPU_ISA_III);
5aac1e8a
RM		 854 break;
855 case PRID_REV_LOONGSON2F:
c579d310
HC		 856 c->cputype = CPU_LOONGSON2;
857 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 858 set_elf_platform(cpu, "loongson2f");
7352c8b1 859 set_isa(c, MIPS_CPU_ISA_III);
5aac1e8a 860 break;
c579d310
HC		 861 case PRID_REV_LOONGSON3A:
862 c->cputype = CPU_LOONGSON3;
863 __cpu_name[cpu] = "ICT Loongson-3";
864 set_elf_platform(cpu, "loongson3a");
7352c8b1 865 set_isa(c, MIPS_CPU_ISA_M64R1);
c579d310 866 break;
e7841be5
HC		 867 case PRID_REV_LOONGSON3B_R1:
868 case PRID_REV_LOONGSON3B_R2:
869 c->cputype = CPU_LOONGSON3;
870 __cpu_name[cpu] = "ICT Loongson-3";
871 set_elf_platform(cpu, "loongson3b");
7352c8b1 872 set_isa(c, MIPS_CPU_ISA_M64R1);
e7841be5 873 break;
5aac1e8a
RM		 874 }
875
2a21c730
FZ		 876 c->options = R4K_OPTS |
877 MIPS_CPU_FPU | MIPS_CPU_LLSC |
878 MIPS_CPU_32FPR;
879 c->tlbsize = 64;
cc94ea31 880 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2a21c730 881 break;
26859198 882 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
2fa36399 883 decode_configs(c);
b4672d37 884
2fa36399 885 c->cputype = CPU_LOONGSON1;
1da177e4 886
2fa36399
KC		 887 switch (c->processor_id & PRID_REV_MASK) {
888 case PRID_REV_LOONGSON1B:
889 __cpu_name[cpu] = "Loongson 1B";
b4672d37 890 break;
b4672d37 891 }
4194318c 892
2fa36399 893 break;
1da177e4 894 }
1da177e4
LT		 895}
896
cea7e2df 897static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 898{
4f12b91d 899 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 900 switch (c->processor_id & PRID_IMP_MASK) {
b2498af5
LY		 901 case PRID_IMP_QEMU_GENERIC:
902 c->writecombine = _CACHE_UNCACHED;
903 c->cputype = CPU_QEMU_GENERIC;
904 __cpu_name[cpu] = "MIPS GENERIC QEMU";
905 break;
1da177e4
LT		 906 case PRID_IMP_4KC:
907 c->cputype = CPU_4KC;
4f12b91d 908 c->writecombine = _CACHE_UNCACHED;
cea7e2df 909 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 910 break;
911 case PRID_IMP_4KEC:
2b07bd02
RB		 912 case PRID_IMP_4KECR2:
913 c->cputype = CPU_4KEC;
4f12b91d 914 c->writecombine = _CACHE_UNCACHED;
cea7e2df 915 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 916 break;
1da177e4 917 case PRID_IMP_4KSC:
8afcb5d8 918 case PRID_IMP_4KSD:
1da177e4 919 c->cputype = CPU_4KSC;
4f12b91d 920 c->writecombine = _CACHE_UNCACHED;
cea7e2df 921 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 922 break;
923 case PRID_IMP_5KC:
924 c->cputype = CPU_5KC;
4f12b91d 925 c->writecombine = _CACHE_UNCACHED;
cea7e2df 926 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4 927 break;
78d4803f
LY		 928 case PRID_IMP_5KE:
929 c->cputype = CPU_5KE;
4f12b91d 930 c->writecombine = _CACHE_UNCACHED;
78d4803f
LY		 931 __cpu_name[cpu] = "MIPS 5KE";
932 break;
1da177e4
LT		 933 case PRID_IMP_20KC:
934 c->cputype = CPU_20KC;
4f12b91d 935 c->writecombine = _CACHE_UNCACHED;
cea7e2df 936 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 937 break;
938 case PRID_IMP_24K:
939 c->cputype = CPU_24K;
4f12b91d 940 c->writecombine = _CACHE_UNCACHED;
cea7e2df 941 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4 942 break;
42f3caef
JC		 943 case PRID_IMP_24KE:
944 c->cputype = CPU_24K;
4f12b91d 945 c->writecombine = _CACHE_UNCACHED;
42f3caef
JC		 946 __cpu_name[cpu] = "MIPS 24KEc";
947 break;
1da177e4
LT		 948 case PRID_IMP_25KF:
949 c->cputype = CPU_25KF;
4f12b91d 950 c->writecombine = _CACHE_UNCACHED;
cea7e2df 951 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 952 break;
bbc7f22f
RB		 953 case PRID_IMP_34K:
954 c->cputype = CPU_34K;
4f12b91d 955 c->writecombine = _CACHE_UNCACHED;
cea7e2df 956 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 957 break;
c620953c
CD		 958 case PRID_IMP_74K:
959 c->cputype = CPU_74K;
4f12b91d 960 c->writecombine = _CACHE_UNCACHED;
cea7e2df 961 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 962 break;
113c62d9
SH		 963 case PRID_IMP_M14KC:
964 c->cputype = CPU_M14KC;
4f12b91d 965 c->writecombine = _CACHE_UNCACHED;
113c62d9
SH		 966 __cpu_name[cpu] = "MIPS M14Kc";
967 break;
f8fa4811
SH		 968 case PRID_IMP_M14KEC:
969 c->cputype = CPU_M14KEC;
4f12b91d 970 c->writecombine = _CACHE_UNCACHED;
f8fa4811
SH		 971 __cpu_name[cpu] = "MIPS M14KEc";
972 break;
39b8d525
RB		 973 case PRID_IMP_1004K:
974 c->cputype = CPU_1004K;
4f12b91d 975 c->writecombine = _CACHE_UNCACHED;
cea7e2df 976 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 977 break;
006a851b 978 case PRID_IMP_1074K:
442e14a2 979 c->cputype = CPU_1074K;
4f12b91d 980 c->writecombine = _CACHE_UNCACHED;
006a851b
SH		 981 __cpu_name[cpu] = "MIPS 1074Kc";
982 break;
b5f065e7
LY		 983 case PRID_IMP_INTERAPTIV_UP:
984 c->cputype = CPU_INTERAPTIV;
985 __cpu_name[cpu] = "MIPS interAptiv";
986 break;
987 case PRID_IMP_INTERAPTIV_MP:
988 c->cputype = CPU_INTERAPTIV;
989 __cpu_name[cpu] = "MIPS interAptiv (multi)";
990 break;
b0d4d300
LY		 991 case PRID_IMP_PROAPTIV_UP:
992 c->cputype = CPU_PROAPTIV;
993 __cpu_name[cpu] = "MIPS proAptiv";
994 break;
995 case PRID_IMP_PROAPTIV_MP:
996 c->cputype = CPU_PROAPTIV;
997 __cpu_name[cpu] = "MIPS proAptiv (multi)";
998 break;
829dcc0a
JH		 999 case PRID_IMP_P5600:
1000 c->cputype = CPU_P5600;
1001 __cpu_name[cpu] = "MIPS P5600";
1002 break;
9943ed92
LY		 1003 case PRID_IMP_M5150:
1004 c->cputype = CPU_M5150;
1005 __cpu_name[cpu] = "MIPS M5150";
1006 break;
1da177e4 1007 }
0b6d497f 1008
75b5b5e0
LY		 1009 decode_configs(c);
1010
0b6d497f 1011 spram_config();
1da177e4
LT		 1012}
1013
cea7e2df 1014static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1015{
4194318c 1016 decode_configs(c);
8ff374b9 1017 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1018 case PRID_IMP_AU1_REV1:
1019 case PRID_IMP_AU1_REV2:
270717a8 1020 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 1021 switch ((c->processor_id >> 24) & 0xff) {
1022 case 0:
cea7e2df 1023 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 1024 break;
1025 case 1:
cea7e2df 1026 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 1027 break;
1028 case 2:
cea7e2df 1029 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 1030 break;
1031 case 3:
cea7e2df 1032 __cpu_name[cpu] = "Au1550";
1da177e4 1033 break;
e3ad1c23 1034 case 4:
cea7e2df 1035 __cpu_name[cpu] = "Au1200";
8ff374b9 1036 if ((c->processor_id & PRID_REV_MASK) == 2)
cea7e2df 1037 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 1038 break;
1039 case 5:
cea7e2df 1040 __cpu_name[cpu] = "Au1210";
e3ad1c23 1041 break;
1da177e4 1042 default:
270717a8 1043 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 1044 break;
1045 }
1da177e4
LT		 1046 break;
1047 }
1048}
1049
cea7e2df 1050static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1051{
4194318c 1052 decode_configs(c);
02cf2119 1053
4f12b91d 1054 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 1055 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1056 case PRID_IMP_SB1:
1057 c->cputype = CPU_SB1;
cea7e2df 1058 __cpu_name[cpu] = "SiByte SB1";
1da177e4 1059 /* FPU in pass1 is known to have issues. */
8ff374b9 1060 if ((c->processor_id & PRID_REV_MASK) < 0x02)
010b853b 1061 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 1062 break;
93ce2f52
AI		 1063 case PRID_IMP_SB1A:
1064 c->cputype = CPU_SB1A;
cea7e2df 1065 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 1066 break;
1da177e4
LT		 1067 }
1068}
1069
cea7e2df 1070static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1071{
4194318c 1072 decode_configs(c);
8ff374b9 1073 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1074 case PRID_IMP_SR71000:
1075 c->cputype = CPU_SR71000;
cea7e2df 1076 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 1077 c->scache.ways = 8;
1078 c->tlbsize = 64;
1079 break;
1080 }
1081}
1082
cea7e2df 1083static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 1084{
1085 decode_configs(c);
8ff374b9 1086 switch (c->processor_id & PRID_IMP_MASK) {
bdf21b18
PP		 1087 case PRID_IMP_PR4450:
1088 c->cputype = CPU_PR4450;
cea7e2df 1089 __cpu_name[cpu] = "Philips PR4450";
a96102be 1090 set_isa(c, MIPS_CPU_ISA_M32R1);
bdf21b18 1091 break;
bdf21b18
PP		 1092 }
1093}
1094
cea7e2df 1095static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 1096{
1097 decode_configs(c);
8ff374b9 1098 switch (c->processor_id & PRID_IMP_MASK) {
190fca3e
KC		 1099 case PRID_IMP_BMIPS32_REV4:
1100 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 1101 c->cputype = CPU_BMIPS32;
1102 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 1103 set_elf_platform(cpu, "bmips32");
602977b0
KC		 1104 break;
1105 case PRID_IMP_BMIPS3300:
1106 case PRID_IMP_BMIPS3300_ALT:
1107 case PRID_IMP_BMIPS3300_BUG:
1108 c->cputype = CPU_BMIPS3300;
1109 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 1110 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 1111 break;
1112 case PRID_IMP_BMIPS43XX: {
8ff374b9 1113 int rev = c->processor_id & PRID_REV_MASK;
602977b0
KC		 1114
1115 if (rev >= PRID_REV_BMIPS4380_LO &&
1116 rev <= PRID_REV_BMIPS4380_HI) {
1117 c->cputype = CPU_BMIPS4380;
1118 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 1119 set_elf_platform(cpu, "bmips4380");
602977b0
KC		 1120 } else {
1121 c->cputype = CPU_BMIPS4350;
1122 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 1123 set_elf_platform(cpu, "bmips4350");
602977b0 1124 }
0de663ef 1125 break;
602977b0
KC		 1126 }
1127 case PRID_IMP_BMIPS5000:
68e6a783 1128 case PRID_IMP_BMIPS5200:
602977b0
KC		 1129 c->cputype = CPU_BMIPS5000;
1130 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 1131 set_elf_platform(cpu, "bmips5000");
602977b0 1132 c->options |= MIPS_CPU_ULRI;
0de663ef 1133 break;
1c0c13eb
AJ		 1134 }
1135}
1136
0dd4781b
DD		 1137static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1138{
1139 decode_configs(c);
8ff374b9 1140 switch (c->processor_id & PRID_IMP_MASK) {
0dd4781b
DD		 1141 case PRID_IMP_CAVIUM_CN38XX:
1142 case PRID_IMP_CAVIUM_CN31XX:
1143 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 1144 c->cputype = CPU_CAVIUM_OCTEON;
1145 __cpu_name[cpu] = "Cavium Octeon";
1146 goto platform;
0dd4781b
DD		 1147 case PRID_IMP_CAVIUM_CN58XX:
1148 case PRID_IMP_CAVIUM_CN56XX:
1149 case PRID_IMP_CAVIUM_CN50XX:
1150 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 1151 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1152 __cpu_name[cpu] = "Cavium Octeon+";
1153platform:
c094c99e 1154 set_elf_platform(cpu, "octeon");
0dd4781b 1155 break;
a1431b61 1156 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 1157 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 1158 case PRID_IMP_CAVIUM_CN66XX:
1159 case PRID_IMP_CAVIUM_CN68XX:
af04bb85 1160 case PRID_IMP_CAVIUM_CNF71XX:
0e56b385
DD		 1161 c->cputype = CPU_CAVIUM_OCTEON2;
1162 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 1163 set_elf_platform(cpu, "octeon2");
0e56b385 1164 break;
af04bb85
DD		 1165 case PRID_IMP_CAVIUM_CN70XX:
1166 case PRID_IMP_CAVIUM_CN78XX:
1167 c->cputype = CPU_CAVIUM_OCTEON3;
1168 __cpu_name[cpu] = "Cavium Octeon III";
1169 set_elf_platform(cpu, "octeon3");
1170 break;
0dd4781b
DD		 1171 default:
1172 printk(KERN_INFO "Unknown Octeon chip!\n");
1173 c->cputype = CPU_UNKNOWN;
1174 break;
1175 }
1176}
1177
83ccf69d
LPC		 1178static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1179{
1180 decode_configs(c);
1181 /* JZRISC does not implement the CP0 counter. */
1182 c->options &= ~MIPS_CPU_COUNTER;
06947aaa 1183 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
8ff374b9 1184 switch (c->processor_id & PRID_IMP_MASK) {
83ccf69d
LPC		 1185 case PRID_IMP_JZRISC:
1186 c->cputype = CPU_JZRISC;
4f12b91d 1187 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
83ccf69d
LPC		 1188 __cpu_name[cpu] = "Ingenic JZRISC";
1189 break;
1190 default:
1191 panic("Unknown Ingenic Processor ID!");
1192 break;
1193 }
1194}
1195
a7117c6b
J		 1196static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1197{
1198 decode_configs(c);
1199
8ff374b9 1200 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
809f36c6
ML		 1201 c->cputype = CPU_ALCHEMY;
1202 __cpu_name[cpu] = "Au1300";
1203 /* following stuff is not for Alchemy */
1204 return;
1205 }
1206
70342287
RB		 1207 c->options = (MIPS_CPU_TLB |
1208 MIPS_CPU_4KEX |
a7117c6b 1209 MIPS_CPU_COUNTER |
70342287
RB		 1210 MIPS_CPU_DIVEC |
1211 MIPS_CPU_WATCH |
1212 MIPS_CPU_EJTAG |
a7117c6b
J		 1213 MIPS_CPU_LLSC);
1214
8ff374b9 1215 switch (c->processor_id & PRID_IMP_MASK) {
4ca86a2f 1216 case PRID_IMP_NETLOGIC_XLP2XX:
8907c55e 1217 case PRID_IMP_NETLOGIC_XLP9XX:
1c983986 1218 case PRID_IMP_NETLOGIC_XLP5XX:
4ca86a2f
J		 1219 c->cputype = CPU_XLP;
1220 __cpu_name[cpu] = "Broadcom XLPII";
1221 break;
1222
2aa54b20
J		 1223 case PRID_IMP_NETLOGIC_XLP8XX:
1224 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 1225 c->cputype = CPU_XLP;
1226 __cpu_name[cpu] = "Netlogic XLP";
1227 break;
1228
a7117c6b
J		 1229 case PRID_IMP_NETLOGIC_XLR732:
1230 case PRID_IMP_NETLOGIC_XLR716:
1231 case PRID_IMP_NETLOGIC_XLR532:
1232 case PRID_IMP_NETLOGIC_XLR308:
1233 case PRID_IMP_NETLOGIC_XLR532C:
1234 case PRID_IMP_NETLOGIC_XLR516C:
1235 case PRID_IMP_NETLOGIC_XLR508C:
1236 case PRID_IMP_NETLOGIC_XLR308C:
1237 c->cputype = CPU_XLR;
1238 __cpu_name[cpu] = "Netlogic XLR";
1239 break;
1240
1241 case PRID_IMP_NETLOGIC_XLS608:
1242 case PRID_IMP_NETLOGIC_XLS408:
1243 case PRID_IMP_NETLOGIC_XLS404:
1244 case PRID_IMP_NETLOGIC_XLS208:
1245 case PRID_IMP_NETLOGIC_XLS204:
1246 case PRID_IMP_NETLOGIC_XLS108:
1247 case PRID_IMP_NETLOGIC_XLS104:
1248 case PRID_IMP_NETLOGIC_XLS616B:
1249 case PRID_IMP_NETLOGIC_XLS608B:
1250 case PRID_IMP_NETLOGIC_XLS416B:
1251 case PRID_IMP_NETLOGIC_XLS412B:
1252 case PRID_IMP_NETLOGIC_XLS408B:
1253 case PRID_IMP_NETLOGIC_XLS404B:
1254 c->cputype = CPU_XLR;
1255 __cpu_name[cpu] = "Netlogic XLS";
1256 break;
1257
1258 default:
a3d4fb2d 1259 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 1260 c->processor_id);
1261 c->cputype = CPU_XLR;
1262 break;
1263 }
1264
a3d4fb2d 1265 if (c->cputype == CPU_XLP) {
a96102be 1266 set_isa(c, MIPS_CPU_ISA_M64R2);
a3d4fb2d
J		 1267 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1268 /* This will be updated again after all threads are woken up */
1269 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1270 } else {
a96102be 1271 set_isa(c, MIPS_CPU_ISA_M64R1);
a3d4fb2d
J		 1272 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1273 }
7777b939 1274 c->kscratch_mask = 0xf;
a7117c6b
J		 1275}
1276
949e51be
DD		 1277#ifdef CONFIG_64BIT
1278/* For use by uaccess.h */
1279u64 __ua_limit;
1280EXPORT_SYMBOL(__ua_limit);
1281#endif
1282
9966db25 1283const char *__cpu_name[NR_CPUS];
874fd3b5 1284const char *__elf_platform;
9966db25 1285
078a55fc 1286void cpu_probe(void)
1da177e4
LT		 1287{
1288 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 1289 unsigned int cpu = smp_processor_id();
1da177e4 1290
70342287 1291 c->processor_id = PRID_IMP_UNKNOWN;
1da177e4
LT		 1292 c->fpu_id = FPIR_IMP_NONE;
1293 c->cputype = CPU_UNKNOWN;
4f12b91d 1294 c->writecombine = _CACHE_UNCACHED;
1da177e4
LT		 1295
1296 c->processor_id = read_c0_prid();
8ff374b9 1297 switch (c->processor_id & PRID_COMP_MASK) {
1da177e4 1298 case PRID_COMP_LEGACY:
cea7e2df 1299 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1300 break;
1301 case PRID_COMP_MIPS:
cea7e2df 1302 cpu_probe_mips(c, cpu);
1da177e4
LT		 1303 break;
1304 case PRID_COMP_ALCHEMY:
cea7e2df 1305 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1306 break;
1307 case PRID_COMP_SIBYTE:
cea7e2df 1308 cpu_probe_sibyte(c, cpu);
1da177e4 1309 break;
1c0c13eb 1310 case PRID_COMP_BROADCOM:
cea7e2df 1311 cpu_probe_broadcom(c, cpu);
1c0c13eb 1312 break;
1da177e4 1313 case PRID_COMP_SANDCRAFT:
cea7e2df 1314 cpu_probe_sandcraft(c, cpu);
1da177e4 1315 break;
a92b0588 1316 case PRID_COMP_NXP:
cea7e2df 1317 cpu_probe_nxp(c, cpu);
a3dddd56 1318 break;
0dd4781b
DD		 1319 case PRID_COMP_CAVIUM:
1320 cpu_probe_cavium(c, cpu);
1321 break;
83ccf69d
LPC		 1322 case PRID_COMP_INGENIC:
1323 cpu_probe_ingenic(c, cpu);
1324 break;
a7117c6b
J		 1325 case PRID_COMP_NETLOGIC:
1326 cpu_probe_netlogic(c, cpu);
1327 break;
1da177e4 1328 }
dec8b1ca 1329
cea7e2df
RB		 1330 BUG_ON(!__cpu_name[cpu]);
1331 BUG_ON(c->cputype == CPU_UNKNOWN);
1332
dec8b1ca
FBH		 1333 /*
1334 * Platform code can force the cpu type to optimize code
1335 * generation. In that case be sure the cpu type is correctly
1336 * manually setup otherwise it could trigger some nasty bugs.
1337 */
1338 BUG_ON(current_cpu_type() != c->cputype);
1339
0103d23f
KC		 1340 if (mips_fpu_disabled)
1341 c->options &= ~MIPS_CPU_FPU;
1342
1343 if (mips_dsp_disabled)
ee80f7c7 1344 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f 1345
3d528b32
MC		 1346 if (mips_htw_disabled) {
1347 c->options &= ~MIPS_CPU_HTW;
1348 write_c0_pwctl(read_c0_pwctl() &
1349 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1350 }
1351
4194318c 1352 if (c->options & MIPS_CPU_FPU) {
1da177e4 1353 c->fpu_id = cpu_get_fpu_id();
4194318c 1354
adb37892
DCZ		 1355 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1356 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
4194318c
RB		 1357 if (c->fpu_id & MIPS_FPIR_3D)
1358 c->ases |= MIPS_ASE_MIPS3D;
adac5d53
PB		 1359 if (c->fpu_id & MIPS_FPIR_FREP)
1360 c->options |= MIPS_CPU_FRE;
4194318c
RB		 1361 }
1362 }
9966db25 1363
da4b62cd 1364 if (cpu_has_mips_r2) {
f6771dbb 1365 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
da4b62cd
AC		 1366 /* R2 has Performance Counter Interrupt indicator */
1367 c->options |= MIPS_CPU_PCI;
1368 }
f6771dbb
RB		 1369 else
1370 c->srsets = 1;
91dfc423 1371
a8ad1367 1372 if (cpu_has_msa) {
a5e9a69e 1373 c->msa_id = cpu_get_msa_id();
a8ad1367
PB		 1374 WARN(c->msa_id & MSA_IR_WRPF,
1375 "Vector register partitioning unimplemented!");
1376 }
a5e9a69e 1377
91dfc423 1378 cpu_probe_vmbits(c);
949e51be
DD		 1379
1380#ifdef CONFIG_64BIT
1381 if (cpu == 0)
1382 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1383#endif
1da177e4
LT		 1384}
1385
078a55fc 1386void cpu_report(void)
1da177e4
LT		 1387{
1388 struct cpuinfo_mips *c = &current_cpu_data;
1389
d9f897c9
LY		 1390 pr_info("CPU%d revision is: %08x (%s)\n",
1391 smp_processor_id(), c->processor_id, cpu_name_string());
1da177e4 1392 if (c->options & MIPS_CPU_FPU)
9966db25 1393 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
a5e9a69e
PB		 1394 if (cpu_has_msa)
1395 pr_info("MSA revision is: %08x\n", c->msa_id);
1da177e4 1396}
Linux 6.x block layer and io_uring tree(s)