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MIPS: Loongson-3: Set cache flush handlers to cache_noop
[linux-2.6-block.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
70342287 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4 22#include <asm/cpu.h>
f6843626 23#include <asm/cpu-features.h>
69f24d17 24#include <asm/cpu-type.h>
1da177e4
LT		 25#include <asm/fpu.h>
26#include <asm/mipsregs.h>
30ee615b 27#include <asm/mipsmtregs.h>
a5e9a69e 28#include <asm/msa.h>
654f57bf 29#include <asm/watch.h>
06372a63 30#include <asm/elf.h>
4f12b91d 31#include <asm/pgtable-bits.h>
a074f0e8 32#include <asm/spram.h>
949e51be
DD		 33#include <asm/uaccess.h>
34
e14f1db7
PB		 35/* Hardware capabilities */
36unsigned int elf_hwcap __read_mostly;
37
7aecd5ca
MR		 38/*
39 * Get the FPU Implementation/Revision.
40 */
41static inline unsigned long cpu_get_fpu_id(void)
42{
43 unsigned long tmp, fpu_id;
44
45 tmp = read_c0_status();
46 __enable_fpu(FPU_AS_IS);
47 fpu_id = read_32bit_cp1_register(CP1_REVISION);
48 write_c0_status(tmp);
49 return fpu_id;
50}
51
52/*
53 * Check if the CPU has an external FPU.
54 */
55static inline int __cpu_has_fpu(void)
56{
57 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
58}
59
60static inline unsigned long cpu_get_msa_id(void)
61{
62 unsigned long status, msa_id;
63
64 status = read_c0_status();
65 __enable_fpu(FPU_64BIT);
66 enable_msa();
67 msa_id = read_msa_ir();
68 disable_msa();
69 write_c0_status(status);
70 return msa_id;
71}
72
9b26616c
MR		 73/*
74 * Determine the FCSR mask for FPU hardware.
75 */
76static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
77{
78 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
79
90b712dd 80 fcsr = c->fpu_csr31;
9b26616c
MR		 81 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
82
83 sr = read_c0_status();
84 __enable_fpu(FPU_AS_IS);
85
9b26616c
MR		 86 fcsr0 = fcsr & mask;
87 write_32bit_cp1_register(CP1_STATUS, fcsr0);
88 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
89
90 fcsr1 = fcsr | ~mask;
91 write_32bit_cp1_register(CP1_STATUS, fcsr1);
92 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
93
94 write_32bit_cp1_register(CP1_STATUS, fcsr);
95
96 write_c0_status(sr);
97
98 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
99}
100
93adeaf6
MR		 101/*
102 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
103 * supported by FPU hardware.
104 */
105static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
106{
107 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
108 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
109 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
110 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
111
112 sr = read_c0_status();
113 __enable_fpu(FPU_AS_IS);
114
115 fir = read_32bit_cp1_register(CP1_REVISION);
116 if (fir & MIPS_FPIR_HAS2008) {
117 fcsr = read_32bit_cp1_register(CP1_STATUS);
118
119 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
120 write_32bit_cp1_register(CP1_STATUS, fcsr0);
121 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
122
123 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
124 write_32bit_cp1_register(CP1_STATUS, fcsr1);
125 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
126
127 write_32bit_cp1_register(CP1_STATUS, fcsr);
128
129 if (!(fcsr0 & FPU_CSR_NAN2008))
130 c->options |= MIPS_CPU_NAN_LEGACY;
131 if (fcsr1 & FPU_CSR_NAN2008)
132 c->options |= MIPS_CPU_NAN_2008;
133
134 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
135 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
136 else
137 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
138
139 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
140 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
141 else
142 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
143 } else {
144 c->options |= MIPS_CPU_NAN_LEGACY;
145 }
146
147 write_c0_status(sr);
148 } else {
149 c->options |= MIPS_CPU_NAN_LEGACY;
150 }
151}
152
153/*
503943e0
MR		 154 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
155 * ABS.fmt/NEG.fmt execution mode.
156 */
157static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
158
159/*
160 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
161 * to support by the FPU emulator according to the IEEE 754 conformance
162 * mode selected. Note that "relaxed" straps the emulator so that it
163 * allows 2008-NaN binaries even for legacy processors.
93adeaf6
MR		 164 */
165static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
166{
503943e0 167 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
93adeaf6 168 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
503943e0
MR		 169 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
170
171 switch (ieee754) {
172 case STRICT:
173 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
174 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
175 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
176 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
177 } else {
178 c->options |= MIPS_CPU_NAN_LEGACY;
179 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
180 }
181 break;
182 case LEGACY:
93adeaf6
MR		 183 c->options |= MIPS_CPU_NAN_LEGACY;
184 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
503943e0
MR		 185 break;
186 case STD2008:
187 c->options |= MIPS_CPU_NAN_2008;
188 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
189 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
190 break;
191 case RELAXED:
192 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
193 break;
93adeaf6
MR		 194 }
195}
196
503943e0
MR		 197/*
198 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
199 * according to the "ieee754=" parameter.
200 */
201static void cpu_set_nan_2008(struct cpuinfo_mips *c)
202{
203 switch (ieee754) {
204 case STRICT:
205 mips_use_nan_legacy = !!cpu_has_nan_legacy;
206 mips_use_nan_2008 = !!cpu_has_nan_2008;
207 break;
208 case LEGACY:
209 mips_use_nan_legacy = !!cpu_has_nan_legacy;
210 mips_use_nan_2008 = !cpu_has_nan_legacy;
211 break;
212 case STD2008:
213 mips_use_nan_legacy = !cpu_has_nan_2008;
214 mips_use_nan_2008 = !!cpu_has_nan_2008;
215 break;
216 case RELAXED:
217 mips_use_nan_legacy = true;
218 mips_use_nan_2008 = true;
219 break;
220 }
221}
222
223/*
224 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
225 * settings:
226 *
227 * strict: accept binaries that request a NaN encoding supported by the FPU
228 * legacy: only accept legacy-NaN binaries
229 * 2008: only accept 2008-NaN binaries
230 * relaxed: accept any binaries regardless of whether supported by the FPU
231 */
232static int __init ieee754_setup(char *s)
233{
234 if (!s)
235 return -1;
236 else if (!strcmp(s, "strict"))
237 ieee754 = STRICT;
238 else if (!strcmp(s, "legacy"))
239 ieee754 = LEGACY;
240 else if (!strcmp(s, "2008"))
241 ieee754 = STD2008;
242 else if (!strcmp(s, "relaxed"))
243 ieee754 = RELAXED;
244 else
245 return -1;
246
247 if (!(boot_cpu_data.options & MIPS_CPU_FPU))
248 cpu_set_nofpu_2008(&boot_cpu_data);
249 cpu_set_nan_2008(&boot_cpu_data);
250
251 return 0;
252}
253
254early_param("ieee754", ieee754_setup);
255
f6843626
MR		 256/*
257 * Set the FIR feature flags for the FPU emulator.
258 */
259static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
260{
261 u32 value;
262
263 value = 0;
264 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
265 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
266 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
267 value |= MIPS_FPIR_D | MIPS_FPIR_S;
268 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
269 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
270 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
90d53a91
MR		 271 if (c->options & MIPS_CPU_NAN_2008)
272 value |= MIPS_FPIR_HAS2008;
f6843626
MR		 273 c->fpu_id = value;
274}
275
9b26616c
MR		 276/* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
277static unsigned int mips_nofpu_msk31;
278
7aecd5ca
MR		 279/*
280 * Set options for FPU hardware.
281 */
282static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
283{
284 c->fpu_id = cpu_get_fpu_id();
285 mips_nofpu_msk31 = c->fpu_msk31;
286
287 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
288 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
289 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
290 if (c->fpu_id & MIPS_FPIR_3D)
291 c->ases |= MIPS_ASE_MIPS3D;
292 if (c->fpu_id & MIPS_FPIR_FREP)
293 c->options |= MIPS_CPU_FRE;
294 }
295
296 cpu_set_fpu_fcsr_mask(c);
93adeaf6 297 cpu_set_fpu_2008(c);
503943e0 298 cpu_set_nan_2008(c);
7aecd5ca
MR		 299}
300
301/*
302 * Set options for the FPU emulator.
303 */
304static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
305{
306 c->options &= ~MIPS_CPU_FPU;
307 c->fpu_msk31 = mips_nofpu_msk31;
308
93adeaf6 309 cpu_set_nofpu_2008(c);
503943e0 310 cpu_set_nan_2008(c);
7aecd5ca
MR		 311 cpu_set_nofpu_id(c);
312}
313
078a55fc 314static int mips_fpu_disabled;
0103d23f
KC		 315
316static int __init fpu_disable(char *s)
317{
7aecd5ca 318 cpu_set_nofpu_opts(&boot_cpu_data);
0103d23f
KC		 319 mips_fpu_disabled = 1;
320
321 return 1;
322}
323
324__setup("nofpu", fpu_disable);
325
078a55fc 326int mips_dsp_disabled;
0103d23f
KC		 327
328static int __init dsp_disable(char *s)
329{
ee80f7c7 330 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f
KC		 331 mips_dsp_disabled = 1;
332
333 return 1;
334}
335
336__setup("nodsp", dsp_disable);
337
3d528b32
MC		 338static int mips_htw_disabled;
339
340static int __init htw_disable(char *s)
341{
342 mips_htw_disabled = 1;
343 cpu_data[0].options &= ~MIPS_CPU_HTW;
344 write_c0_pwctl(read_c0_pwctl() &
345 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
346
347 return 1;
348}
349
350__setup("nohtw", htw_disable);
351
97f4ad29
MC		 352static int mips_ftlb_disabled;
353static int mips_has_ftlb_configured;
354
912708c2 355static int set_ftlb_enable(struct cpuinfo_mips *c, int enable);
97f4ad29
MC		 356
357static int __init ftlb_disable(char *s)
358{
359 unsigned int config4, mmuextdef;
360
361 /*
362 * If the core hasn't done any FTLB configuration, there is nothing
363 * for us to do here.
364 */
365 if (!mips_has_ftlb_configured)
366 return 1;
367
368 /* Disable it in the boot cpu */
912708c2
MC		 369 if (set_ftlb_enable(&cpu_data[0], 0)) {
370 pr_warn("Can't turn FTLB off\n");
371 return 1;
372 }
97f4ad29
MC		 373
374 back_to_back_c0_hazard();
375
376 config4 = read_c0_config4();
377
378 /* Check that FTLB has been disabled */
379 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
380 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
381 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
382 /* This should never happen */
383 pr_warn("FTLB could not be disabled!\n");
384 return 1;
385 }
386
387 mips_ftlb_disabled = 1;
388 mips_has_ftlb_configured = 0;
389
390 /*
391 * noftlb is mainly used for debug purposes so print
392 * an informative message instead of using pr_debug()
393 */
394 pr_info("FTLB has been disabled\n");
395
396 /*
397 * Some of these bits are duplicated in the decode_config4.
398 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
399 * once FTLB has been disabled so undo what decode_config4 did.
400 */
401 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
402 cpu_data[0].tlbsizeftlbsets;
403 cpu_data[0].tlbsizeftlbsets = 0;
404 cpu_data[0].tlbsizeftlbways = 0;
405
406 return 1;
407}
408
409__setup("noftlb", ftlb_disable);
410
411
9267a30d
MSJ		 412static inline void check_errata(void)
413{
414 struct cpuinfo_mips *c = &current_cpu_data;
415
69f24d17 416 switch (current_cpu_type()) {
9267a30d
MSJ		 417 case CPU_34K:
418 /*
419 * Erratum "RPS May Cause Incorrect Instruction Execution"
b633648c 420 * This code only handles VPE0, any SMP/RTOS code
9267a30d
MSJ		 421 * making use of VPE1 will be responsable for that VPE.
422 */
423 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
424 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
425 break;
426 default:
427 break;
428 }
429}
430
1da177e4
LT		 431void __init check_bugs32(void)
432{
9267a30d 433 check_errata();
1da177e4
LT		 434}
435
436/*
437 * Probe whether cpu has config register by trying to play with
438 * alternate cache bit and see whether it matters.
439 * It's used by cpu_probe to distinguish between R3000A and R3081.
440 */
441static inline int cpu_has_confreg(void)
442{
443#ifdef CONFIG_CPU_R3000
444 extern unsigned long r3k_cache_size(unsigned long);
445 unsigned long size1, size2;
446 unsigned long cfg = read_c0_conf();
447
448 size1 = r3k_cache_size(ST0_ISC);
449 write_c0_conf(cfg ^ R30XX_CONF_AC);
450 size2 = r3k_cache_size(ST0_ISC);
451 write_c0_conf(cfg);
452 return size1 != size2;
453#else
454 return 0;
455#endif
456}
457
c094c99e
RM		 458static inline void set_elf_platform(int cpu, const char *plat)
459{
460 if (cpu == 0)
461 __elf_platform = plat;
462}
463
91dfc423
GR		 464static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
465{
466#ifdef __NEED_VMBITS_PROBE
5b7efa89 467 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 468 back_to_back_c0_hazard();
5b7efa89 469 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 470#endif
471}
472
078a55fc 473static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
a96102be
SH		 474{
475 switch (isa) {
476 case MIPS_CPU_ISA_M64R2:
477 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
478 case MIPS_CPU_ISA_M64R1:
479 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
480 case MIPS_CPU_ISA_V:
481 c->isa_level |= MIPS_CPU_ISA_V;
482 case MIPS_CPU_ISA_IV:
483 c->isa_level |= MIPS_CPU_ISA_IV;
484 case MIPS_CPU_ISA_III:
1990e542 485 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
a96102be
SH		 486 break;
487
8b8aa636
LY		 488 /* R6 incompatible with everything else */
489 case MIPS_CPU_ISA_M64R6:
490 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
491 case MIPS_CPU_ISA_M32R6:
492 c->isa_level |= MIPS_CPU_ISA_M32R6;
493 /* Break here so we don't add incompatible ISAs */
494 break;
a96102be
SH		 495 case MIPS_CPU_ISA_M32R2:
496 c->isa_level |= MIPS_CPU_ISA_M32R2;
497 case MIPS_CPU_ISA_M32R1:
498 c->isa_level |= MIPS_CPU_ISA_M32R1;
499 case MIPS_CPU_ISA_II:
500 c->isa_level |= MIPS_CPU_ISA_II;
a96102be
SH		 501 break;
502 }
503}
504
078a55fc 505static char unknown_isa[] = KERN_ERR \
2fa36399
KC		 506 "Unsupported ISA type, c0.config0: %d.";
507
cf0a8aa0
MC		 508static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
509{
510
511 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
512
513 /*
514 * 0 = All TLBWR instructions go to FTLB
515 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
516 * FTLB and 1 goes to the VTLB.
517 * 2 = 7:1: As above with 7:1 ratio.
518 * 3 = 3:1: As above with 3:1 ratio.
519 *
520 * Use the linear midpoint as the probability threshold.
521 */
522 if (probability >= 12)
523 return 1;
524 else if (probability >= 6)
525 return 2;
526 else
527 /*
528 * So FTLB is less than 4 times bigger than VTLB.
529 * A 3:1 ratio can still be useful though.
530 */
531 return 3;
532}
533
912708c2 534static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
75b5b5e0 535{
20a7f7e5 536 unsigned int config;
d83b0e82
JH		 537
538 /* It's implementation dependent how the FTLB can be enabled */
539 switch (c->cputype) {
540 case CPU_PROAPTIV:
541 case CPU_P5600:
1091bfa2 542 case CPU_P6600:
d83b0e82 543 /* proAptiv & related cores use Config6 to enable the FTLB */
20a7f7e5 544 config = read_c0_config6();
cf0a8aa0 545 /* Clear the old probability value */
20a7f7e5 546 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
75b5b5e0
LY		 547 if (enable)
548 /* Enable FTLB */
20a7f7e5 549 write_c0_config6(config |
cf0a8aa0
MC		 550 (calculate_ftlb_probability(c)
551 << MIPS_CONF6_FTLBP_SHIFT)
552 | MIPS_CONF6_FTLBEN);
75b5b5e0
LY		 553 else
554 /* Disable FTLB */
20a7f7e5
MC		 555 write_c0_config6(config & ~MIPS_CONF6_FTLBEN);
556 break;
557 case CPU_I6400:
558 /* I6400 & related cores use Config7 to configure FTLB */
559 config = read_c0_config7();
560 /* Clear the old probability value */
561 config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT);
562 write_c0_config7(config | (calculate_ftlb_probability(c)
563 << MIPS_CONF7_FTLBP_SHIFT));
d83b0e82 564 break;
b2edcfc8
HC		 565 case CPU_LOONGSON3:
566 /* Loongson-3 cores use Config6 to enable the FTLB */
567 config = read_c0_config6();
568 if (enable)
569 /* Enable FTLB */
570 write_c0_config6(config & ~MIPS_CONF6_FTLBDIS);
571 else
572 /* Disable FTLB */
573 write_c0_config6(config | MIPS_CONF6_FTLBDIS);
574 break;
912708c2
MC		 575 default:
576 return 1;
75b5b5e0 577 }
912708c2
MC		 578
579 return 0;
75b5b5e0
LY		 580}
581
2fa36399
KC		 582static inline unsigned int decode_config0(struct cpuinfo_mips *c)
583{
584 unsigned int config0;
2f6f3136 585 int isa, mt;
2fa36399
KC		 586
587 config0 = read_c0_config();
588
75b5b5e0
LY		 589 /*
590 * Look for Standard TLB or Dual VTLB and FTLB
591 */
2f6f3136
JH		 592 mt = config0 & MIPS_CONF_MT;
593 if (mt == MIPS_CONF_MT_TLB)
2fa36399 594 c->options |= MIPS_CPU_TLB;
2f6f3136
JH		 595 else if (mt == MIPS_CONF_MT_FTLB)
596 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
75b5b5e0 597
2fa36399
KC		 598 isa = (config0 & MIPS_CONF_AT) >> 13;
599 switch (isa) {
600 case 0:
601 switch ((config0 & MIPS_CONF_AR) >> 10) {
602 case 0:
a96102be 603 set_isa(c, MIPS_CPU_ISA_M32R1);
2fa36399
KC		 604 break;
605 case 1:
a96102be 606 set_isa(c, MIPS_CPU_ISA_M32R2);
2fa36399 607 break;
8b8aa636
LY		 608 case 2:
609 set_isa(c, MIPS_CPU_ISA_M32R6);
610 break;
2fa36399
KC		 611 default:
612 goto unknown;
613 }
614 break;
615 case 2:
616 switch ((config0 & MIPS_CONF_AR) >> 10) {
617 case 0:
a96102be 618 set_isa(c, MIPS_CPU_ISA_M64R1);
2fa36399
KC		 619 break;
620 case 1:
a96102be 621 set_isa(c, MIPS_CPU_ISA_M64R2);
2fa36399 622 break;
8b8aa636
LY		 623 case 2:
624 set_isa(c, MIPS_CPU_ISA_M64R6);
625 break;
2fa36399
KC		 626 default:
627 goto unknown;
628 }
629 break;
630 default:
631 goto unknown;
632 }
633
634 return config0 & MIPS_CONF_M;
635
636unknown:
637 panic(unknown_isa, config0);
638}
639
640static inline unsigned int decode_config1(struct cpuinfo_mips *c)
641{
642 unsigned int config1;
643
644 config1 = read_c0_config1();
645
646 if (config1 & MIPS_CONF1_MD)
647 c->ases |= MIPS_ASE_MDMX;
648 if (config1 & MIPS_CONF1_WR)
649 c->options |= MIPS_CPU_WATCH;
650 if (config1 & MIPS_CONF1_CA)
651 c->ases |= MIPS_ASE_MIPS16;
652 if (config1 & MIPS_CONF1_EP)
653 c->options |= MIPS_CPU_EJTAG;
654 if (config1 & MIPS_CONF1_FP) {
655 c->options |= MIPS_CPU_FPU;
656 c->options |= MIPS_CPU_32FPR;
657 }
75b5b5e0 658 if (cpu_has_tlb) {
2fa36399 659 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
75b5b5e0
LY		 660 c->tlbsizevtlb = c->tlbsize;
661 c->tlbsizeftlbsets = 0;
662 }
2fa36399
KC		 663
664 return config1 & MIPS_CONF_M;
665}
666
667static inline unsigned int decode_config2(struct cpuinfo_mips *c)
668{
669 unsigned int config2;
670
671 config2 = read_c0_config2();
672
673 if (config2 & MIPS_CONF2_SL)
674 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
675
676 return config2 & MIPS_CONF_M;
677}
678
679static inline unsigned int decode_config3(struct cpuinfo_mips *c)
680{
681 unsigned int config3;
682
683 config3 = read_c0_config3();
684
b2ab4f08 685 if (config3 & MIPS_CONF3_SM) {
2fa36399 686 c->ases |= MIPS_ASE_SMARTMIPS;
b2ab4f08
SH		 687 c->options |= MIPS_CPU_RIXI;
688 }
689 if (config3 & MIPS_CONF3_RXI)
690 c->options |= MIPS_CPU_RIXI;
2fa36399
KC		 691 if (config3 & MIPS_CONF3_DSP)
692 c->ases |= MIPS_ASE_DSP;
b5a6455c 693 if (config3 & MIPS_CONF3_DSP2P) {
ee80f7c7 694 c->ases |= MIPS_ASE_DSP2P;
b5a6455c
ZLK		 695 if (cpu_has_mips_r6)
696 c->ases |= MIPS_ASE_DSP3;
697 }
2fa36399
KC		 698 if (config3 & MIPS_CONF3_VINT)
699 c->options |= MIPS_CPU_VINT;
700 if (config3 & MIPS_CONF3_VEIC)
701 c->options |= MIPS_CPU_VEIC;
702 if (config3 & MIPS_CONF3_MT)
703 c->ases |= MIPS_ASE_MIPSMT;
704 if (config3 & MIPS_CONF3_ULRI)
705 c->options |= MIPS_CPU_ULRI;
f8fa4811
SH		 706 if (config3 & MIPS_CONF3_ISA)
707 c->options |= MIPS_CPU_MICROMIPS;
1e7decdb
DD		 708 if (config3 & MIPS_CONF3_VZ)
709 c->ases |= MIPS_ASE_VZ;
4a0156fb
SH		 710 if (config3 & MIPS_CONF3_SC)
711 c->options |= MIPS_CPU_SEGMENTS;
a5e9a69e
PB		 712 if (config3 & MIPS_CONF3_MSA)
713 c->ases |= MIPS_ASE_MSA;
cab25bc7 714 if (config3 & MIPS_CONF3_PW) {
ed4cbc81 715 c->htw_seq = 0;
3d528b32 716 c->options |= MIPS_CPU_HTW;
ed4cbc81 717 }
9b3274bd
JH		 718 if (config3 & MIPS_CONF3_CDMM)
719 c->options |= MIPS_CPU_CDMM;
aaa7be48
JH		 720 if (config3 & MIPS_CONF3_SP)
721 c->options |= MIPS_CPU_SP;
2fa36399
KC		 722
723 return config3 & MIPS_CONF_M;
724}
725
726static inline unsigned int decode_config4(struct cpuinfo_mips *c)
727{
728 unsigned int config4;
75b5b5e0
LY		 729 unsigned int newcf4;
730 unsigned int mmuextdef;
731 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
2fa36399
KC		 732
733 config4 = read_c0_config4();
734
1745c1ef
LY		 735 if (cpu_has_tlb) {
736 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
737 c->options |= MIPS_CPU_TLBINV;
43d104db 738
e87569cd 739 /*
43d104db
JH		 740 * R6 has dropped the MMUExtDef field from config4.
741 * On R6 the fields always describe the FTLB, and only if it is
742 * present according to Config.MT.
e87569cd 743 */
43d104db
JH		 744 if (!cpu_has_mips_r6)
745 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
746 else if (cpu_has_ftlb)
e87569cd
MC		 747 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
748 else
43d104db 749 mmuextdef = 0;
e87569cd 750
75b5b5e0
LY		 751 switch (mmuextdef) {
752 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
753 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
754 c->tlbsizevtlb = c->tlbsize;
755 break;
756 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
757 c->tlbsizevtlb +=
758 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
759 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
760 c->tlbsize = c->tlbsizevtlb;
761 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
762 /* fall through */
763 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
97f4ad29
MC		 764 if (mips_ftlb_disabled)
765 break;
75b5b5e0
LY		 766 newcf4 = (config4 & ~ftlb_page) |
767 (page_size_ftlb(mmuextdef) <<
768 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
769 write_c0_config4(newcf4);
770 back_to_back_c0_hazard();
771 config4 = read_c0_config4();
772 if (config4 != newcf4) {
773 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
774 PAGE_SIZE, config4);
775 /* Switch FTLB off */
776 set_ftlb_enable(c, 0);
777 break;
778 }
779 c->tlbsizeftlbsets = 1 <<
780 ((config4 & MIPS_CONF4_FTLBSETS) >>
781 MIPS_CONF4_FTLBSETS_SHIFT);
782 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
783 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
784 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
97f4ad29 785 mips_has_ftlb_configured = 1;
75b5b5e0
LY		 786 break;
787 }
1745c1ef
LY		 788 }
789
2fa36399
KC		 790 c->kscratch_mask = (config4 >> 16) & 0xff;
791
792 return config4 & MIPS_CONF_M;
793}
794
8b8a7634
RB		 795static inline unsigned int decode_config5(struct cpuinfo_mips *c)
796{
797 unsigned int config5;
798
799 config5 = read_c0_config5();
d175ed2b 800 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
8b8a7634
RB		 801 write_c0_config5(config5);
802
49016748
MC		 803 if (config5 & MIPS_CONF5_EVA)
804 c->options |= MIPS_CPU_EVA;
1f6c52ff
PB		 805 if (config5 & MIPS_CONF5_MRP)
806 c->options |= MIPS_CPU_MAAR;
5aed9da1
MC		 807 if (config5 & MIPS_CONF5_LLB)
808 c->options |= MIPS_CPU_RW_LLB;
c5b36783
SH		 809#ifdef CONFIG_XPA
810 if (config5 & MIPS_CONF5_MVH)
811 c->options |= MIPS_CPU_XPA;
812#endif
f270d881
PB		 813 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
814 c->options |= MIPS_CPU_VP;
49016748 815
8b8a7634
RB		 816 return config5 & MIPS_CONF_M;
817}
818
078a55fc 819static void decode_configs(struct cpuinfo_mips *c)
2fa36399
KC		 820{
821 int ok;
822
823 /* MIPS32 or MIPS64 compliant CPU. */
824 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
825 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
826
827 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
828
97f4ad29
MC		 829 /* Enable FTLB if present and not disabled */
830 set_ftlb_enable(c, !mips_ftlb_disabled);
75b5b5e0 831
2fa36399 832 ok = decode_config0(c); /* Read Config registers. */
70342287 833 BUG_ON(!ok); /* Arch spec violation! */
2fa36399
KC		 834 if (ok)
835 ok = decode_config1(c);
836 if (ok)
837 ok = decode_config2(c);
838 if (ok)
839 ok = decode_config3(c);
840 if (ok)
841 ok = decode_config4(c);
8b8a7634
RB		 842 if (ok)
843 ok = decode_config5(c);
2fa36399
KC		 844
845 mips_probe_watch_registers(c);
846
6575b1d4
LY		 847 if (cpu_has_rixi) {
848 /* Enable the RIXI exceptions */
a5770df0 849 set_c0_pagegrain(PG_IEC);
6575b1d4
LY		 850 back_to_back_c0_hazard();
851 /* Verify the IEC bit is set */
852 if (read_c0_pagegrain() & PG_IEC)
853 c->options |= MIPS_CPU_RIXIEX;
854 }
855
0ee958e1 856#ifndef CONFIG_MIPS_CPS
8b8aa636 857 if (cpu_has_mips_r2_r6) {
45b585c8 858 c->core = get_ebase_cpunum();
30ee615b
PB		 859 if (cpu_has_mipsmt)
860 c->core >>= fls(core_nvpes()) - 1;
861 }
0ee958e1 862#endif
2fa36399
KC		 863}
864
02cf2119 865#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 866 | MIPS_CPU_COUNTER)
867
cea7e2df 868static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 869{
8ff374b9 870 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 871 case PRID_IMP_R2000:
872 c->cputype = CPU_R2000;
cea7e2df 873 __cpu_name[cpu] = "R2000";
9b26616c 874 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 875 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 876 MIPS_CPU_NOFPUEX;
1da177e4
LT		 877 if (__cpu_has_fpu())
878 c->options |= MIPS_CPU_FPU;
879 c->tlbsize = 64;
880 break;
881 case PRID_IMP_R3000:
8ff374b9 882 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
cea7e2df 883 if (cpu_has_confreg()) {
1da177e4 884 c->cputype = CPU_R3081E;
cea7e2df
RB		 885 __cpu_name[cpu] = "R3081";
886 } else {
1da177e4 887 c->cputype = CPU_R3000A;
cea7e2df
RB		 888 __cpu_name[cpu] = "R3000A";
889 }
cea7e2df 890 } else {
1da177e4 891 c->cputype = CPU_R3000;
cea7e2df
RB		 892 __cpu_name[cpu] = "R3000";
893 }
9b26616c 894 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 895 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 896 MIPS_CPU_NOFPUEX;
1da177e4
LT		 897 if (__cpu_has_fpu())
898 c->options |= MIPS_CPU_FPU;
899 c->tlbsize = 64;
900 break;
901 case PRID_IMP_R4000:
902 if (read_c0_config() & CONF_SC) {
8ff374b9
MR		 903 if ((c->processor_id & PRID_REV_MASK) >=
904 PRID_REV_R4400) {
1da177e4 905 c->cputype = CPU_R4400PC;
cea7e2df
RB		 906 __cpu_name[cpu] = "R4400PC";
907 } else {
1da177e4 908 c->cputype = CPU_R4000PC;
cea7e2df
RB		 909 __cpu_name[cpu] = "R4000PC";
910 }
1da177e4 911 } else {
7f177a52
MR		 912 int cca = read_c0_config() & CONF_CM_CMASK;
913 int mc;
914
915 /*
916 * SC and MC versions can't be reliably told apart,
917 * but only the latter support coherent caching
918 * modes so assume the firmware has set the KSEG0
919 * coherency attribute reasonably (if uncached, we
920 * assume SC).
921 */
922 switch (cca) {
923 case CONF_CM_CACHABLE_CE:
924 case CONF_CM_CACHABLE_COW:
925 case CONF_CM_CACHABLE_CUW:
926 mc = 1;
927 break;
928 default:
929 mc = 0;
930 break;
931 }
8ff374b9
MR		 932 if ((c->processor_id & PRID_REV_MASK) >=
933 PRID_REV_R4400) {
7f177a52
MR		 934 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
935 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
cea7e2df 936 } else {
7f177a52
MR		 937 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
938 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
cea7e2df 939 }
1da177e4
LT		 940 }
941
a96102be 942 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 943 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 944 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 945 MIPS_CPU_WATCH | MIPS_CPU_VCE |
946 MIPS_CPU_LLSC;
1da177e4
LT		 947 c->tlbsize = 48;
948 break;
949 case PRID_IMP_VR41XX:
9f91e506 950 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 951 c->fpu_msk31 |= FPU_CSR_CONDX;
9f91e506
YY		 952 c->options = R4K_OPTS;
953 c->tlbsize = 32;
1da177e4 954 switch (c->processor_id & 0xf0) {
1da177e4
LT		 955 case PRID_REV_VR4111:
956 c->cputype = CPU_VR4111;
cea7e2df 957 __cpu_name[cpu] = "NEC VR4111";
1da177e4 958 break;
1da177e4
LT		 959 case PRID_REV_VR4121:
960 c->cputype = CPU_VR4121;
cea7e2df 961 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 962 break;
963 case PRID_REV_VR4122:
cea7e2df 964 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 965 c->cputype = CPU_VR4122;
cea7e2df
RB		 966 __cpu_name[cpu] = "NEC VR4122";
967 } else {
1da177e4 968 c->cputype = CPU_VR4181A;
cea7e2df
RB		 969 __cpu_name[cpu] = "NEC VR4181A";
970 }
1da177e4
LT		 971 break;
972 case PRID_REV_VR4130:
cea7e2df 973 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 974 c->cputype = CPU_VR4131;
cea7e2df
RB		 975 __cpu_name[cpu] = "NEC VR4131";
976 } else {
1da177e4 977 c->cputype = CPU_VR4133;
9f91e506 978 c->options |= MIPS_CPU_LLSC;
cea7e2df
RB		 979 __cpu_name[cpu] = "NEC VR4133";
980 }
1da177e4
LT		 981 break;
982 default:
983 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
984 c->cputype = CPU_VR41XX;
cea7e2df 985 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 986 break;
987 }
1da177e4
LT		 988 break;
989 case PRID_IMP_R4300:
990 c->cputype = CPU_R4300;
cea7e2df 991 __cpu_name[cpu] = "R4300";
a96102be 992 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 993 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 994 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 995 MIPS_CPU_LLSC;
1da177e4
LT		 996 c->tlbsize = 32;
997 break;
998 case PRID_IMP_R4600:
999 c->cputype = CPU_R4600;
cea7e2df 1000 __cpu_name[cpu] = "R4600";
a96102be 1001 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1002 c->fpu_msk31 |= FPU_CSR_CONDX;
075e7502
TS		 1003 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1004 MIPS_CPU_LLSC;
1da177e4
LT		 1005 c->tlbsize = 48;
1006 break;
1007 #if 0
03751e79 1008 case PRID_IMP_R4650:
1da177e4
LT		 1009 /*
1010 * This processor doesn't have an MMU, so it's not
1011 * "real easy" to run Linux on it. It is left purely
1012 * for documentation. Commented out because it shares
1013 * it's c0_prid id number with the TX3900.
1014 */
a3dddd56 1015 c->cputype = CPU_R4650;
cea7e2df 1016 __cpu_name[cpu] = "R4650";
a96102be 1017 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1018 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 1019 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 1020 c->tlbsize = 48;
1da177e4
LT		 1021 break;
1022 #endif
1023 case PRID_IMP_TX39:
9b26616c 1024 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 1025 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 1026
1027 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1028 c->cputype = CPU_TX3927;
cea7e2df 1029 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 1030 c->tlbsize = 64;
1031 } else {
8ff374b9 1032 switch (c->processor_id & PRID_REV_MASK) {
1da177e4
LT		 1033 case PRID_REV_TX3912:
1034 c->cputype = CPU_TX3912;
cea7e2df 1035 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 1036 c->tlbsize = 32;
1037 break;
1038 case PRID_REV_TX3922:
1039 c->cputype = CPU_TX3922;
cea7e2df 1040 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 1041 c->tlbsize = 64;
1042 break;
1da177e4
LT		 1043 }
1044 }
1045 break;
1046 case PRID_IMP_R4700:
1047 c->cputype = CPU_R4700;
cea7e2df 1048 __cpu_name[cpu] = "R4700";
a96102be 1049 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1050 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 1051 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1052 MIPS_CPU_LLSC;
1da177e4
LT		 1053 c->tlbsize = 48;
1054 break;
1055 case PRID_IMP_TX49:
1056 c->cputype = CPU_TX49XX;
cea7e2df 1057 __cpu_name[cpu] = "R49XX";
a96102be 1058 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1059 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4
LT		 1060 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1061 if (!(c->processor_id & 0x08))
1062 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1063 c->tlbsize = 48;
1064 break;
1065 case PRID_IMP_R5000:
1066 c->cputype = CPU_R5000;
cea7e2df 1067 __cpu_name[cpu] = "R5000";
a96102be 1068 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1069 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1070 MIPS_CPU_LLSC;
1da177e4
LT		 1071 c->tlbsize = 48;
1072 break;
1073 case PRID_IMP_R5432:
1074 c->cputype = CPU_R5432;
cea7e2df 1075 __cpu_name[cpu] = "R5432";
a96102be 1076 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1077 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1078 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 1079 c->tlbsize = 48;
1080 break;
1081 case PRID_IMP_R5500:
1082 c->cputype = CPU_R5500;
cea7e2df 1083 __cpu_name[cpu] = "R5500";
a96102be 1084 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1085 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1086 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 1087 c->tlbsize = 48;
1088 break;
1089 case PRID_IMP_NEVADA:
1090 c->cputype = CPU_NEVADA;
cea7e2df 1091 __cpu_name[cpu] = "Nevada";
a96102be 1092 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1093 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1094 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 1095 c->tlbsize = 48;
1096 break;
1097 case PRID_IMP_R6000:
1098 c->cputype = CPU_R6000;
cea7e2df 1099 __cpu_name[cpu] = "R6000";
a96102be 1100 set_isa(c, MIPS_CPU_ISA_II);
9b26616c 1101 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1da177e4 1102 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 1103 MIPS_CPU_LLSC;
1da177e4
LT		 1104 c->tlbsize = 32;
1105 break;
1106 case PRID_IMP_R6000A:
1107 c->cputype = CPU_R6000A;
cea7e2df 1108 __cpu_name[cpu] = "R6000A";
a96102be 1109 set_isa(c, MIPS_CPU_ISA_II);
9b26616c 1110 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1da177e4 1111 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 1112 MIPS_CPU_LLSC;
1da177e4
LT		 1113 c->tlbsize = 32;
1114 break;
1115 case PRID_IMP_RM7000:
1116 c->cputype = CPU_RM7000;
cea7e2df 1117 __cpu_name[cpu] = "RM7000";
a96102be 1118 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1119 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1120 MIPS_CPU_LLSC;
1da177e4 1121 /*
70342287 1122 * Undocumented RM7000: Bit 29 in the info register of
1da177e4
LT		 1123 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1124 * entries.
1125 *
70342287
RB		 1126 * 29 1 => 64 entry JTLB
1127 * 0 => 48 entry JTLB
1da177e4
LT		 1128 */
1129 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1da177e4
LT		 1130 break;
1131 case PRID_IMP_R8000:
1132 c->cputype = CPU_R8000;
cea7e2df 1133 __cpu_name[cpu] = "RM8000";
a96102be 1134 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1135 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 1136 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1137 MIPS_CPU_LLSC;
1da177e4
LT		 1138 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
1139 break;
1140 case PRID_IMP_R10000:
1141 c->cputype = CPU_R10000;
cea7e2df 1142 __cpu_name[cpu] = "R10000";
a96102be 1143 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 1144 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 1145 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 1146 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 1147 MIPS_CPU_LLSC;
1da177e4
LT		 1148 c->tlbsize = 64;
1149 break;
1150 case PRID_IMP_R12000:
1151 c->cputype = CPU_R12000;
cea7e2df 1152 __cpu_name[cpu] = "R12000";
a96102be 1153 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 1154 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 1155 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 1156 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
8d5ded16 1157 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1da177e4
LT		 1158 c->tlbsize = 64;
1159 break;
44d921b2 1160 case PRID_IMP_R14000:
30577391
JK		 1161 if (((c->processor_id >> 4) & 0x0f) > 2) {
1162 c->cputype = CPU_R16000;
1163 __cpu_name[cpu] = "R16000";
1164 } else {
1165 c->cputype = CPU_R14000;
1166 __cpu_name[cpu] = "R14000";
1167 }
a96102be 1168 set_isa(c, MIPS_CPU_ISA_IV);
44d921b2 1169 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 1170 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 1171 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
8d5ded16 1172 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
44d921b2
K		 1173 c->tlbsize = 64;
1174 break;
26859198 1175 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
5aac1e8a
RM		 1176 switch (c->processor_id & PRID_REV_MASK) {
1177 case PRID_REV_LOONGSON2E:
c579d310
HC		 1178 c->cputype = CPU_LOONGSON2;
1179 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 1180 set_elf_platform(cpu, "loongson2e");
7352c8b1 1181 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1182 c->fpu_msk31 |= FPU_CSR_CONDX;
5aac1e8a
RM		 1183 break;
1184 case PRID_REV_LOONGSON2F:
c579d310
HC		 1185 c->cputype = CPU_LOONGSON2;
1186 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 1187 set_elf_platform(cpu, "loongson2f");
7352c8b1 1188 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1189 c->fpu_msk31 |= FPU_CSR_CONDX;
5aac1e8a 1190 break;
b2edcfc8 1191 case PRID_REV_LOONGSON3A_R1:
c579d310
HC		 1192 c->cputype = CPU_LOONGSON3;
1193 __cpu_name[cpu] = "ICT Loongson-3";
1194 set_elf_platform(cpu, "loongson3a");
7352c8b1 1195 set_isa(c, MIPS_CPU_ISA_M64R1);
c579d310 1196 break;
e7841be5
HC		 1197 case PRID_REV_LOONGSON3B_R1:
1198 case PRID_REV_LOONGSON3B_R2:
1199 c->cputype = CPU_LOONGSON3;
1200 __cpu_name[cpu] = "ICT Loongson-3";
1201 set_elf_platform(cpu, "loongson3b");
7352c8b1 1202 set_isa(c, MIPS_CPU_ISA_M64R1);
e7841be5 1203 break;
5aac1e8a
RM		 1204 }
1205
2a21c730
FZ		 1206 c->options = R4K_OPTS |
1207 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1208 MIPS_CPU_32FPR;
1209 c->tlbsize = 64;
cc94ea31 1210 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2a21c730 1211 break;
26859198 1212 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
2fa36399 1213 decode_configs(c);
b4672d37 1214
2fa36399 1215 c->cputype = CPU_LOONGSON1;
1da177e4 1216
2fa36399
KC		 1217 switch (c->processor_id & PRID_REV_MASK) {
1218 case PRID_REV_LOONGSON1B:
1219 __cpu_name[cpu] = "Loongson 1B";
b4672d37 1220 break;
b4672d37 1221 }
4194318c 1222
2fa36399 1223 break;
1da177e4 1224 }
1da177e4
LT		 1225}
1226
cea7e2df 1227static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1228{
4f12b91d 1229 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 1230 switch (c->processor_id & PRID_IMP_MASK) {
b2498af5
LY		 1231 case PRID_IMP_QEMU_GENERIC:
1232 c->writecombine = _CACHE_UNCACHED;
1233 c->cputype = CPU_QEMU_GENERIC;
1234 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1235 break;
1da177e4
LT		 1236 case PRID_IMP_4KC:
1237 c->cputype = CPU_4KC;
4f12b91d 1238 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1239 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 1240 break;
1241 case PRID_IMP_4KEC:
2b07bd02
RB		 1242 case PRID_IMP_4KECR2:
1243 c->cputype = CPU_4KEC;
4f12b91d 1244 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1245 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 1246 break;
1da177e4 1247 case PRID_IMP_4KSC:
8afcb5d8 1248 case PRID_IMP_4KSD:
1da177e4 1249 c->cputype = CPU_4KSC;
4f12b91d 1250 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1251 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 1252 break;
1253 case PRID_IMP_5KC:
1254 c->cputype = CPU_5KC;
4f12b91d 1255 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1256 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4 1257 break;
78d4803f
LY		 1258 case PRID_IMP_5KE:
1259 c->cputype = CPU_5KE;
4f12b91d 1260 c->writecombine = _CACHE_UNCACHED;
78d4803f
LY		 1261 __cpu_name[cpu] = "MIPS 5KE";
1262 break;
1da177e4
LT		 1263 case PRID_IMP_20KC:
1264 c->cputype = CPU_20KC;
4f12b91d 1265 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1266 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 1267 break;
1268 case PRID_IMP_24K:
1269 c->cputype = CPU_24K;
4f12b91d 1270 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1271 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4 1272 break;
42f3caef
JC		 1273 case PRID_IMP_24KE:
1274 c->cputype = CPU_24K;
4f12b91d 1275 c->writecombine = _CACHE_UNCACHED;
42f3caef
JC		 1276 __cpu_name[cpu] = "MIPS 24KEc";
1277 break;
1da177e4
LT		 1278 case PRID_IMP_25KF:
1279 c->cputype = CPU_25KF;
4f12b91d 1280 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1281 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 1282 break;
bbc7f22f
RB		 1283 case PRID_IMP_34K:
1284 c->cputype = CPU_34K;
4f12b91d 1285 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1286 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 1287 break;
c620953c
CD		 1288 case PRID_IMP_74K:
1289 c->cputype = CPU_74K;
4f12b91d 1290 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1291 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 1292 break;
113c62d9
SH		 1293 case PRID_IMP_M14KC:
1294 c->cputype = CPU_M14KC;
4f12b91d 1295 c->writecombine = _CACHE_UNCACHED;
113c62d9
SH		 1296 __cpu_name[cpu] = "MIPS M14Kc";
1297 break;
f8fa4811
SH		 1298 case PRID_IMP_M14KEC:
1299 c->cputype = CPU_M14KEC;
4f12b91d 1300 c->writecombine = _CACHE_UNCACHED;
f8fa4811
SH		 1301 __cpu_name[cpu] = "MIPS M14KEc";
1302 break;
39b8d525
RB		 1303 case PRID_IMP_1004K:
1304 c->cputype = CPU_1004K;
4f12b91d 1305 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1306 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 1307 break;
006a851b 1308 case PRID_IMP_1074K:
442e14a2 1309 c->cputype = CPU_1074K;
4f12b91d 1310 c->writecombine = _CACHE_UNCACHED;
006a851b
SH		 1311 __cpu_name[cpu] = "MIPS 1074Kc";
1312 break;
b5f065e7
LY		 1313 case PRID_IMP_INTERAPTIV_UP:
1314 c->cputype = CPU_INTERAPTIV;
1315 __cpu_name[cpu] = "MIPS interAptiv";
1316 break;
1317 case PRID_IMP_INTERAPTIV_MP:
1318 c->cputype = CPU_INTERAPTIV;
1319 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1320 break;
b0d4d300
LY		 1321 case PRID_IMP_PROAPTIV_UP:
1322 c->cputype = CPU_PROAPTIV;
1323 __cpu_name[cpu] = "MIPS proAptiv";
1324 break;
1325 case PRID_IMP_PROAPTIV_MP:
1326 c->cputype = CPU_PROAPTIV;
1327 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1328 break;
829dcc0a
JH		 1329 case PRID_IMP_P5600:
1330 c->cputype = CPU_P5600;
1331 __cpu_name[cpu] = "MIPS P5600";
1332 break;
eba20a3a
PB		 1333 case PRID_IMP_P6600:
1334 c->cputype = CPU_P6600;
1335 __cpu_name[cpu] = "MIPS P6600";
1336 break;
e57f9a2d
MC		 1337 case PRID_IMP_I6400:
1338 c->cputype = CPU_I6400;
1339 __cpu_name[cpu] = "MIPS I6400";
1340 break;
9943ed92
LY		 1341 case PRID_IMP_M5150:
1342 c->cputype = CPU_M5150;
1343 __cpu_name[cpu] = "MIPS M5150";
1344 break;
43aff742
PB		 1345 case PRID_IMP_M6250:
1346 c->cputype = CPU_M6250;
1347 __cpu_name[cpu] = "MIPS M6250";
1348 break;
1da177e4 1349 }
0b6d497f 1350
75b5b5e0
LY		 1351 decode_configs(c);
1352
0b6d497f 1353 spram_config();
1da177e4
LT		 1354}
1355
cea7e2df 1356static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1357{
4194318c 1358 decode_configs(c);
8ff374b9 1359 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1360 case PRID_IMP_AU1_REV1:
1361 case PRID_IMP_AU1_REV2:
270717a8 1362 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 1363 switch ((c->processor_id >> 24) & 0xff) {
1364 case 0:
cea7e2df 1365 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 1366 break;
1367 case 1:
cea7e2df 1368 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 1369 break;
1370 case 2:
cea7e2df 1371 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 1372 break;
1373 case 3:
cea7e2df 1374 __cpu_name[cpu] = "Au1550";
1da177e4 1375 break;
e3ad1c23 1376 case 4:
cea7e2df 1377 __cpu_name[cpu] = "Au1200";
8ff374b9 1378 if ((c->processor_id & PRID_REV_MASK) == 2)
cea7e2df 1379 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 1380 break;
1381 case 5:
cea7e2df 1382 __cpu_name[cpu] = "Au1210";
e3ad1c23 1383 break;
1da177e4 1384 default:
270717a8 1385 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 1386 break;
1387 }
1da177e4
LT		 1388 break;
1389 }
1390}
1391
cea7e2df 1392static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1393{
4194318c 1394 decode_configs(c);
02cf2119 1395
4f12b91d 1396 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 1397 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1398 case PRID_IMP_SB1:
1399 c->cputype = CPU_SB1;
cea7e2df 1400 __cpu_name[cpu] = "SiByte SB1";
1da177e4 1401 /* FPU in pass1 is known to have issues. */
8ff374b9 1402 if ((c->processor_id & PRID_REV_MASK) < 0x02)
010b853b 1403 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 1404 break;
93ce2f52
AI		 1405 case PRID_IMP_SB1A:
1406 c->cputype = CPU_SB1A;
cea7e2df 1407 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 1408 break;
1da177e4
LT		 1409 }
1410}
1411
cea7e2df 1412static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1413{
4194318c 1414 decode_configs(c);
8ff374b9 1415 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1416 case PRID_IMP_SR71000:
1417 c->cputype = CPU_SR71000;
cea7e2df 1418 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 1419 c->scache.ways = 8;
1420 c->tlbsize = 64;
1421 break;
1422 }
1423}
1424
cea7e2df 1425static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 1426{
1427 decode_configs(c);
8ff374b9 1428 switch (c->processor_id & PRID_IMP_MASK) {
bdf21b18
PP		 1429 case PRID_IMP_PR4450:
1430 c->cputype = CPU_PR4450;
cea7e2df 1431 __cpu_name[cpu] = "Philips PR4450";
a96102be 1432 set_isa(c, MIPS_CPU_ISA_M32R1);
bdf21b18 1433 break;
bdf21b18
PP		 1434 }
1435}
1436
cea7e2df 1437static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 1438{
1439 decode_configs(c);
8ff374b9 1440 switch (c->processor_id & PRID_IMP_MASK) {
190fca3e
KC		 1441 case PRID_IMP_BMIPS32_REV4:
1442 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 1443 c->cputype = CPU_BMIPS32;
1444 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 1445 set_elf_platform(cpu, "bmips32");
602977b0
KC		 1446 break;
1447 case PRID_IMP_BMIPS3300:
1448 case PRID_IMP_BMIPS3300_ALT:
1449 case PRID_IMP_BMIPS3300_BUG:
1450 c->cputype = CPU_BMIPS3300;
1451 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 1452 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 1453 break;
1454 case PRID_IMP_BMIPS43XX: {
8ff374b9 1455 int rev = c->processor_id & PRID_REV_MASK;
602977b0
KC		 1456
1457 if (rev >= PRID_REV_BMIPS4380_LO &&
1458 rev <= PRID_REV_BMIPS4380_HI) {
1459 c->cputype = CPU_BMIPS4380;
1460 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 1461 set_elf_platform(cpu, "bmips4380");
602977b0
KC		 1462 } else {
1463 c->cputype = CPU_BMIPS4350;
1464 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 1465 set_elf_platform(cpu, "bmips4350");
602977b0 1466 }
0de663ef 1467 break;
602977b0
KC		 1468 }
1469 case PRID_IMP_BMIPS5000:
68e6a783 1470 case PRID_IMP_BMIPS5200:
602977b0 1471 c->cputype = CPU_BMIPS5000;
37808d62
FF		 1472 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1473 __cpu_name[cpu] = "Broadcom BMIPS5200";
1474 else
1475 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 1476 set_elf_platform(cpu, "bmips5000");
602977b0 1477 c->options |= MIPS_CPU_ULRI;
0de663ef 1478 break;
1c0c13eb
AJ		 1479 }
1480}
1481
0dd4781b
DD		 1482static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1483{
1484 decode_configs(c);
8ff374b9 1485 switch (c->processor_id & PRID_IMP_MASK) {
0dd4781b
DD		 1486 case PRID_IMP_CAVIUM_CN38XX:
1487 case PRID_IMP_CAVIUM_CN31XX:
1488 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 1489 c->cputype = CPU_CAVIUM_OCTEON;
1490 __cpu_name[cpu] = "Cavium Octeon";
1491 goto platform;
0dd4781b
DD		 1492 case PRID_IMP_CAVIUM_CN58XX:
1493 case PRID_IMP_CAVIUM_CN56XX:
1494 case PRID_IMP_CAVIUM_CN50XX:
1495 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 1496 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1497 __cpu_name[cpu] = "Cavium Octeon+";
1498platform:
c094c99e 1499 set_elf_platform(cpu, "octeon");
0dd4781b 1500 break;
a1431b61 1501 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 1502 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 1503 case PRID_IMP_CAVIUM_CN66XX:
1504 case PRID_IMP_CAVIUM_CN68XX:
af04bb85 1505 case PRID_IMP_CAVIUM_CNF71XX:
0e56b385
DD		 1506 c->cputype = CPU_CAVIUM_OCTEON2;
1507 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 1508 set_elf_platform(cpu, "octeon2");
0e56b385 1509 break;
af04bb85 1510 case PRID_IMP_CAVIUM_CN70XX:
b8c8f665
DD		 1511 case PRID_IMP_CAVIUM_CN73XX:
1512 case PRID_IMP_CAVIUM_CNF75XX:
af04bb85
DD		 1513 case PRID_IMP_CAVIUM_CN78XX:
1514 c->cputype = CPU_CAVIUM_OCTEON3;
1515 __cpu_name[cpu] = "Cavium Octeon III";
1516 set_elf_platform(cpu, "octeon3");
1517 break;
0dd4781b
DD		 1518 default:
1519 printk(KERN_INFO "Unknown Octeon chip!\n");
1520 c->cputype = CPU_UNKNOWN;
1521 break;
1522 }
1523}
1524
b2edcfc8
HC		 1525static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
1526{
1527 switch (c->processor_id & PRID_IMP_MASK) {
1528 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1529 switch (c->processor_id & PRID_REV_MASK) {
1530 case PRID_REV_LOONGSON3A_R2:
1531 c->cputype = CPU_LOONGSON3;
1532 __cpu_name[cpu] = "ICT Loongson-3";
1533 set_elf_platform(cpu, "loongson3a");
1534 set_isa(c, MIPS_CPU_ISA_M64R2);
1535 break;
1536 }
1537
1538 decode_configs(c);
1539 c->options |= MIPS_CPU_TLBINV;
1540 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1541 break;
1542 default:
1543 panic("Unknown Loongson Processor ID!");
1544 break;
1545 }
1546}
1547
83ccf69d
LPC		 1548static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1549{
1550 decode_configs(c);
1551 /* JZRISC does not implement the CP0 counter. */
1552 c->options &= ~MIPS_CPU_COUNTER;
06947aaa 1553 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
8ff374b9 1554 switch (c->processor_id & PRID_IMP_MASK) {
83ccf69d
LPC		 1555 case PRID_IMP_JZRISC:
1556 c->cputype = CPU_JZRISC;
4f12b91d 1557 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
83ccf69d
LPC		 1558 __cpu_name[cpu] = "Ingenic JZRISC";
1559 break;
1560 default:
1561 panic("Unknown Ingenic Processor ID!");
1562 break;
1563 }
1564}
1565
a7117c6b
J		 1566static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1567{
1568 decode_configs(c);
1569
8ff374b9 1570 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
809f36c6
ML		 1571 c->cputype = CPU_ALCHEMY;
1572 __cpu_name[cpu] = "Au1300";
1573 /* following stuff is not for Alchemy */
1574 return;
1575 }
1576
70342287
RB		 1577 c->options = (MIPS_CPU_TLB |
1578 MIPS_CPU_4KEX |
a7117c6b 1579 MIPS_CPU_COUNTER |
70342287
RB		 1580 MIPS_CPU_DIVEC |
1581 MIPS_CPU_WATCH |
1582 MIPS_CPU_EJTAG |
a7117c6b
J		 1583 MIPS_CPU_LLSC);
1584
8ff374b9 1585 switch (c->processor_id & PRID_IMP_MASK) {
4ca86a2f 1586 case PRID_IMP_NETLOGIC_XLP2XX:
8907c55e 1587 case PRID_IMP_NETLOGIC_XLP9XX:
1c983986 1588 case PRID_IMP_NETLOGIC_XLP5XX:
4ca86a2f
J		 1589 c->cputype = CPU_XLP;
1590 __cpu_name[cpu] = "Broadcom XLPII";
1591 break;
1592
2aa54b20
J		 1593 case PRID_IMP_NETLOGIC_XLP8XX:
1594 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 1595 c->cputype = CPU_XLP;
1596 __cpu_name[cpu] = "Netlogic XLP";
1597 break;
1598
a7117c6b
J		 1599 case PRID_IMP_NETLOGIC_XLR732:
1600 case PRID_IMP_NETLOGIC_XLR716:
1601 case PRID_IMP_NETLOGIC_XLR532:
1602 case PRID_IMP_NETLOGIC_XLR308:
1603 case PRID_IMP_NETLOGIC_XLR532C:
1604 case PRID_IMP_NETLOGIC_XLR516C:
1605 case PRID_IMP_NETLOGIC_XLR508C:
1606 case PRID_IMP_NETLOGIC_XLR308C:
1607 c->cputype = CPU_XLR;
1608 __cpu_name[cpu] = "Netlogic XLR";
1609 break;
1610
1611 case PRID_IMP_NETLOGIC_XLS608:
1612 case PRID_IMP_NETLOGIC_XLS408:
1613 case PRID_IMP_NETLOGIC_XLS404:
1614 case PRID_IMP_NETLOGIC_XLS208:
1615 case PRID_IMP_NETLOGIC_XLS204:
1616 case PRID_IMP_NETLOGIC_XLS108:
1617 case PRID_IMP_NETLOGIC_XLS104:
1618 case PRID_IMP_NETLOGIC_XLS616B:
1619 case PRID_IMP_NETLOGIC_XLS608B:
1620 case PRID_IMP_NETLOGIC_XLS416B:
1621 case PRID_IMP_NETLOGIC_XLS412B:
1622 case PRID_IMP_NETLOGIC_XLS408B:
1623 case PRID_IMP_NETLOGIC_XLS404B:
1624 c->cputype = CPU_XLR;
1625 __cpu_name[cpu] = "Netlogic XLS";
1626 break;
1627
1628 default:
a3d4fb2d 1629 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 1630 c->processor_id);
1631 c->cputype = CPU_XLR;
1632 break;
1633 }
1634
a3d4fb2d 1635 if (c->cputype == CPU_XLP) {
a96102be 1636 set_isa(c, MIPS_CPU_ISA_M64R2);
a3d4fb2d
J		 1637 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1638 /* This will be updated again after all threads are woken up */
1639 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1640 } else {
a96102be 1641 set_isa(c, MIPS_CPU_ISA_M64R1);
a3d4fb2d
J		 1642 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1643 }
7777b939 1644 c->kscratch_mask = 0xf;
a7117c6b
J		 1645}
1646
949e51be
DD		 1647#ifdef CONFIG_64BIT
1648/* For use by uaccess.h */
1649u64 __ua_limit;
1650EXPORT_SYMBOL(__ua_limit);
1651#endif
1652
9966db25 1653const char *__cpu_name[NR_CPUS];
874fd3b5 1654const char *__elf_platform;
9966db25 1655
078a55fc 1656void cpu_probe(void)
1da177e4
LT		 1657{
1658 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 1659 unsigned int cpu = smp_processor_id();
1da177e4 1660
70342287 1661 c->processor_id = PRID_IMP_UNKNOWN;
1da177e4
LT		 1662 c->fpu_id = FPIR_IMP_NONE;
1663 c->cputype = CPU_UNKNOWN;
4f12b91d 1664 c->writecombine = _CACHE_UNCACHED;
1da177e4 1665
9b26616c
MR		 1666 c->fpu_csr31 = FPU_CSR_RN;
1667 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1668
1da177e4 1669 c->processor_id = read_c0_prid();
8ff374b9 1670 switch (c->processor_id & PRID_COMP_MASK) {
1da177e4 1671 case PRID_COMP_LEGACY:
cea7e2df 1672 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1673 break;
1674 case PRID_COMP_MIPS:
cea7e2df 1675 cpu_probe_mips(c, cpu);
1da177e4
LT		 1676 break;
1677 case PRID_COMP_ALCHEMY:
cea7e2df 1678 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1679 break;
1680 case PRID_COMP_SIBYTE:
cea7e2df 1681 cpu_probe_sibyte(c, cpu);
1da177e4 1682 break;
1c0c13eb 1683 case PRID_COMP_BROADCOM:
cea7e2df 1684 cpu_probe_broadcom(c, cpu);
1c0c13eb 1685 break;
1da177e4 1686 case PRID_COMP_SANDCRAFT:
cea7e2df 1687 cpu_probe_sandcraft(c, cpu);
1da177e4 1688 break;
a92b0588 1689 case PRID_COMP_NXP:
cea7e2df 1690 cpu_probe_nxp(c, cpu);
a3dddd56 1691 break;
0dd4781b
DD		 1692 case PRID_COMP_CAVIUM:
1693 cpu_probe_cavium(c, cpu);
1694 break;
b2edcfc8
HC		 1695 case PRID_COMP_LOONGSON:
1696 cpu_probe_loongson(c, cpu);
1697 break;
252617a4
PB		 1698 case PRID_COMP_INGENIC_D0:
1699 case PRID_COMP_INGENIC_D1:
1700 case PRID_COMP_INGENIC_E1:
83ccf69d
LPC		 1701 cpu_probe_ingenic(c, cpu);
1702 break;
a7117c6b
J		 1703 case PRID_COMP_NETLOGIC:
1704 cpu_probe_netlogic(c, cpu);
1705 break;
1da177e4 1706 }
dec8b1ca 1707
cea7e2df
RB		 1708 BUG_ON(!__cpu_name[cpu]);
1709 BUG_ON(c->cputype == CPU_UNKNOWN);
1710
dec8b1ca
FBH		 1711 /*
1712 * Platform code can force the cpu type to optimize code
1713 * generation. In that case be sure the cpu type is correctly
1714 * manually setup otherwise it could trigger some nasty bugs.
1715 */
1716 BUG_ON(current_cpu_type() != c->cputype);
1717
0103d23f
KC		 1718 if (mips_fpu_disabled)
1719 c->options &= ~MIPS_CPU_FPU;
1720
1721 if (mips_dsp_disabled)
ee80f7c7 1722 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f 1723
3d528b32
MC		 1724 if (mips_htw_disabled) {
1725 c->options &= ~MIPS_CPU_HTW;
1726 write_c0_pwctl(read_c0_pwctl() &
1727 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1728 }
1729
7aecd5ca
MR		 1730 if (c->options & MIPS_CPU_FPU)
1731 cpu_set_fpu_opts(c);
1732 else
1733 cpu_set_nofpu_opts(c);
9966db25 1734
8d5ded16
JK		 1735 if (cpu_has_bp_ghist)
1736 write_c0_r10k_diag(read_c0_r10k_diag() |
1737 R10K_DIAG_E_GHIST);
1738
8b8aa636 1739 if (cpu_has_mips_r2_r6) {
f6771dbb 1740 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
da4b62cd
AC		 1741 /* R2 has Performance Counter Interrupt indicator */
1742 c->options |= MIPS_CPU_PCI;
1743 }
f6771dbb
RB		 1744 else
1745 c->srsets = 1;
91dfc423 1746
4c063034
PB		 1747 if (cpu_has_mips_r6)
1748 elf_hwcap |= HWCAP_MIPS_R6;
1749
a8ad1367 1750 if (cpu_has_msa) {
a5e9a69e 1751 c->msa_id = cpu_get_msa_id();
a8ad1367
PB		 1752 WARN(c->msa_id & MSA_IR_WRPF,
1753 "Vector register partitioning unimplemented!");
3cc9fa7f 1754 elf_hwcap |= HWCAP_MIPS_MSA;
a8ad1367 1755 }
a5e9a69e 1756
91dfc423 1757 cpu_probe_vmbits(c);
949e51be
DD		 1758
1759#ifdef CONFIG_64BIT
1760 if (cpu == 0)
1761 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1762#endif
1da177e4
LT		 1763}
1764
078a55fc 1765void cpu_report(void)
1da177e4
LT		 1766{
1767 struct cpuinfo_mips *c = &current_cpu_data;
1768
d9f897c9
LY		 1769 pr_info("CPU%d revision is: %08x (%s)\n",
1770 smp_processor_id(), c->processor_id, cpu_name_string());
1da177e4 1771 if (c->options & MIPS_CPU_FPU)
9966db25 1772 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
a5e9a69e
PB		 1773 if (cpu_has_msa)
1774 pr_info("MSA revision is: %08x\n", c->msa_id);
1da177e4 1775}
Linux 6.x block layer and io_uring tree(s)