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MIPS: Emulate the new MIPS R6 B{L,G}Ε{Z,}{AL,}C instructions
[linux-2.6-block.git] / arch / mips / kernel / branch.c
CommitLineData
1da177e4
LT		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1996, 97, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2001 MIPS Technologies, Inc.
8 */
9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/signal.h>
d8d4e3ae 12#include <linux/module.h>
1da177e4
LT		 13#include <asm/branch.h>
14#include <asm/cpu.h>
15#include <asm/cpu-features.h>
1d74f6bc 16#include <asm/fpu.h>
fb6883e5 17#include <asm/fpu_emulator.h>
1da177e4
LT		 18#include <asm/inst.h>
19#include <asm/ptrace.h>
20#include <asm/uaccess.h>
21
fb6883e5 22/*
8508488f
SH		 23 * Calculate and return exception PC in case of branch delay slot
24 * for microMIPS and MIPS16e. It does not clear the ISA mode bit.
fb6883e5
LY		 25 */
26int __isa_exception_epc(struct pt_regs *regs)
27{
fb6883e5 28 unsigned short inst;
8508488f 29 long epc = regs->cp0_epc;
fb6883e5
LY		 30
31 /* Calculate exception PC in branch delay slot. */
32 if (__get_user(inst, (u16 __user *) msk_isa16_mode(epc))) {
33 /* This should never happen because delay slot was checked. */
34 force_sig(SIGSEGV, current);
35 return epc;
36 }
8508488f
SH		 37 if (cpu_has_mips16) {
38 if (((union mips16e_instruction)inst).ri.opcode
39 == MIPS16e_jal_op)
40 epc += 4;
41 else
42 epc += 2;
43 } else if (mm_insn_16bit(inst))
fb6883e5
LY		 44 epc += 2;
45 else
46 epc += 4;
47
48 return epc;
49}
50
76fbfc31
RB		 51/* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
52static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7};
53
54int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
55 unsigned long *contpc)
56{
57 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
58 int bc_false = 0;
59 unsigned int fcr31;
60 unsigned int bit;
61
62 if (!cpu_has_mmips)
63 return 0;
64
65 switch (insn.mm_i_format.opcode) {
66 case mm_pool32a_op:
67 if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) ==
68 mm_pool32axf_op) {
69 switch (insn.mm_i_format.simmediate >>
70 MM_POOL32A_MINOR_SHIFT) {
71 case mm_jalr_op:
72 case mm_jalrhb_op:
73 case mm_jalrs_op:
74 case mm_jalrshb_op:
75 if (insn.mm_i_format.rt != 0) /* Not mm_jr */
76 regs->regs[insn.mm_i_format.rt] =
77 regs->cp0_epc +
78 dec_insn.pc_inc +
79 dec_insn.next_pc_inc;
80 *contpc = regs->regs[insn.mm_i_format.rs];
81 return 1;
82 }
83 }
84 break;
85 case mm_pool32i_op:
86 switch (insn.mm_i_format.rt) {
87 case mm_bltzals_op:
88 case mm_bltzal_op:
89 regs->regs[31] = regs->cp0_epc +
90 dec_insn.pc_inc +
91 dec_insn.next_pc_inc;
92 /* Fall through */
93 case mm_bltz_op:
94 if ((long)regs->regs[insn.mm_i_format.rs] < 0)
95 *contpc = regs->cp0_epc +
96 dec_insn.pc_inc +
97 (insn.mm_i_format.simmediate << 1);
98 else
99 *contpc = regs->cp0_epc +
100 dec_insn.pc_inc +
101 dec_insn.next_pc_inc;
102 return 1;
103 case mm_bgezals_op:
104 case mm_bgezal_op:
105 regs->regs[31] = regs->cp0_epc +
106 dec_insn.pc_inc +
107 dec_insn.next_pc_inc;
108 /* Fall through */
109 case mm_bgez_op:
110 if ((long)regs->regs[insn.mm_i_format.rs] >= 0)
111 *contpc = regs->cp0_epc +
112 dec_insn.pc_inc +
113 (insn.mm_i_format.simmediate << 1);
114 else
115 *contpc = regs->cp0_epc +
116 dec_insn.pc_inc +
117 dec_insn.next_pc_inc;
118 return 1;
119 case mm_blez_op:
120 if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
121 *contpc = regs->cp0_epc +
122 dec_insn.pc_inc +
123 (insn.mm_i_format.simmediate << 1);
124 else
125 *contpc = regs->cp0_epc +
126 dec_insn.pc_inc +
127 dec_insn.next_pc_inc;
128 return 1;
129 case mm_bgtz_op:
130 if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
131 *contpc = regs->cp0_epc +
132 dec_insn.pc_inc +
133 (insn.mm_i_format.simmediate << 1);
134 else
135 *contpc = regs->cp0_epc +
136 dec_insn.pc_inc +
137 dec_insn.next_pc_inc;
138 return 1;
139 case mm_bc2f_op:
140 case mm_bc1f_op:
141 bc_false = 1;
142 /* Fall through */
143 case mm_bc2t_op:
144 case mm_bc1t_op:
145 preempt_disable();
146 if (is_fpu_owner())
842dfc11 147 fcr31 = read_32bit_cp1_register(CP1_STATUS);
76fbfc31
RB		 148 else
149 fcr31 = current->thread.fpu.fcr31;
150 preempt_enable();
151
152 if (bc_false)
153 fcr31 = ~fcr31;
154
155 bit = (insn.mm_i_format.rs >> 2);
156 bit += (bit != 0);
157 bit += 23;
158 if (fcr31 & (1 << bit))
159 *contpc = regs->cp0_epc +
160 dec_insn.pc_inc +
161 (insn.mm_i_format.simmediate << 1);
162 else
163 *contpc = regs->cp0_epc +
164 dec_insn.pc_inc + dec_insn.next_pc_inc;
165 return 1;
166 }
167 break;
168 case mm_pool16c_op:
169 switch (insn.mm_i_format.rt) {
170 case mm_jalr16_op:
171 case mm_jalrs16_op:
172 regs->regs[31] = regs->cp0_epc +
173 dec_insn.pc_inc + dec_insn.next_pc_inc;
174 /* Fall through */
175 case mm_jr16_op:
176 *contpc = regs->regs[insn.mm_i_format.rs];
177 return 1;
178 }
179 break;
180 case mm_beqz16_op:
181 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0)
182 *contpc = regs->cp0_epc +
183 dec_insn.pc_inc +
184 (insn.mm_b1_format.simmediate << 1);
185 else
186 *contpc = regs->cp0_epc +
187 dec_insn.pc_inc + dec_insn.next_pc_inc;
188 return 1;
189 case mm_bnez16_op:
190 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0)
191 *contpc = regs->cp0_epc +
192 dec_insn.pc_inc +
193 (insn.mm_b1_format.simmediate << 1);
194 else
195 *contpc = regs->cp0_epc +
196 dec_insn.pc_inc + dec_insn.next_pc_inc;
197 return 1;
198 case mm_b16_op:
199 *contpc = regs->cp0_epc + dec_insn.pc_inc +
200 (insn.mm_b0_format.simmediate << 1);
201 return 1;
202 case mm_beq32_op:
203 if (regs->regs[insn.mm_i_format.rs] ==
204 regs->regs[insn.mm_i_format.rt])
205 *contpc = regs->cp0_epc +
206 dec_insn.pc_inc +
207 (insn.mm_i_format.simmediate << 1);
208 else
209 *contpc = regs->cp0_epc +
210 dec_insn.pc_inc +
211 dec_insn.next_pc_inc;
212 return 1;
213 case mm_bne32_op:
214 if (regs->regs[insn.mm_i_format.rs] !=
215 regs->regs[insn.mm_i_format.rt])
216 *contpc = regs->cp0_epc +
217 dec_insn.pc_inc +
218 (insn.mm_i_format.simmediate << 1);
219 else
220 *contpc = regs->cp0_epc +
221 dec_insn.pc_inc + dec_insn.next_pc_inc;
222 return 1;
223 case mm_jalx32_op:
224 regs->regs[31] = regs->cp0_epc +
225 dec_insn.pc_inc + dec_insn.next_pc_inc;
226 *contpc = regs->cp0_epc + dec_insn.pc_inc;
227 *contpc >>= 28;
228 *contpc <<= 28;
229 *contpc |= (insn.j_format.target << 2);
230 return 1;
231 case mm_jals32_op:
232 case mm_jal32_op:
233 regs->regs[31] = regs->cp0_epc +
234 dec_insn.pc_inc + dec_insn.next_pc_inc;
235 /* Fall through */
236 case mm_j32_op:
237 *contpc = regs->cp0_epc + dec_insn.pc_inc;
238 *contpc >>= 27;
239 *contpc <<= 27;
240 *contpc |= (insn.j_format.target << 1);
241 set_isa16_mode(*contpc);
242 return 1;
243 }
244 return 0;
245}
246
fb6883e5
LY		 247/*
248 * Compute return address and emulate branch in microMIPS mode after an
249 * exception only. It does not handle compact branches/jumps and cannot
250 * be used in interrupt context. (Compact branches/jumps do not cause
251 * exceptions.)
252 */
253int __microMIPS_compute_return_epc(struct pt_regs *regs)
254{
255 u16 __user *pc16;
256 u16 halfword;
257 unsigned int word;
258 unsigned long contpc;
259 struct mm_decoded_insn mminsn = { 0 };
260
261 mminsn.micro_mips_mode = 1;
262
263 /* This load never faults. */
264 pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc);
265 __get_user(halfword, pc16);
266 pc16++;
267 contpc = regs->cp0_epc + 2;
268 word = ((unsigned int)halfword << 16);
269 mminsn.pc_inc = 2;
270
271 if (!mm_insn_16bit(halfword)) {
272 __get_user(halfword, pc16);
273 pc16++;
274 contpc = regs->cp0_epc + 4;
275 mminsn.pc_inc = 4;
276 word |= halfword;
277 }
278 mminsn.insn = word;
279
280 if (get_user(halfword, pc16))
281 goto sigsegv;
282 mminsn.next_pc_inc = 2;
283 word = ((unsigned int)halfword << 16);
284
285 if (!mm_insn_16bit(halfword)) {
286 pc16++;
287 if (get_user(halfword, pc16))
288 goto sigsegv;
289 mminsn.next_pc_inc = 4;
290 word |= halfword;
291 }
292 mminsn.next_insn = word;
293
294 mm_isBranchInstr(regs, mminsn, &contpc);
295
296 regs->cp0_epc = contpc;
297
298 return 0;
299
300sigsegv:
301 force_sig(SIGSEGV, current);
302 return -EFAULT;
303}
304
8508488f
SH		 305/*
306 * Compute return address and emulate branch in MIPS16e mode after an
307 * exception only. It does not handle compact branches/jumps and cannot
308 * be used in interrupt context. (Compact branches/jumps do not cause
309 * exceptions.)
310 */
311int __MIPS16e_compute_return_epc(struct pt_regs *regs)
312{
313 u16 __user *addr;
314 union mips16e_instruction inst;
315 u16 inst2;
316 u32 fullinst;
317 long epc;
318
319 epc = regs->cp0_epc;
320
321 /* Read the instruction. */
322 addr = (u16 __user *)msk_isa16_mode(epc);
323 if (__get_user(inst.full, addr)) {
324 force_sig(SIGSEGV, current);
325 return -EFAULT;
326 }
327
328 switch (inst.ri.opcode) {
329 case MIPS16e_extend_op:
330 regs->cp0_epc += 4;
331 return 0;
332
333 /*
334 * JAL and JALX in MIPS16e mode
335 */
336 case MIPS16e_jal_op:
337 addr += 1;
338 if (__get_user(inst2, addr)) {
339 force_sig(SIGSEGV, current);
340 return -EFAULT;
341 }
342 fullinst = ((unsigned)inst.full << 16) | inst2;
343 regs->regs[31] = epc + 6;
344 epc += 4;
345 epc >>= 28;
346 epc <<= 28;
347 /*
348 * JAL:5 X:1 TARGET[20-16]:5 TARGET[25:21]:5 TARGET[15:0]:16
349 *
350 * ......TARGET[15:0].................TARGET[20:16]...........
351 * ......TARGET[25:21]
352 */
353 epc |=
354 ((fullinst & 0xffff) << 2) | ((fullinst & 0x3e00000) >> 3) |
355 ((fullinst & 0x1f0000) << 7);
356 if (!inst.jal.x)
357 set_isa16_mode(epc); /* Set ISA mode bit. */
358 regs->cp0_epc = epc;
359 return 0;
360
361 /*
362 * J(AL)R(C)
363 */
364 case MIPS16e_rr_op:
365 if (inst.rr.func == MIPS16e_jr_func) {
366
367 if (inst.rr.ra)
368 regs->cp0_epc = regs->regs[31];
369 else
370 regs->cp0_epc =
371 regs->regs[reg16to32[inst.rr.rx]];
372
373 if (inst.rr.l) {
374 if (inst.rr.nd)
375 regs->regs[31] = epc + 2;
376 else
377 regs->regs[31] = epc + 4;
378 }
379 return 0;
380 }
381 break;
382 }
383
384 /*
385 * All other cases have no branch delay slot and are 16-bits.
386 * Branches do not cause an exception.
387 */
388 regs->cp0_epc += 2;
389
390 return 0;
391}
392
d8d4e3ae
MS		 393/**
394 * __compute_return_epc_for_insn - Computes the return address and do emulate
395 * branch simulation, if required.
396 *
397 * @regs: Pointer to pt_regs
398 * @insn: branch instruction to decode
399 * @returns: -EFAULT on error and forces SIGBUS, and on success
400 * returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
401 * evaluating the branch.
a8ff66f5
MC		 402 *
403 * MIPS R6 Compact branches and forbidden slots:
404 * Compact branches do not throw exceptions because they do
405 * not have delay slots. The forbidden slot instruction ($PC+4)
406 * is only executed if the branch was not taken. Otherwise the
407 * forbidden slot is skipped entirely. This means that the
408 * only possible reason to be here because of a MIPS R6 compact
409 * branch instruction is that the forbidden slot has thrown one.
410 * In that case the branch was not taken, so the EPC can be safely
411 * set to EPC + 8.
1da177e4 412 */
d8d4e3ae
MS		 413int __compute_return_epc_for_insn(struct pt_regs *regs,
414 union mips_instruction insn)
1da177e4 415{
c8a34581 416 unsigned int bit, fcr31, dspcontrol, reg;
d8d4e3ae
MS		 417 long epc = regs->cp0_epc;
418 int ret = 0;
1da177e4 419
1da177e4
LT		 420 switch (insn.i_format.opcode) {
421 /*
422 * jr and jalr are in r_format format.
423 */
424 case spec_op:
425 switch (insn.r_format.func) {
426 case jalr_op:
427 regs->regs[insn.r_format.rd] = epc + 8;
428 /* Fall through */
429 case jr_op:
5f9f41c4
MC		 430 if (NO_R6EMU && insn.r_format.func == jr_op)
431 goto sigill_r6;
1da177e4
LT		 432 regs->cp0_epc = regs->regs[insn.r_format.rs];
433 break;
434 }
435 break;
436
437 /*
438 * This group contains:
439 * bltz_op, bgez_op, bltzl_op, bgezl_op,
440 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
441 */
442 case bcond_op:
443 switch (insn.i_format.rt) {
1da177e4 444 case bltzl_op:
319824ea
MC		 445 if (NO_R6EMU)
446 goto sigill_r6;
447 case bltz_op:
d8d4e3ae 448 if ((long)regs->regs[insn.i_format.rs] < 0) {
1da177e4 449 epc = epc + 4 + (insn.i_format.simmediate << 2);
d8d4e3ae
MS		 450 if (insn.i_format.rt == bltzl_op)
451 ret = BRANCH_LIKELY_TAKEN;
452 } else
1da177e4
LT		 453 epc += 8;
454 regs->cp0_epc = epc;
455 break;
456
1da177e4 457 case bgezl_op:
319824ea
MC		 458 if (NO_R6EMU)
459 goto sigill_r6;
460 case bgez_op:
d8d4e3ae 461 if ((long)regs->regs[insn.i_format.rs] >= 0) {
1da177e4 462 epc = epc + 4 + (insn.i_format.simmediate << 2);
d8d4e3ae
MS		 463 if (insn.i_format.rt == bgezl_op)
464 ret = BRANCH_LIKELY_TAKEN;
465 } else
1da177e4
LT		 466 epc += 8;
467 regs->cp0_epc = epc;
468 break;
469
470 case bltzal_op:
471 case bltzall_op:
319824ea
MC		 472 if (NO_R6EMU && (insn.i_format.rs ||
473 insn.i_format.rt == bltzall_op)) {
474 ret = -SIGILL;
475 break;
476 }
1da177e4 477 regs->regs[31] = epc + 8;
319824ea
MC		 478 /*
479 * OK we are here either because we hit a NAL
480 * instruction or because we are emulating an
481 * old bltzal{,l} one. Lets figure out what the
482 * case really is.
483 */
484 if (!insn.i_format.rs) {
485 /*
486 * NAL or BLTZAL with rs == 0
487 * Doesn't matter if we are R6 or not. The
488 * result is the same
489 */
490 regs->cp0_epc += 4 +
491 (insn.i_format.simmediate << 2);
492 break;
493 }
494 /* Now do the real thing for non-R6 BLTZAL{,L} */
d8d4e3ae 495 if ((long)regs->regs[insn.i_format.rs] < 0) {
1da177e4 496 epc = epc + 4 + (insn.i_format.simmediate << 2);
d8d4e3ae
MS		 497 if (insn.i_format.rt == bltzall_op)
498 ret = BRANCH_LIKELY_TAKEN;
499 } else
1da177e4
LT		 500 epc += 8;
501 regs->cp0_epc = epc;
502 break;
503
504 case bgezal_op:
505 case bgezall_op:
319824ea
MC		 506 if (NO_R6EMU && (insn.i_format.rs ||
507 insn.i_format.rt == bgezall_op)) {
508 ret = -SIGILL;
509 break;
510 }
1da177e4 511 regs->regs[31] = epc + 8;
319824ea
MC		 512 /*
513 * OK we are here either because we hit a BAL
514 * instruction or because we are emulating an
515 * old bgezal{,l} one. Lets figure out what the
516 * case really is.
517 */
518 if (!insn.i_format.rs) {
519 /*
520 * BAL or BGEZAL with rs == 0
521 * Doesn't matter if we are R6 or not. The
522 * result is the same
523 */
524 regs->cp0_epc += 4 +
525 (insn.i_format.simmediate << 2);
526 break;
527 }
528 /* Now do the real thing for non-R6 BGEZAL{,L} */
d8d4e3ae 529 if ((long)regs->regs[insn.i_format.rs] >= 0) {
1da177e4 530 epc = epc + 4 + (insn.i_format.simmediate << 2);
d8d4e3ae
MS		 531 if (insn.i_format.rt == bgezall_op)
532 ret = BRANCH_LIKELY_TAKEN;
533 } else
1da177e4
LT		 534 epc += 8;
535 regs->cp0_epc = epc;
536 break;
d8d4e3ae 537
e50c0a8f
RB		 538 case bposge32_op:
539 if (!cpu_has_dsp)
5f9f41c4 540 goto sigill_dsp;
e50c0a8f
RB		 541
542 dspcontrol = rddsp(0x01);
543
544 if (dspcontrol >= 32) {
545 epc = epc + 4 + (insn.i_format.simmediate << 2);
546 } else
547 epc += 8;
548 regs->cp0_epc = epc;
549 break;
1da177e4
LT		 550 }
551 break;
552
553 /*
554 * These are unconditional and in j_format.
555 */
556 case jal_op:
557 regs->regs[31] = regs->cp0_epc + 8;
558 case j_op:
559 epc += 4;
560 epc >>= 28;
561 epc <<= 28;
562 epc |= (insn.j_format.target << 2);
563 regs->cp0_epc = epc;
fb6883e5
LY		 564 if (insn.i_format.opcode == jalx_op)
565 set_isa16_mode(regs->cp0_epc);
1da177e4
LT		 566 break;
567
568 /*
569 * These are conditional and in i_format.
570 */
1da177e4 571 case beql_op:
319824ea
MC		 572 if (NO_R6EMU)
573 goto sigill_r6;
574 case beq_op:
1da177e4 575 if (regs->regs[insn.i_format.rs] ==
d8d4e3ae 576 regs->regs[insn.i_format.rt]) {
1da177e4 577 epc = epc + 4 + (insn.i_format.simmediate << 2);
41ca86e8 578 if (insn.i_format.opcode == beql_op)
d8d4e3ae
MS		 579 ret = BRANCH_LIKELY_TAKEN;
580 } else
1da177e4
LT		 581 epc += 8;
582 regs->cp0_epc = epc;
583 break;
584
1da177e4 585 case bnel_op:
319824ea
MC		 586 if (NO_R6EMU)
587 goto sigill_r6;
588 case bne_op:
1da177e4 589 if (regs->regs[insn.i_format.rs] !=
d8d4e3ae 590 regs->regs[insn.i_format.rt]) {
1da177e4 591 epc = epc + 4 + (insn.i_format.simmediate << 2);
41ca86e8 592 if (insn.i_format.opcode == bnel_op)
d8d4e3ae
MS		 593 ret = BRANCH_LIKELY_TAKEN;
594 } else
1da177e4
LT		 595 epc += 8;
596 regs->cp0_epc = epc;
597 break;
598
319824ea
MC		 599 case blezl_op: /* not really i_format */
600 if (NO_R6EMU)
601 goto sigill_r6;
602 case blez_op:
a8ff66f5
MC		 603 /*
604 * Compact branches for R6 for the
605 * blez and blezl opcodes.
606 * BLEZ | rs = 0 | rt != 0 == BLEZALC
607 * BLEZ | rs = rt != 0 == BGEZALC
608 * BLEZ | rs != 0 | rt != 0 == BGEUC
609 * BLEZL | rs = 0 | rt != 0 == BLEZC
610 * BLEZL | rs = rt != 0 == BGEZC
611 * BLEZL | rs != 0 | rt != 0 == BGEC
612 *
613 * For real BLEZ{,L}, rt is always 0.
614 */
615
616 if (cpu_has_mips_r6 && insn.i_format.rt) {
617 if ((insn.i_format.opcode == blez_op) &&
618 ((!insn.i_format.rs && insn.i_format.rt) ||
619 (insn.i_format.rs == insn.i_format.rt)))
620 regs->regs[31] = epc + 4;
621 regs->cp0_epc += 8;
622 break;
623 }
1da177e4 624 /* rt field assumed to be zero */
d8d4e3ae 625 if ((long)regs->regs[insn.i_format.rs] <= 0) {
1da177e4 626 epc = epc + 4 + (insn.i_format.simmediate << 2);
41ca86e8 627 if (insn.i_format.opcode == blezl_op)
d8d4e3ae
MS		 628 ret = BRANCH_LIKELY_TAKEN;
629 } else
1da177e4
LT		 630 epc += 8;
631 regs->cp0_epc = epc;
632 break;
633
1da177e4 634 case bgtzl_op:
319824ea
MC		 635 if (NO_R6EMU)
636 goto sigill_r6;
637 case bgtz_op:
1da177e4 638 /* rt field assumed to be zero */
d8d4e3ae 639 if ((long)regs->regs[insn.i_format.rs] > 0) {
1da177e4 640 epc = epc + 4 + (insn.i_format.simmediate << 2);
41ca86e8 641 if (insn.i_format.opcode == bgtzl_op)
d8d4e3ae
MS		 642 ret = BRANCH_LIKELY_TAKEN;
643 } else
1da177e4
LT		 644 epc += 8;
645 regs->cp0_epc = epc;
646 break;
647
648 /*
649 * And now the FPA/cp1 branch instructions.
650 */
651 case cop1_op:
c8a34581
MC		 652 if (cpu_has_mips_r6 &&
653 ((insn.i_format.rs == bc1eqz_op) ||
654 (insn.i_format.rs == bc1nez_op))) {
655 if (!used_math()) { /* First time FPU user */
656 ret = init_fpu();
657 if (ret && NO_R6EMU) {
658 ret = -ret;
659 break;
660 }
661 ret = 0;
662 set_used_math();
663 }
664 lose_fpu(1); /* Save FPU state for the emulator. */
665 reg = insn.i_format.rt;
666 bit = 0;
667 switch (insn.i_format.rs) {
668 case bc1eqz_op:
669 /* Test bit 0 */
670 if (get_fpr32(&current->thread.fpu.fpr[reg], 0)
671 & 0x1)
672 bit = 1;
673 break;
674 case bc1nez_op:
675 /* Test bit 0 */
676 if (!(get_fpr32(&current->thread.fpu.fpr[reg], 0)
677 & 0x1))
678 bit = 1;
679 break;
680 }
681 own_fpu(1);
682 if (bit)
683 epc = epc + 4 +
684 (insn.i_format.simmediate << 2);
685 else
1da177e4
LT		 686 epc += 8;
687 regs->cp0_epc = epc;
c8a34581 688
1da177e4 689 break;
c8a34581 690 } else {
1da177e4 691
c8a34581
MC		 692 preempt_disable();
693 if (is_fpu_owner())
694 fcr31 = read_32bit_cp1_register(CP1_STATUS);
695 else
696 fcr31 = current->thread.fpu.fcr31;
697 preempt_enable();
698
699 bit = (insn.i_format.rt >> 2);
700 bit += (bit != 0);
701 bit += 23;
702 switch (insn.i_format.rt & 3) {
703 case 0: /* bc1f */
704 case 2: /* bc1fl */
705 if (~fcr31 & (1 << bit)) {
706 epc = epc + 4 +
707 (insn.i_format.simmediate << 2);
708 if (insn.i_format.rt == 2)
709 ret = BRANCH_LIKELY_TAKEN;
710 } else
711 epc += 8;
712 regs->cp0_epc = epc;
713 break;
714
715 case 1: /* bc1t */
716 case 3: /* bc1tl */
717 if (fcr31 & (1 << bit)) {
718 epc = epc + 4 +
719 (insn.i_format.simmediate << 2);
720 if (insn.i_format.rt == 3)
721 ret = BRANCH_LIKELY_TAKEN;
722 } else
723 epc += 8;
724 regs->cp0_epc = epc;
725 break;
726 }
1da177e4
LT		 727 break;
728 }
126336f0
DD		 729#ifdef CONFIG_CPU_CAVIUM_OCTEON
730 case lwc2_op: /* This is bbit0 on Octeon */
731 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
732 == 0)
733 epc = epc + 4 + (insn.i_format.simmediate << 2);
734 else
735 epc += 8;
736 regs->cp0_epc = epc;
737 break;
738 case ldc2_op: /* This is bbit032 on Octeon */
739 if ((regs->regs[insn.i_format.rs] &
740 (1ull<<(insn.i_format.rt+32))) == 0)
741 epc = epc + 4 + (insn.i_format.simmediate << 2);
742 else
743 epc += 8;
744 regs->cp0_epc = epc;
745 break;
746 case swc2_op: /* This is bbit1 on Octeon */
747 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
748 epc = epc + 4 + (insn.i_format.simmediate << 2);
749 else
750 epc += 8;
751 regs->cp0_epc = epc;
752 break;
753 case sdc2_op: /* This is bbit132 on Octeon */
754 if (regs->regs[insn.i_format.rs] &
755 (1ull<<(insn.i_format.rt+32)))
756 epc = epc + 4 + (insn.i_format.simmediate << 2);
757 else
758 epc += 8;
759 regs->cp0_epc = epc;
760 break;
761#endif
1da177e4
LT		 762 }
763
d8d4e3ae 764 return ret;
1da177e4 765
5f9f41c4 766sigill_dsp:
d8d4e3ae 767 printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm);
1da177e4
LT		 768 force_sig(SIGBUS, current);
769 return -EFAULT;
5f9f41c4
MC		 770sigill_r6:
771 pr_info("%s: R2 branch but r2-to-r6 emulator is not preset - sending SIGILL.\n",
772 current->comm);
773 force_sig(SIGILL, current);
774 return -EFAULT;
d8d4e3ae
MS		 775}
776EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn);
e50c0a8f 777
d8d4e3ae
MS		 778int __compute_return_epc(struct pt_regs *regs)
779{
780 unsigned int __user *addr;
781 long epc;
782 union mips_instruction insn;
783
784 epc = regs->cp0_epc;
785 if (epc & 3)
786 goto unaligned;
787
788 /*
789 * Read the instruction
790 */
791 addr = (unsigned int __user *) epc;
792 if (__get_user(insn.word, addr)) {
793 force_sig(SIGSEGV, current);
794 return -EFAULT;
795 }
796
797 return __compute_return_epc_for_insn(regs, insn);
798
799unaligned:
800 printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
e50c0a8f
RB		 801 force_sig(SIGBUS, current);
802 return -EFAULT;
1da177e4 803}
Linux 6.x block layer and io_uring tree(s)