[linux-2.6-block.git] / arch / mips / include / asm / mach-lantiq / xway / lantiq_soc.h

/*
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 *
 *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 */

#ifndef _LTQ_XWAY_H__
#define _LTQ_XWAY_H__

#ifdef CONFIG_SOC_TYPE_XWAY

#include <lantiq.h>

/* Chip IDs */
#define SOC_ID_DANUBE1		0x129
#define SOC_ID_DANUBE2		0x12B
#define SOC_ID_TWINPASS		0x12D
#define SOC_ID_AMAZON_SE_1	0x152 /* 50601 */
#define SOC_ID_AMAZON_SE_2	0x153 /* 50600 */
#define SOC_ID_ARX188		0x16C
#define SOC_ID_ARX168_1		0x16D
#define SOC_ID_ARX168_2		0x16E
#define SOC_ID_ARX182		0x16F
#define SOC_ID_GRX188		0x170
#define SOC_ID_GRX168		0x171

#define SOC_ID_VRX288		0x1C0 /* v1.1 */
#define SOC_ID_VRX282		0x1C1 /* v1.1 */
#define SOC_ID_VRX268		0x1C2 /* v1.1 */
#define SOC_ID_GRX268		0x1C8 /* v1.1 */
#define SOC_ID_GRX288		0x1C9 /* v1.1 */
#define SOC_ID_VRX288_2		0x00B /* v1.2 */
#define SOC_ID_VRX268_2		0x00C /* v1.2 */
#define SOC_ID_GRX288_2		0x00D /* v1.2 */
#define SOC_ID_GRX282_2		0x00E /* v1.2 */

#define SOC_ID_ARX362		0x004
#define SOC_ID_ARX368		0x005
#define SOC_ID_ARX382		0x007
#define SOC_ID_ARX388		0x008
#define SOC_ID_URX388		0x009
#define SOC_ID_GRX383		0x010
#define SOC_ID_GRX369		0x011
#define SOC_ID_GRX387		0x00F
#define SOC_ID_GRX389		0x012

 /* SoC Types */
#define SOC_TYPE_DANUBE		0x01
#define SOC_TYPE_TWINPASS	0x02
#define SOC_TYPE_AR9		0x03
#define SOC_TYPE_VR9		0x04 /* v1.1 */
#define SOC_TYPE_VR9_2		0x05 /* v1.2 */
#define SOC_TYPE_AMAZON_SE	0x06
#define SOC_TYPE_AR10		0x07
#define SOC_TYPE_GRX390		0x08

/* BOOT_SEL - find what boot media we have */
#define BS_EXT_ROM		0x0
#define BS_FLASH		0x1
#define BS_MII0			0x2
#define BS_PCI			0x3
#define BS_UART1		0x4
#define BS_SPI			0x5
#define BS_NAND			0x6
#define BS_RMII0		0x7

/* helpers used to access the cgu */
#define ltq_cgu_w32(x, y)	ltq_w32((x), ltq_cgu_membase + (y))
#define ltq_cgu_r32(x)		ltq_r32(ltq_cgu_membase + (x))
extern __iomem void *ltq_cgu_membase;

/*
 * during early_printk no ioremap is possible
 * lets use KSEG1 instead
 */
#define LTQ_ASC1_BASE_ADDR	0x1E100C00
#define LTQ_EARLY_ASC		KSEG1ADDR(LTQ_ASC1_BASE_ADDR)

/* EBU - external bus unit */
#define LTQ_EBU_BUSCON0		0x0060
#define LTQ_EBU_PCC_CON		0x0090
#define LTQ_EBU_PCC_IEN		0x00A4
#define LTQ_EBU_PCC_ISTAT	0x00A0
#define LTQ_EBU_BUSCON1		0x0064
#define LTQ_EBU_ADDRSEL1	0x0024
#define EBU_WRDIS		0x80000000

/* WDT */
#define LTQ_RST_CAUSE_WDTRST	0x20

/* MPS - multi processor unit (voice) */
#define LTQ_MPS_BASE_ADDR	(KSEG1 + 0x1F107000)
#define LTQ_MPS_CHIPID		((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))

/* allow booting xrx200 phys */
int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr);

/* request a non-gpio and set the PIO config */
#define PMU_PPE			 BIT(13)
extern void ltq_pmu_enable(unsigned int module);
extern void ltq_pmu_disable(unsigned int module);

#endif /* CONFIG_SOC_TYPE_XWAY */
#endif /* _LTQ_XWAY_H__ */
Commit	Line	Data
8ec6d935 JC	1	/*
	2	* This program is free software; you can redistribute it and/or modify it
	3	* under the terms of the GNU General Public License version 2 as published
	4	* by the Free Software Foundation.
	5	*
	6	* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
	7	*/
	8
	9	#ifndef _LTQ_XWAY_H__
	10	#define _LTQ_XWAY_H__
	11
	12	#ifdef CONFIG_SOC_TYPE_XWAY
	13
	14	#include <lantiq.h>
	15
	16	/* Chip IDs */
	17	#define SOC_ID_DANUBE1 0x129
	18	#define SOC_ID_DANUBE2 0x12B
	19	#define SOC_ID_TWINPASS 0x12D
215ed200 JC	20	#define SOC_ID_AMAZON_SE_1 0x152 /* 50601 */
215ed200 JC	21	#define SOC_ID_AMAZON_SE_2 0x153 /* 50600 */
8ec6d935	22	#define SOC_ID_ARX188 0x16C
215ed200 JC	23	#define SOC_ID_ARX168_1 0x16D
215ed200 JC	24	#define SOC_ID_ARX168_2 0x16E
8ec6d935	25	#define SOC_ID_ARX182 0x16F
215ed200 JC	26	#define SOC_ID_GRX188 0x170
215ed200 JC	27	#define SOC_ID_GRX168 0x171
8ec6d935	28
215ed200 JC	29	#define SOC_ID_VRX288 0x1C0 /* v1.1 */
	30	#define SOC_ID_VRX282 0x1C1 /* v1.1 */
	31	#define SOC_ID_VRX268 0x1C2 /* v1.1 */
	32	#define SOC_ID_GRX268 0x1C8 /* v1.1 */
	33	#define SOC_ID_GRX288 0x1C9 /* v1.1 */
	34	#define SOC_ID_VRX288_2 0x00B /* v1.2 */
	35	#define SOC_ID_VRX268_2 0x00C /* v1.2 */
	36	#define SOC_ID_GRX288_2 0x00D /* v1.2 */
	37	#define SOC_ID_GRX282_2 0x00E /* v1.2 */
	38
a5c1aad8 HM	39	#define SOC_ID_ARX362 0x004
	40	#define SOC_ID_ARX368 0x005
	41	#define SOC_ID_ARX382 0x007
	42	#define SOC_ID_ARX388 0x008
	43	#define SOC_ID_URX388 0x009
	44	#define SOC_ID_GRX383 0x010
	45	#define SOC_ID_GRX369 0x011
	46	#define SOC_ID_GRX387 0x00F
	47	#define SOC_ID_GRX389 0x012
	48
215ed200	49	/* SoC Types */
8ec6d935 JC	50	#define SOC_TYPE_DANUBE 0x01
	51	#define SOC_TYPE_TWINPASS 0x02
	52	#define SOC_TYPE_AR9 0x03
215ed200 JC	53	#define SOC_TYPE_VR9 0x04 /* v1.1 */
	54	#define SOC_TYPE_VR9_2 0x05 /* v1.2 */
	55	#define SOC_TYPE_AMAZON_SE 0x06
a5c1aad8 HM	56	#define SOC_TYPE_AR10 0x07
a5c1aad8 HM	57	#define SOC_TYPE_GRX390 0x08
8ec6d935	58
6697c693 JC	59	/* BOOT_SEL - find what boot media we have */
	60	#define BS_EXT_ROM 0x0
	61	#define BS_FLASH 0x1
	62	#define BS_MII0 0x2
	63	#define BS_PCI 0x3
	64	#define BS_UART1 0x4
	65	#define BS_SPI 0x5
	66	#define BS_NAND 0x6
	67	#define BS_RMII0 0x7
	68
287e3f3f JC	69	/* helpers used to access the cgu */
	70	#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y))
	71	#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x))
	72	extern __iomem void *ltq_cgu_membase;
	73
7705f686 TL	74	/*
	75	* during early_printk no ioremap is possible
	76	* lets use KSEG1 instead
	77	*/
009d6914	78	#define LTQ_ASC1_BASE_ADDR 0x1E100C00
7705f686 TL	79	#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
7705f686 TL	80
8ec6d935	81	/* EBU - external bus unit */
8ec6d935 JC	82	#define LTQ_EBU_BUSCON0 0x0060
	83	#define LTQ_EBU_PCC_CON 0x0090
	84	#define LTQ_EBU_PCC_IEN 0x00A4
	85	#define LTQ_EBU_PCC_ISTAT 0x00A0
	86	#define LTQ_EBU_BUSCON1 0x0064
	87	#define LTQ_EBU_ADDRSEL1 0x0024
	88	#define EBU_WRDIS 0x80000000
	89
8ec6d935	90	/* WDT */
cdb86121 JC	91	#define LTQ_RST_CAUSE_WDTRST 0x20
cdb86121 JC	92
8ec6d935 JC	93	/* MPS - multi processor unit (voice) */
	94	#define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
	95	#define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
	96
af14a456 JC	97	/* allow booting xrx200 phys */
	98	int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr);
	99
8ec6d935	100	/* request a non-gpio and set the PIO config */
009d6914	101	#define PMU_PPE BIT(13)
8ec6d935 JC	102	extern void ltq_pmu_enable(unsigned int module);
	103	extern void ltq_pmu_disable(unsigned int module);
	104
8ec6d935 JC	105	#endif /* CONFIG_SOC_TYPE_XWAY */
8ec6d935 JC	106	#endif /* _LTQ_XWAY_H__ */