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05490626 RB |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Macros for 32/64-bit neutral inline assembler | |
7 | */ | |
8 | ||
9 | #ifndef __ASM_LLSC_H | |
10 | #define __ASM_LLSC_H | |
11 | ||
ef85d057 PB |
12 | #include <asm/isa-rev.h> |
13 | ||
05490626 | 14 | #if _MIPS_SZLONG == 32 |
05490626 RB |
15 | #define __LL "ll " |
16 | #define __SC "sc " | |
17 | #define __INS "ins " | |
18 | #define __EXT "ext " | |
19 | #elif _MIPS_SZLONG == 64 | |
05490626 RB |
20 | #define __LL "lld " |
21 | #define __SC "scd " | |
22 | #define __INS "dins " | |
23 | #define __EXT "dext " | |
24 | #endif | |
25 | ||
878f75c7 PB |
26 | /* |
27 | * Using a branch-likely instruction to check the result of an sc instruction | |
28 | * works around a bug present in R10000 CPUs prior to revision 3.0 that could | |
29 | * cause ll-sc sequences to execute non-atomically. | |
30 | */ | |
31 | #if R10000_LLSC_WAR | |
32 | # define __SC_BEQZ "beqzl " | |
ef85d057 PB |
33 | #elif MIPS_ISA_REV >= 6 |
34 | # define __SC_BEQZ "beqzc " | |
878f75c7 PB |
35 | #else |
36 | # define __SC_BEQZ "beqz " | |
37 | #endif | |
38 | ||
05490626 | 39 | #endif /* __ASM_LLSC_H */ |