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740765ce SL |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | |
7 | * Authors: Sanjay Lal <sanjayl@kymasys.com> | |
8 | */ | |
9 | ||
10 | #ifndef __MIPS_KVM_HOST_H__ | |
11 | #define __MIPS_KVM_HOST_H__ | |
12 | ||
c992a4f6 | 13 | #include <linux/cpumask.h> |
740765ce SL |
14 | #include <linux/mutex.h> |
15 | #include <linux/hrtimer.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/types.h> | |
18 | #include <linux/kvm.h> | |
19 | #include <linux/kvm_types.h> | |
20 | #include <linux/threads.h> | |
21 | #include <linux/spinlock.h> | |
22 | ||
258f3a2e | 23 | #include <asm/inst.h> |
e6207bbe JH |
24 | #include <asm/mipsregs.h> |
25 | ||
48a3c4e4 JH |
26 | /* MIPS KVM register ids */ |
27 | #define MIPS_CP0_32(_R, _S) \ | |
7bd4acec | 28 | (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S))) |
48a3c4e4 JH |
29 | |
30 | #define MIPS_CP0_64(_R, _S) \ | |
7bd4acec | 31 | (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S))) |
48a3c4e4 JH |
32 | |
33 | #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) | |
34 | #define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0) | |
35 | #define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0) | |
36 | #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) | |
dffe042f | 37 | #define KVM_REG_MIPS_CP0_CONTEXTCONFIG MIPS_CP0_32(4, 1) |
48a3c4e4 | 38 | #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) |
dffe042f | 39 | #define KVM_REG_MIPS_CP0_XCONTEXTCONFIG MIPS_CP0_64(4, 3) |
48a3c4e4 JH |
40 | #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) |
41 | #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1) | |
4b7de028 JH |
42 | #define KVM_REG_MIPS_CP0_SEGCTL0 MIPS_CP0_64(5, 2) |
43 | #define KVM_REG_MIPS_CP0_SEGCTL1 MIPS_CP0_64(5, 3) | |
44 | #define KVM_REG_MIPS_CP0_SEGCTL2 MIPS_CP0_64(5, 4) | |
5a2f352f JH |
45 | #define KVM_REG_MIPS_CP0_PWBASE MIPS_CP0_64(5, 5) |
46 | #define KVM_REG_MIPS_CP0_PWFIELD MIPS_CP0_64(5, 6) | |
47 | #define KVM_REG_MIPS_CP0_PWSIZE MIPS_CP0_64(5, 7) | |
48a3c4e4 | 48 | #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) |
5a2f352f | 49 | #define KVM_REG_MIPS_CP0_PWCTL MIPS_CP0_32(6, 6) |
48a3c4e4 JH |
50 | #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) |
51 | #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) | |
edc89260 JH |
52 | #define KVM_REG_MIPS_CP0_BADINSTR MIPS_CP0_32(8, 1) |
53 | #define KVM_REG_MIPS_CP0_BADINSTRP MIPS_CP0_32(8, 2) | |
48a3c4e4 JH |
54 | #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0) |
55 | #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0) | |
56 | #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0) | |
57 | #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0) | |
ad58d4d4 | 58 | #define KVM_REG_MIPS_CP0_INTCTL MIPS_CP0_32(12, 1) |
48a3c4e4 JH |
59 | #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) |
60 | #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) | |
1068eaaf | 61 | #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0) |
48a3c4e4 JH |
62 | #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1) |
63 | #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) | |
64 | #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) | |
65 | #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2) | |
66 | #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3) | |
c771607a JH |
67 | #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4) |
68 | #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5) | |
48a3c4e4 | 69 | #define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7) |
d42a008f | 70 | #define KVM_REG_MIPS_CP0_MAARI MIPS_CP0_64(17, 2) |
48a3c4e4 JH |
71 | #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0) |
72 | #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) | |
05108709 JH |
73 | #define KVM_REG_MIPS_CP0_KSCRATCH1 MIPS_CP0_64(31, 2) |
74 | #define KVM_REG_MIPS_CP0_KSCRATCH2 MIPS_CP0_64(31, 3) | |
75 | #define KVM_REG_MIPS_CP0_KSCRATCH3 MIPS_CP0_64(31, 4) | |
76 | #define KVM_REG_MIPS_CP0_KSCRATCH4 MIPS_CP0_64(31, 5) | |
77 | #define KVM_REG_MIPS_CP0_KSCRATCH5 MIPS_CP0_64(31, 6) | |
78 | #define KVM_REG_MIPS_CP0_KSCRATCH6 MIPS_CP0_64(31, 7) | |
48a3c4e4 | 79 | |
740765ce | 80 | |
12ed1fae | 81 | #define KVM_MAX_VCPUS 8 |
740765ce SL |
82 | #define KVM_USER_MEM_SLOTS 8 |
83 | /* memory slots that does not exposed to userspace */ | |
caa1faa7 | 84 | #define KVM_PRIVATE_MEM_SLOTS 0 |
740765ce SL |
85 | |
86 | #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 | |
920552b2 | 87 | #define KVM_HALT_POLL_NS_DEFAULT 500000 |
740765ce | 88 | |
c992a4f6 JH |
89 | #ifdef CONFIG_KVM_MIPS_VZ |
90 | extern unsigned long GUESTID_MASK; | |
91 | extern unsigned long GUESTID_FIRST_VERSION; | |
92 | extern unsigned long GUESTID_VERSION_MASK; | |
93 | #endif | |
740765ce SL |
94 | |
95 | ||
42aa12e7 JH |
96 | /* |
97 | * Special address that contains the comm page, used for reducing # of traps | |
98 | * This needs to be within 32Kb of 0x0 (so the zero register can be used), but | |
99 | * preferably not at 0x0 so that most kernel NULL pointer dereferences can be | |
100 | * caught. | |
101 | */ | |
102 | #define KVM_GUEST_COMMPAGE_ADDR ((PAGE_SIZE > 0x8000) ? 0 : \ | |
103 | (0x8000 - PAGE_SIZE)) | |
740765ce SL |
104 | |
105 | #define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \ | |
106 | ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0)) | |
107 | ||
22027945 JH |
108 | #define KVM_GUEST_KUSEG 0x00000000UL |
109 | #define KVM_GUEST_KSEG0 0x40000000UL | |
7801bbe1 | 110 | #define KVM_GUEST_KSEG1 0x40000000UL |
22027945 | 111 | #define KVM_GUEST_KSEG23 0x60000000UL |
7f5a1ddc | 112 | #define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0xe0000000) |
22027945 | 113 | #define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) |
740765ce SL |
114 | |
115 | #define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0) | |
116 | #define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1) | |
117 | #define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23) | |
118 | ||
119 | /* | |
120 | * Map an address to a certain kernel segment | |
121 | */ | |
122 | #define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0) | |
123 | #define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1) | |
124 | #define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23) | |
125 | ||
22027945 | 126 | #define KVM_INVALID_PAGE 0xdeadbeef |
22027945 | 127 | #define KVM_INVALID_ADDR 0xdeadbeef |
740765ce | 128 | |
f6f70171 JH |
129 | /* |
130 | * EVA has overlapping user & kernel address spaces, so user VAs may be > | |
131 | * PAGE_OFFSET. For this reason we can't use the default KVM_HVA_ERR_BAD of | |
132 | * PAGE_OFFSET. | |
133 | */ | |
134 | ||
135 | #define KVM_HVA_ERR_BAD (-1UL) | |
136 | #define KVM_HVA_ERR_RO_BAD (-2UL) | |
137 | ||
138 | static inline bool kvm_is_error_hva(unsigned long addr) | |
139 | { | |
140 | return IS_ERR_VALUE(addr); | |
141 | } | |
142 | ||
740765ce | 143 | struct kvm_vm_stat { |
8a7e75d4 | 144 | ulong remote_tlb_flush; |
740765ce SL |
145 | }; |
146 | ||
147 | struct kvm_vcpu_stat { | |
8a7e75d4 SJS |
148 | u64 wait_exits; |
149 | u64 cache_exits; | |
150 | u64 signal_exits; | |
151 | u64 int_exits; | |
152 | u64 cop_unusable_exits; | |
153 | u64 tlbmod_exits; | |
154 | u64 tlbmiss_ld_exits; | |
155 | u64 tlbmiss_st_exits; | |
156 | u64 addrerr_st_exits; | |
157 | u64 addrerr_ld_exits; | |
158 | u64 syscall_exits; | |
159 | u64 resvd_inst_exits; | |
160 | u64 break_inst_exits; | |
161 | u64 trap_inst_exits; | |
162 | u64 msa_fpe_exits; | |
163 | u64 fpe_exits; | |
164 | u64 msa_disabled_exits; | |
165 | u64 flush_dcache_exits; | |
a7244920 JH |
166 | #ifdef CONFIG_KVM_MIPS_VZ |
167 | u64 vz_gpsi_exits; | |
168 | u64 vz_gsfc_exits; | |
169 | u64 vz_hc_exits; | |
170 | u64 vz_grr_exits; | |
171 | u64 vz_gva_exits; | |
172 | u64 vz_ghfc_exits; | |
173 | u64 vz_gpa_exits; | |
174 | u64 vz_resvd_exits; | |
175 | #endif | |
8a7e75d4 SJS |
176 | u64 halt_successful_poll; |
177 | u64 halt_attempted_poll; | |
178 | u64 halt_poll_invalid; | |
179 | u64 halt_wakeup; | |
740765ce SL |
180 | }; |
181 | ||
740765ce SL |
182 | struct kvm_arch_memory_slot { |
183 | }; | |
184 | ||
185 | struct kvm_arch { | |
06c158c9 JH |
186 | /* Guest physical mm */ |
187 | struct mm_struct gpa_mm; | |
c992a4f6 JH |
188 | /* Mask of CPUs needing GPA ASID flush */ |
189 | cpumask_t asid_flush_mask; | |
740765ce SL |
190 | }; |
191 | ||
22027945 JH |
192 | #define N_MIPS_COPROC_REGS 32 |
193 | #define N_MIPS_COPROC_SEL 8 | |
740765ce SL |
194 | |
195 | struct mips_coproc { | |
196 | unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL]; | |
197 | #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS | |
198 | unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL]; | |
199 | #endif | |
200 | }; | |
201 | ||
202 | /* | |
203 | * Coprocessor 0 register names | |
204 | */ | |
22027945 JH |
205 | #define MIPS_CP0_TLB_INDEX 0 |
206 | #define MIPS_CP0_TLB_RANDOM 1 | |
207 | #define MIPS_CP0_TLB_LOW 2 | |
208 | #define MIPS_CP0_TLB_LO0 2 | |
209 | #define MIPS_CP0_TLB_LO1 3 | |
210 | #define MIPS_CP0_TLB_CONTEXT 4 | |
211 | #define MIPS_CP0_TLB_PG_MASK 5 | |
212 | #define MIPS_CP0_TLB_WIRED 6 | |
213 | #define MIPS_CP0_HWRENA 7 | |
214 | #define MIPS_CP0_BAD_VADDR 8 | |
215 | #define MIPS_CP0_COUNT 9 | |
216 | #define MIPS_CP0_TLB_HI 10 | |
217 | #define MIPS_CP0_COMPARE 11 | |
218 | #define MIPS_CP0_STATUS 12 | |
219 | #define MIPS_CP0_CAUSE 13 | |
220 | #define MIPS_CP0_EXC_PC 14 | |
221 | #define MIPS_CP0_PRID 15 | |
222 | #define MIPS_CP0_CONFIG 16 | |
223 | #define MIPS_CP0_LLADDR 17 | |
224 | #define MIPS_CP0_WATCH_LO 18 | |
225 | #define MIPS_CP0_WATCH_HI 19 | |
226 | #define MIPS_CP0_TLB_XCONTEXT 20 | |
227 | #define MIPS_CP0_ECC 26 | |
228 | #define MIPS_CP0_CACHE_ERR 27 | |
229 | #define MIPS_CP0_TAG_LO 28 | |
230 | #define MIPS_CP0_TAG_HI 29 | |
231 | #define MIPS_CP0_ERROR_PC 30 | |
232 | #define MIPS_CP0_DEBUG 23 | |
233 | #define MIPS_CP0_DEPC 24 | |
234 | #define MIPS_CP0_PERFCNT 25 | |
235 | #define MIPS_CP0_ERRCTL 26 | |
236 | #define MIPS_CP0_DATA_LO 28 | |
237 | #define MIPS_CP0_DATA_HI 29 | |
238 | #define MIPS_CP0_DESAVE 31 | |
239 | ||
240 | #define MIPS_CP0_CONFIG_SEL 0 | |
241 | #define MIPS_CP0_CONFIG1_SEL 1 | |
242 | #define MIPS_CP0_CONFIG2_SEL 2 | |
243 | #define MIPS_CP0_CONFIG3_SEL 3 | |
c771607a JH |
244 | #define MIPS_CP0_CONFIG4_SEL 4 |
245 | #define MIPS_CP0_CONFIG5_SEL 5 | |
740765ce | 246 | |
c992a4f6 JH |
247 | #define MIPS_CP0_GUESTCTL2 10 |
248 | #define MIPS_CP0_GUESTCTL2_SEL 5 | |
249 | #define MIPS_CP0_GTOFFSET 12 | |
250 | #define MIPS_CP0_GTOFFSET_SEL 7 | |
251 | ||
740765ce | 252 | /* Resume Flags */ |
22027945 JH |
253 | #define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */ |
254 | #define RESUME_FLAG_HOST (1<<1) /* Resume host? */ | |
740765ce | 255 | |
22027945 JH |
256 | #define RESUME_GUEST 0 |
257 | #define RESUME_GUEST_DR RESUME_FLAG_DR | |
258 | #define RESUME_HOST RESUME_FLAG_HOST | |
740765ce SL |
259 | |
260 | enum emulation_result { | |
261 | EMULATE_DONE, /* no further processing */ | |
262 | EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */ | |
263 | EMULATE_FAIL, /* can't emulate this instruction */ | |
264 | EMULATE_WAIT, /* WAIT instruction */ | |
265 | EMULATE_PRIV_FAIL, | |
4cf74c9c | 266 | EMULATE_EXCEPT, /* A guest exception has been generated */ |
955d8dc3 | 267 | EMULATE_HYPERCALL, /* HYPCALL instruction */ |
740765ce SL |
268 | }; |
269 | ||
740765ce | 270 | #define mips3_paddr_to_tlbpfn(x) \ |
22027945 | 271 | (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME) |
740765ce | 272 | #define mips3_tlbpfn_to_paddr(x) \ |
22027945 | 273 | ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT) |
740765ce | 274 | |
22027945 JH |
275 | #define MIPS3_PG_SHIFT 6 |
276 | #define MIPS3_PG_FRAME 0x3fffffc0 | |
740765ce | 277 | |
22027945 | 278 | #define VPN2_MASK 0xffffe000 |
ca64c2be | 279 | #define KVM_ENTRYHI_ASID MIPS_ENTRYHI_ASID |
e6207bbe | 280 | #define TLB_IS_GLOBAL(x) ((x).tlb_lo[0] & (x).tlb_lo[1] & ENTRYLO_G) |
22027945 | 281 | #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK) |
ca64c2be | 282 | #define TLB_ASID(x) ((x).tlb_hi & KVM_ENTRYHI_ASID) |
19d194c6 | 283 | #define TLB_LO_IDX(x, va) (((va) >> PAGE_SHIFT) & 1) |
e6207bbe | 284 | #define TLB_IS_VALID(x, va) ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_V) |
1880afd6 | 285 | #define TLB_IS_DIRTY(x, va) ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_D) |
d116e812 DCZ |
286 | #define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \ |
287 | ((y) & VPN2_MASK & ~(x).tlb_mask)) | |
288 | #define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \ | |
ca64c2be | 289 | TLB_ASID(x) == ((y) & KVM_ENTRYHI_ASID)) |
740765ce SL |
290 | |
291 | struct kvm_mips_tlb { | |
292 | long tlb_mask; | |
293 | long tlb_hi; | |
9fbfb06a | 294 | long tlb_lo[2]; |
740765ce SL |
295 | }; |
296 | ||
aba85929 JH |
297 | #define KVM_NR_MEM_OBJS 4 |
298 | ||
299 | /* | |
300 | * We don't want allocation failures within the mmu code, so we preallocate | |
301 | * enough memory for a single page fault in a cache. | |
302 | */ | |
303 | struct kvm_mmu_memory_cache { | |
304 | int nobjs; | |
305 | void *objects[KVM_NR_MEM_OBJS]; | |
306 | }; | |
307 | ||
f943176a JH |
308 | #define KVM_MIPS_AUX_FPU 0x1 |
309 | #define KVM_MIPS_AUX_MSA 0x2 | |
98e91b84 | 310 | |
22027945 | 311 | #define KVM_MIPS_GUEST_TLB_SIZE 64 |
740765ce | 312 | struct kvm_vcpu_arch { |
878edf01 | 313 | void *guest_ebase; |
797179bc | 314 | int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu); |
1934a3ad JH |
315 | |
316 | /* Host registers preserved across guest mode execution */ | |
740765ce SL |
317 | unsigned long host_stack; |
318 | unsigned long host_gp; | |
1934a3ad JH |
319 | unsigned long host_pgd; |
320 | unsigned long host_entryhi; | |
740765ce SL |
321 | |
322 | /* Host CP0 registers used when handling exits from guest */ | |
323 | unsigned long host_cp0_badvaddr; | |
740765ce | 324 | unsigned long host_cp0_epc; |
31cf7498 | 325 | u32 host_cp0_cause; |
1934a3ad | 326 | u32 host_cp0_guestctl0; |
6a97c775 JH |
327 | u32 host_cp0_badinstr; |
328 | u32 host_cp0_badinstrp; | |
740765ce SL |
329 | |
330 | /* GPRS */ | |
331 | unsigned long gprs[32]; | |
332 | unsigned long hi; | |
333 | unsigned long lo; | |
334 | unsigned long pc; | |
335 | ||
336 | /* FPU State */ | |
337 | struct mips_fpu_struct fpu; | |
f943176a JH |
338 | /* Which auxiliary state is loaded (KVM_MIPS_AUX_*) */ |
339 | unsigned int aux_inuse; | |
740765ce SL |
340 | |
341 | /* COP0 State */ | |
342 | struct mips_coproc *cop0; | |
343 | ||
344 | /* Host KSEG0 address of the EI/DI offset */ | |
345 | void *kseg0_commpage; | |
346 | ||
e1e575f6 JH |
347 | /* Resume PC after MMIO completion */ |
348 | unsigned long io_pc; | |
349 | /* GPR used as IO source/target */ | |
350 | u32 io_gpr; | |
740765ce | 351 | |
e30492bb | 352 | struct hrtimer comparecount_timer; |
f8239342 | 353 | /* Count timer control KVM register */ |
bdb7ed86 | 354 | u32 count_ctl; |
e30492bb | 355 | /* Count bias from the raw time */ |
bdb7ed86 | 356 | u32 count_bias; |
e30492bb | 357 | /* Frequency of timer in Hz */ |
bdb7ed86 | 358 | u32 count_hz; |
e30492bb JH |
359 | /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */ |
360 | s64 count_dyn_bias; | |
f8239342 JH |
361 | /* Resume time */ |
362 | ktime_t count_resume; | |
e30492bb JH |
363 | /* Period of timer tick in ns */ |
364 | u64 count_period; | |
740765ce SL |
365 | |
366 | /* Bitmask of exceptions that are pending */ | |
367 | unsigned long pending_exceptions; | |
368 | ||
369 | /* Bitmask of pending exceptions to be cleared */ | |
370 | unsigned long pending_exceptions_clr; | |
371 | ||
740765ce SL |
372 | /* S/W Based TLB for guest */ |
373 | struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE]; | |
374 | ||
c550d539 | 375 | /* Guest kernel/user [partial] mm */ |
740765ce SL |
376 | struct mm_struct guest_kernel_mm, guest_user_mm; |
377 | ||
25b08c7f JH |
378 | /* Guest ASID of last user mode execution */ |
379 | unsigned int last_user_gasid; | |
380 | ||
aba85929 JH |
381 | /* Cache some mmu pages needed inside spinlock regions */ |
382 | struct kvm_mmu_memory_cache mmu_page_cache; | |
383 | ||
c992a4f6 JH |
384 | #ifdef CONFIG_KVM_MIPS_VZ |
385 | /* vcpu's vzguestid is different on each host cpu in an smp system */ | |
386 | u32 vzguestid[NR_CPUS]; | |
387 | ||
388 | /* wired guest TLB entries */ | |
389 | struct kvm_mips_tlb *wired_tlb; | |
390 | unsigned int wired_tlb_limit; | |
391 | unsigned int wired_tlb_used; | |
d42a008f JH |
392 | |
393 | /* emulated guest MAAR registers */ | |
394 | unsigned long maar[6]; | |
c992a4f6 JH |
395 | #endif |
396 | ||
397 | /* Last CPU the VCPU state was loaded on */ | |
740765ce | 398 | int last_sched_cpu; |
c992a4f6 JH |
399 | /* Last CPU the VCPU actually executed guest code on */ |
400 | int last_exec_cpu; | |
740765ce SL |
401 | |
402 | /* WAIT executed */ | |
403 | int wait; | |
98e91b84 JH |
404 | |
405 | u8 fpu_enabled; | |
539cb89f | 406 | u8 msa_enabled; |
740765ce SL |
407 | }; |
408 | ||
c73c99b0 JH |
409 | static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg, |
410 | unsigned long val) | |
411 | { | |
412 | unsigned long temp; | |
413 | do { | |
414 | __asm__ __volatile__( | |
d85ebff0 | 415 | " .set "MIPS_ISA_ARCH_LEVEL" \n" |
c73c99b0 JH |
416 | " " __LL "%0, %1 \n" |
417 | " or %0, %2 \n" | |
418 | " " __SC "%0, %1 \n" | |
419 | " .set mips0 \n" | |
420 | : "=&r" (temp), "+m" (*reg) | |
421 | : "r" (val)); | |
422 | } while (unlikely(!temp)); | |
423 | } | |
424 | ||
425 | static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg, | |
426 | unsigned long val) | |
427 | { | |
428 | unsigned long temp; | |
429 | do { | |
430 | __asm__ __volatile__( | |
d85ebff0 | 431 | " .set "MIPS_ISA_ARCH_LEVEL" \n" |
c73c99b0 JH |
432 | " " __LL "%0, %1 \n" |
433 | " and %0, %2 \n" | |
434 | " " __SC "%0, %1 \n" | |
435 | " .set mips0 \n" | |
436 | : "=&r" (temp), "+m" (*reg) | |
437 | : "r" (~val)); | |
438 | } while (unlikely(!temp)); | |
439 | } | |
440 | ||
441 | static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg, | |
442 | unsigned long change, | |
443 | unsigned long val) | |
444 | { | |
445 | unsigned long temp; | |
446 | do { | |
447 | __asm__ __volatile__( | |
d85ebff0 | 448 | " .set "MIPS_ISA_ARCH_LEVEL" \n" |
c73c99b0 JH |
449 | " " __LL "%0, %1 \n" |
450 | " and %0, %2 \n" | |
451 | " or %0, %3 \n" | |
452 | " " __SC "%0, %1 \n" | |
453 | " .set mips0 \n" | |
454 | : "=&r" (temp), "+m" (*reg) | |
455 | : "r" (~change), "r" (val & change)); | |
456 | } while (unlikely(!temp)); | |
457 | } | |
458 | ||
a27660f3 JH |
459 | /* Guest register types, used in accessor build below */ |
460 | #define __KVMT32 u32 | |
461 | #define __KVMTl unsigned long | |
c73c99b0 | 462 | |
a27660f3 JH |
463 | /* |
464 | * __BUILD_KVM_$ops_SAVED(): kvm_$op_sw_gc0_$reg() | |
465 | * These operate on the saved guest C0 state in RAM. | |
466 | */ | |
467 | ||
468 | /* Generate saved context simple accessors */ | |
469 | #define __BUILD_KVM_RW_SAVED(name, type, _reg, sel) \ | |
470 | static inline __KVMT##type kvm_read_sw_gc0_##name(struct mips_coproc *cop0) \ | |
471 | { \ | |
472 | return cop0->reg[(_reg)][(sel)]; \ | |
473 | } \ | |
474 | static inline void kvm_write_sw_gc0_##name(struct mips_coproc *cop0, \ | |
475 | __KVMT##type val) \ | |
476 | { \ | |
477 | cop0->reg[(_reg)][(sel)] = val; \ | |
478 | } | |
479 | ||
480 | /* Generate saved context bitwise modifiers */ | |
481 | #define __BUILD_KVM_SET_SAVED(name, type, _reg, sel) \ | |
482 | static inline void kvm_set_sw_gc0_##name(struct mips_coproc *cop0, \ | |
483 | __KVMT##type val) \ | |
484 | { \ | |
485 | cop0->reg[(_reg)][(sel)] |= val; \ | |
486 | } \ | |
487 | static inline void kvm_clear_sw_gc0_##name(struct mips_coproc *cop0, \ | |
488 | __KVMT##type val) \ | |
489 | { \ | |
490 | cop0->reg[(_reg)][(sel)] &= ~val; \ | |
491 | } \ | |
492 | static inline void kvm_change_sw_gc0_##name(struct mips_coproc *cop0, \ | |
493 | __KVMT##type mask, \ | |
494 | __KVMT##type val) \ | |
495 | { \ | |
496 | unsigned long _mask = mask; \ | |
497 | cop0->reg[(_reg)][(sel)] &= ~_mask; \ | |
498 | cop0->reg[(_reg)][(sel)] |= val & _mask; \ | |
499 | } | |
500 | ||
501 | /* Generate saved context atomic bitwise modifiers */ | |
502 | #define __BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel) \ | |
503 | static inline void kvm_set_sw_gc0_##name(struct mips_coproc *cop0, \ | |
504 | __KVMT##type val) \ | |
505 | { \ | |
506 | _kvm_atomic_set_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \ | |
507 | } \ | |
508 | static inline void kvm_clear_sw_gc0_##name(struct mips_coproc *cop0, \ | |
509 | __KVMT##type val) \ | |
510 | { \ | |
511 | _kvm_atomic_clear_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \ | |
512 | } \ | |
513 | static inline void kvm_change_sw_gc0_##name(struct mips_coproc *cop0, \ | |
514 | __KVMT##type mask, \ | |
515 | __KVMT##type val) \ | |
22027945 | 516 | { \ |
a27660f3 JH |
517 | _kvm_atomic_change_c0_guest_reg(&cop0->reg[(_reg)][(sel)], mask, \ |
518 | val); \ | |
740765ce SL |
519 | } |
520 | ||
a27660f3 JH |
521 | /* |
522 | * __BUILD_KVM_$ops_VZ(): kvm_$op_vz_gc0_$reg() | |
523 | * These operate on the VZ guest C0 context in hardware. | |
524 | */ | |
525 | ||
526 | /* Generate VZ guest context simple accessors */ | |
527 | #define __BUILD_KVM_RW_VZ(name, type, _reg, sel) \ | |
528 | static inline __KVMT##type kvm_read_vz_gc0_##name(struct mips_coproc *cop0) \ | |
529 | { \ | |
530 | return read_gc0_##name(); \ | |
531 | } \ | |
532 | static inline void kvm_write_vz_gc0_##name(struct mips_coproc *cop0, \ | |
533 | __KVMT##type val) \ | |
534 | { \ | |
535 | write_gc0_##name(val); \ | |
536 | } | |
537 | ||
538 | /* Generate VZ guest context bitwise modifiers */ | |
539 | #define __BUILD_KVM_SET_VZ(name, type, _reg, sel) \ | |
540 | static inline void kvm_set_vz_gc0_##name(struct mips_coproc *cop0, \ | |
541 | __KVMT##type val) \ | |
542 | { \ | |
543 | set_gc0_##name(val); \ | |
544 | } \ | |
545 | static inline void kvm_clear_vz_gc0_##name(struct mips_coproc *cop0, \ | |
546 | __KVMT##type val) \ | |
547 | { \ | |
548 | clear_gc0_##name(val); \ | |
549 | } \ | |
550 | static inline void kvm_change_vz_gc0_##name(struct mips_coproc *cop0, \ | |
551 | __KVMT##type mask, \ | |
552 | __KVMT##type val) \ | |
553 | { \ | |
554 | change_gc0_##name(mask, val); \ | |
555 | } | |
556 | ||
557 | /* Generate VZ guest context save/restore to/from saved context */ | |
558 | #define __BUILD_KVM_SAVE_VZ(name, _reg, sel) \ | |
559 | static inline void kvm_restore_gc0_##name(struct mips_coproc *cop0) \ | |
560 | { \ | |
561 | write_gc0_##name(cop0->reg[(_reg)][(sel)]); \ | |
562 | } \ | |
563 | static inline void kvm_save_gc0_##name(struct mips_coproc *cop0) \ | |
564 | { \ | |
565 | cop0->reg[(_reg)][(sel)] = read_gc0_##name(); \ | |
566 | } | |
567 | ||
568 | /* | |
569 | * __BUILD_KVM_$ops_WRAP(): kvm_$op_$name1() -> kvm_$op_$name2() | |
570 | * These wrap a set of operations to provide them with a different name. | |
571 | */ | |
572 | ||
573 | /* Generate simple accessor wrapper */ | |
574 | #define __BUILD_KVM_RW_WRAP(name1, name2, type) \ | |
575 | static inline __KVMT##type kvm_read_##name1(struct mips_coproc *cop0) \ | |
576 | { \ | |
577 | return kvm_read_##name2(cop0); \ | |
578 | } \ | |
579 | static inline void kvm_write_##name1(struct mips_coproc *cop0, \ | |
580 | __KVMT##type val) \ | |
581 | { \ | |
582 | kvm_write_##name2(cop0, val); \ | |
583 | } | |
584 | ||
585 | /* Generate bitwise modifier wrapper */ | |
586 | #define __BUILD_KVM_SET_WRAP(name1, name2, type) \ | |
587 | static inline void kvm_set_##name1(struct mips_coproc *cop0, \ | |
588 | __KVMT##type val) \ | |
589 | { \ | |
590 | kvm_set_##name2(cop0, val); \ | |
591 | } \ | |
592 | static inline void kvm_clear_##name1(struct mips_coproc *cop0, \ | |
593 | __KVMT##type val) \ | |
594 | { \ | |
595 | kvm_clear_##name2(cop0, val); \ | |
596 | } \ | |
597 | static inline void kvm_change_##name1(struct mips_coproc *cop0, \ | |
598 | __KVMT##type mask, \ | |
599 | __KVMT##type val) \ | |
600 | { \ | |
601 | kvm_change_##name2(cop0, mask, val); \ | |
602 | } | |
603 | ||
604 | /* | |
605 | * __BUILD_KVM_$ops_SW(): kvm_$op_c0_guest_$reg() -> kvm_$op_sw_gc0_$reg() | |
606 | * These generate accessors operating on the saved context in RAM, and wrap them | |
607 | * with the common guest C0 accessors (for use by common emulation code). | |
608 | */ | |
609 | ||
610 | #define __BUILD_KVM_RW_SW(name, type, _reg, sel) \ | |
611 | __BUILD_KVM_RW_SAVED(name, type, _reg, sel) \ | |
612 | __BUILD_KVM_RW_WRAP(c0_guest_##name, sw_gc0_##name, type) | |
613 | ||
614 | #define __BUILD_KVM_SET_SW(name, type, _reg, sel) \ | |
615 | __BUILD_KVM_SET_SAVED(name, type, _reg, sel) \ | |
616 | __BUILD_KVM_SET_WRAP(c0_guest_##name, sw_gc0_##name, type) | |
617 | ||
618 | #define __BUILD_KVM_ATOMIC_SW(name, type, _reg, sel) \ | |
619 | __BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel) \ | |
620 | __BUILD_KVM_SET_WRAP(c0_guest_##name, sw_gc0_##name, type) | |
621 | ||
622 | #ifndef CONFIG_KVM_MIPS_VZ | |
623 | ||
624 | /* | |
625 | * T&E (trap & emulate software based virtualisation) | |
626 | * We generate the common accessors operating exclusively on the saved context | |
627 | * in RAM. | |
628 | */ | |
629 | ||
630 | #define __BUILD_KVM_RW_HW __BUILD_KVM_RW_SW | |
631 | #define __BUILD_KVM_SET_HW __BUILD_KVM_SET_SW | |
632 | #define __BUILD_KVM_ATOMIC_HW __BUILD_KVM_ATOMIC_SW | |
633 | ||
634 | #else | |
635 | ||
636 | /* | |
637 | * VZ (hardware assisted virtualisation) | |
638 | * These macros use the active guest state in VZ mode (hardware registers), | |
639 | */ | |
640 | ||
641 | /* | |
642 | * __BUILD_KVM_$ops_HW(): kvm_$op_c0_guest_$reg() -> kvm_$op_vz_gc0_$reg() | |
643 | * These generate accessors operating on the VZ guest context in hardware, and | |
644 | * wrap them with the common guest C0 accessors (for use by common emulation | |
645 | * code). | |
646 | * | |
647 | * Accessors operating on the saved context in RAM are also generated to allow | |
648 | * convenient explicit saving and restoring of the state. | |
649 | */ | |
650 | ||
651 | #define __BUILD_KVM_RW_HW(name, type, _reg, sel) \ | |
652 | __BUILD_KVM_RW_SAVED(name, type, _reg, sel) \ | |
653 | __BUILD_KVM_RW_VZ(name, type, _reg, sel) \ | |
654 | __BUILD_KVM_RW_WRAP(c0_guest_##name, vz_gc0_##name, type) \ | |
655 | __BUILD_KVM_SAVE_VZ(name, _reg, sel) | |
656 | ||
657 | #define __BUILD_KVM_SET_HW(name, type, _reg, sel) \ | |
658 | __BUILD_KVM_SET_SAVED(name, type, _reg, sel) \ | |
659 | __BUILD_KVM_SET_VZ(name, type, _reg, sel) \ | |
660 | __BUILD_KVM_SET_WRAP(c0_guest_##name, vz_gc0_##name, type) | |
661 | ||
662 | /* | |
663 | * We can't do atomic modifications of COP0 state if hardware can modify it. | |
664 | * Races must be handled explicitly. | |
665 | */ | |
666 | #define __BUILD_KVM_ATOMIC_HW __BUILD_KVM_SET_HW | |
667 | ||
668 | #endif | |
669 | ||
670 | /* | |
671 | * Define accessors for CP0 registers that are accessible to the guest. These | |
672 | * are primarily used by common emulation code, which may need to access the | |
673 | * registers differently depending on the implementation. | |
674 | * | |
675 | * fns_hw/sw name type reg num select | |
676 | */ | |
677 | __BUILD_KVM_RW_HW(index, 32, MIPS_CP0_TLB_INDEX, 0) | |
678 | __BUILD_KVM_RW_HW(entrylo0, l, MIPS_CP0_TLB_LO0, 0) | |
679 | __BUILD_KVM_RW_HW(entrylo1, l, MIPS_CP0_TLB_LO1, 0) | |
680 | __BUILD_KVM_RW_HW(context, l, MIPS_CP0_TLB_CONTEXT, 0) | |
dffe042f | 681 | __BUILD_KVM_RW_HW(contextconfig, 32, MIPS_CP0_TLB_CONTEXT, 1) |
a27660f3 | 682 | __BUILD_KVM_RW_HW(userlocal, l, MIPS_CP0_TLB_CONTEXT, 2) |
dffe042f | 683 | __BUILD_KVM_RW_HW(xcontextconfig, l, MIPS_CP0_TLB_CONTEXT, 3) |
a27660f3 JH |
684 | __BUILD_KVM_RW_HW(pagemask, l, MIPS_CP0_TLB_PG_MASK, 0) |
685 | __BUILD_KVM_RW_HW(pagegrain, 32, MIPS_CP0_TLB_PG_MASK, 1) | |
4b7de028 JH |
686 | __BUILD_KVM_RW_HW(segctl0, l, MIPS_CP0_TLB_PG_MASK, 2) |
687 | __BUILD_KVM_RW_HW(segctl1, l, MIPS_CP0_TLB_PG_MASK, 3) | |
688 | __BUILD_KVM_RW_HW(segctl2, l, MIPS_CP0_TLB_PG_MASK, 4) | |
5a2f352f JH |
689 | __BUILD_KVM_RW_HW(pwbase, l, MIPS_CP0_TLB_PG_MASK, 5) |
690 | __BUILD_KVM_RW_HW(pwfield, l, MIPS_CP0_TLB_PG_MASK, 6) | |
691 | __BUILD_KVM_RW_HW(pwsize, l, MIPS_CP0_TLB_PG_MASK, 7) | |
a27660f3 | 692 | __BUILD_KVM_RW_HW(wired, 32, MIPS_CP0_TLB_WIRED, 0) |
5a2f352f | 693 | __BUILD_KVM_RW_HW(pwctl, 32, MIPS_CP0_TLB_WIRED, 6) |
a27660f3 JH |
694 | __BUILD_KVM_RW_HW(hwrena, 32, MIPS_CP0_HWRENA, 0) |
695 | __BUILD_KVM_RW_HW(badvaddr, l, MIPS_CP0_BAD_VADDR, 0) | |
edc89260 JH |
696 | __BUILD_KVM_RW_HW(badinstr, 32, MIPS_CP0_BAD_VADDR, 1) |
697 | __BUILD_KVM_RW_HW(badinstrp, 32, MIPS_CP0_BAD_VADDR, 2) | |
a27660f3 JH |
698 | __BUILD_KVM_RW_SW(count, 32, MIPS_CP0_COUNT, 0) |
699 | __BUILD_KVM_RW_HW(entryhi, l, MIPS_CP0_TLB_HI, 0) | |
700 | __BUILD_KVM_RW_HW(compare, 32, MIPS_CP0_COMPARE, 0) | |
701 | __BUILD_KVM_RW_HW(status, 32, MIPS_CP0_STATUS, 0) | |
702 | __BUILD_KVM_RW_HW(intctl, 32, MIPS_CP0_STATUS, 1) | |
703 | __BUILD_KVM_RW_HW(cause, 32, MIPS_CP0_CAUSE, 0) | |
704 | __BUILD_KVM_RW_HW(epc, l, MIPS_CP0_EXC_PC, 0) | |
705 | __BUILD_KVM_RW_SW(prid, 32, MIPS_CP0_PRID, 0) | |
706 | __BUILD_KVM_RW_HW(ebase, l, MIPS_CP0_PRID, 1) | |
707 | __BUILD_KVM_RW_HW(config, 32, MIPS_CP0_CONFIG, 0) | |
708 | __BUILD_KVM_RW_HW(config1, 32, MIPS_CP0_CONFIG, 1) | |
709 | __BUILD_KVM_RW_HW(config2, 32, MIPS_CP0_CONFIG, 2) | |
710 | __BUILD_KVM_RW_HW(config3, 32, MIPS_CP0_CONFIG, 3) | |
711 | __BUILD_KVM_RW_HW(config4, 32, MIPS_CP0_CONFIG, 4) | |
712 | __BUILD_KVM_RW_HW(config5, 32, MIPS_CP0_CONFIG, 5) | |
713 | __BUILD_KVM_RW_HW(config6, 32, MIPS_CP0_CONFIG, 6) | |
714 | __BUILD_KVM_RW_HW(config7, 32, MIPS_CP0_CONFIG, 7) | |
d42a008f | 715 | __BUILD_KVM_RW_SW(maari, l, MIPS_CP0_LLADDR, 2) |
c992a4f6 | 716 | __BUILD_KVM_RW_HW(xcontext, l, MIPS_CP0_TLB_XCONTEXT, 0) |
a27660f3 JH |
717 | __BUILD_KVM_RW_HW(errorepc, l, MIPS_CP0_ERROR_PC, 0) |
718 | __BUILD_KVM_RW_HW(kscratch1, l, MIPS_CP0_DESAVE, 2) | |
719 | __BUILD_KVM_RW_HW(kscratch2, l, MIPS_CP0_DESAVE, 3) | |
720 | __BUILD_KVM_RW_HW(kscratch3, l, MIPS_CP0_DESAVE, 4) | |
721 | __BUILD_KVM_RW_HW(kscratch4, l, MIPS_CP0_DESAVE, 5) | |
722 | __BUILD_KVM_RW_HW(kscratch5, l, MIPS_CP0_DESAVE, 6) | |
723 | __BUILD_KVM_RW_HW(kscratch6, l, MIPS_CP0_DESAVE, 7) | |
724 | ||
725 | /* Bitwise operations (on HW state) */ | |
726 | __BUILD_KVM_SET_HW(status, 32, MIPS_CP0_STATUS, 0) | |
727 | /* Cause can be modified asynchronously from hardirq hrtimer callback */ | |
728 | __BUILD_KVM_ATOMIC_HW(cause, 32, MIPS_CP0_CAUSE, 0) | |
729 | __BUILD_KVM_SET_HW(ebase, l, MIPS_CP0_PRID, 1) | |
730 | ||
c992a4f6 JH |
731 | /* Bitwise operations (on saved state) */ |
732 | __BUILD_KVM_SET_SAVED(config, 32, MIPS_CP0_CONFIG, 0) | |
733 | __BUILD_KVM_SET_SAVED(config1, 32, MIPS_CP0_CONFIG, 1) | |
734 | __BUILD_KVM_SET_SAVED(config2, 32, MIPS_CP0_CONFIG, 2) | |
735 | __BUILD_KVM_SET_SAVED(config3, 32, MIPS_CP0_CONFIG, 3) | |
736 | __BUILD_KVM_SET_SAVED(config4, 32, MIPS_CP0_CONFIG, 4) | |
737 | __BUILD_KVM_SET_SAVED(config5, 32, MIPS_CP0_CONFIG, 5) | |
738 | ||
98e91b84 JH |
739 | /* Helpers */ |
740 | ||
741 | static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu) | |
742 | { | |
19451e51 | 743 | return (!__builtin_constant_p(raw_cpu_has_fpu) || raw_cpu_has_fpu) && |
98e91b84 JH |
744 | vcpu->fpu_enabled; |
745 | } | |
746 | ||
747 | static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu) | |
748 | { | |
749 | return kvm_mips_guest_can_have_fpu(vcpu) && | |
750 | kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP; | |
751 | } | |
740765ce | 752 | |
539cb89f JH |
753 | static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu) |
754 | { | |
755 | return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) && | |
756 | vcpu->msa_enabled; | |
757 | } | |
758 | ||
759 | static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu) | |
760 | { | |
761 | return kvm_mips_guest_can_have_msa(vcpu) && | |
762 | kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA; | |
763 | } | |
764 | ||
740765ce | 765 | struct kvm_mips_callbacks { |
2dca3725 JH |
766 | int (*handle_cop_unusable)(struct kvm_vcpu *vcpu); |
767 | int (*handle_tlb_mod)(struct kvm_vcpu *vcpu); | |
768 | int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu); | |
769 | int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu); | |
770 | int (*handle_addr_err_st)(struct kvm_vcpu *vcpu); | |
771 | int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu); | |
772 | int (*handle_syscall)(struct kvm_vcpu *vcpu); | |
773 | int (*handle_res_inst)(struct kvm_vcpu *vcpu); | |
774 | int (*handle_break)(struct kvm_vcpu *vcpu); | |
0a560427 | 775 | int (*handle_trap)(struct kvm_vcpu *vcpu); |
c2537ed9 | 776 | int (*handle_msa_fpe)(struct kvm_vcpu *vcpu); |
1c0cd66a | 777 | int (*handle_fpe)(struct kvm_vcpu *vcpu); |
98119ad5 | 778 | int (*handle_msa_disabled)(struct kvm_vcpu *vcpu); |
28c1e762 | 779 | int (*handle_guest_exit)(struct kvm_vcpu *vcpu); |
edab4fe1 JH |
780 | int (*hardware_enable)(void); |
781 | void (*hardware_disable)(void); | |
607ef2fd | 782 | int (*check_extension)(struct kvm *kvm, long ext); |
2dca3725 | 783 | int (*vcpu_init)(struct kvm_vcpu *vcpu); |
630766b3 | 784 | void (*vcpu_uninit)(struct kvm_vcpu *vcpu); |
2dca3725 | 785 | int (*vcpu_setup)(struct kvm_vcpu *vcpu); |
b6209110 JH |
786 | void (*flush_shadow_all)(struct kvm *kvm); |
787 | /* | |
788 | * Must take care of flushing any cached GPA PTEs (e.g. guest entries in | |
789 | * VZ root TLB, or T&E GVA page tables and corresponding root TLB | |
790 | * mappings). | |
791 | */ | |
792 | void (*flush_shadow_memslot)(struct kvm *kvm, | |
793 | const struct kvm_memory_slot *slot); | |
2dca3725 JH |
794 | gpa_t (*gva_to_gpa)(gva_t gva); |
795 | void (*queue_timer_int)(struct kvm_vcpu *vcpu); | |
796 | void (*dequeue_timer_int)(struct kvm_vcpu *vcpu); | |
797 | void (*queue_io_int)(struct kvm_vcpu *vcpu, | |
798 | struct kvm_mips_interrupt *irq); | |
799 | void (*dequeue_io_int)(struct kvm_vcpu *vcpu, | |
800 | struct kvm_mips_interrupt *irq); | |
801 | int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority, | |
bdb7ed86 | 802 | u32 cause); |
2dca3725 | 803 | int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority, |
bdb7ed86 | 804 | u32 cause); |
f5c43bd4 JH |
805 | unsigned long (*num_regs)(struct kvm_vcpu *vcpu); |
806 | int (*copy_reg_indices)(struct kvm_vcpu *vcpu, u64 __user *indices); | |
f8be02da JH |
807 | int (*get_one_reg)(struct kvm_vcpu *vcpu, |
808 | const struct kvm_one_reg *reg, s64 *v); | |
809 | int (*set_one_reg)(struct kvm_vcpu *vcpu, | |
810 | const struct kvm_one_reg *reg, s64 v); | |
a60b8438 JH |
811 | int (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); |
812 | int (*vcpu_put)(struct kvm_vcpu *vcpu, int cpu); | |
a2c046e4 JH |
813 | int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu); |
814 | void (*vcpu_reenter)(struct kvm_run *run, struct kvm_vcpu *vcpu); | |
740765ce SL |
815 | }; |
816 | extern struct kvm_mips_callbacks *kvm_mips_callbacks; | |
817 | int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks); | |
818 | ||
819 | /* Debug: dump vcpu state */ | |
820 | int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu); | |
821 | ||
90e9311a JH |
822 | extern int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu); |
823 | ||
824 | /* Building of entry/exception code */ | |
1e5217f5 | 825 | int kvm_mips_entry_setup(void); |
90e9311a | 826 | void *kvm_mips_build_vcpu_run(void *addr); |
a7cfa7ac | 827 | void *kvm_mips_build_tlb_refill_exception(void *addr, void *handler); |
1f9ca62c | 828 | void *kvm_mips_build_exception(void *addr, void *handler); |
90e9311a | 829 | void *kvm_mips_build_exit(void *addr); |
740765ce | 830 | |
539cb89f | 831 | /* FPU/MSA context management */ |
98e91b84 JH |
832 | void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu); |
833 | void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu); | |
834 | void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu); | |
539cb89f JH |
835 | void __kvm_save_msa(struct kvm_vcpu_arch *vcpu); |
836 | void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu); | |
837 | void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu); | |
838 | void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu); | |
98e91b84 | 839 | void kvm_own_fpu(struct kvm_vcpu *vcpu); |
539cb89f | 840 | void kvm_own_msa(struct kvm_vcpu *vcpu); |
98e91b84 JH |
841 | void kvm_drop_fpu(struct kvm_vcpu *vcpu); |
842 | void kvm_lose_fpu(struct kvm_vcpu *vcpu); | |
843 | ||
740765ce | 844 | /* TLB handling */ |
bdb7ed86 | 845 | u32 kvm_get_kernel_asid(struct kvm_vcpu *vcpu); |
740765ce | 846 | |
bdb7ed86 | 847 | u32 kvm_get_user_asid(struct kvm_vcpu *vcpu); |
740765ce | 848 | |
bdb7ed86 | 849 | u32 kvm_get_commpage_asid (struct kvm_vcpu *vcpu); |
740765ce | 850 | |
c992a4f6 JH |
851 | #ifdef CONFIG_KVM_MIPS_VZ |
852 | int kvm_mips_handle_vz_root_tlb_fault(unsigned long badvaddr, | |
853 | struct kvm_vcpu *vcpu, bool write_fault); | |
854 | #endif | |
740765ce | 855 | extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr, |
577ed7f7 JH |
856 | struct kvm_vcpu *vcpu, |
857 | bool write_fault); | |
740765ce SL |
858 | |
859 | extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr, | |
860 | struct kvm_vcpu *vcpu); | |
861 | ||
862 | extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu, | |
7e3d2a75 | 863 | struct kvm_mips_tlb *tlb, |
577ed7f7 JH |
864 | unsigned long gva, |
865 | bool write_fault); | |
740765ce | 866 | |
31cf7498 | 867 | extern enum emulation_result kvm_mips_handle_tlbmiss(u32 cause, |
bdb7ed86 | 868 | u32 *opc, |
740765ce | 869 | struct kvm_run *run, |
577ed7f7 JH |
870 | struct kvm_vcpu *vcpu, |
871 | bool write_fault); | |
740765ce | 872 | |
740765ce SL |
873 | extern void kvm_mips_dump_host_tlbs(void); |
874 | extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu); | |
57e3869c JH |
875 | extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi, |
876 | bool user, bool kernel); | |
740765ce SL |
877 | |
878 | extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu, | |
879 | unsigned long entryhi); | |
a7ebb2e4 | 880 | |
372582a6 JH |
881 | #ifdef CONFIG_KVM_MIPS_VZ |
882 | int kvm_vz_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi); | |
883 | int kvm_vz_guest_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long gva, | |
884 | unsigned long *gpa); | |
885 | void kvm_vz_local_flush_roottlb_all_guests(void); | |
886 | void kvm_vz_local_flush_guesttlb_all(void); | |
887 | void kvm_vz_save_guesttlb(struct kvm_mips_tlb *buf, unsigned int index, | |
888 | unsigned int count); | |
889 | void kvm_vz_load_guesttlb(const struct kvm_mips_tlb *buf, unsigned int index, | |
890 | unsigned int count); | |
891 | #endif | |
892 | ||
a7ebb2e4 JH |
893 | void kvm_mips_suspend_mm(int cpu); |
894 | void kvm_mips_resume_mm(int cpu); | |
895 | ||
a31b50d7 JH |
896 | /* MMU handling */ |
897 | ||
898 | /** | |
899 | * enum kvm_mips_flush - Types of MMU flushes. | |
900 | * @KMF_USER: Flush guest user virtual memory mappings. | |
901 | * Guest USeg only. | |
902 | * @KMF_KERN: Flush guest kernel virtual memory mappings. | |
903 | * Guest USeg and KSeg2/3. | |
904 | * @KMF_GPA: Flush guest physical memory mappings. | |
905 | * Also includes KSeg0 if KMF_KERN is set. | |
906 | */ | |
907 | enum kvm_mips_flush { | |
908 | KMF_USER = 0x0, | |
909 | KMF_KERN = 0x1, | |
910 | KMF_GPA = 0x2, | |
911 | }; | |
912 | void kvm_mips_flush_gva_pt(pgd_t *pgd, enum kvm_mips_flush flags); | |
06c158c9 | 913 | bool kvm_mips_flush_gpa_pt(struct kvm *kvm, gfn_t start_gfn, gfn_t end_gfn); |
f0c0c330 | 914 | int kvm_mips_mkclean_gpa_pt(struct kvm *kvm, gfn_t start_gfn, gfn_t end_gfn); |
06c158c9 | 915 | pgd_t *kvm_pgd_alloc(void); |
aba85929 JH |
916 | void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu); |
917 | void kvm_trap_emul_invalidate_gva(struct kvm_vcpu *vcpu, unsigned long addr, | |
918 | bool user); | |
1880afd6 JH |
919 | void kvm_trap_emul_gva_lockless_begin(struct kvm_vcpu *vcpu); |
920 | void kvm_trap_emul_gva_lockless_end(struct kvm_vcpu *vcpu); | |
921 | ||
922 | enum kvm_mips_fault_result { | |
923 | KVM_MIPS_MAPPED = 0, | |
924 | KVM_MIPS_GVA, | |
925 | KVM_MIPS_GPA, | |
926 | KVM_MIPS_TLB, | |
927 | KVM_MIPS_TLBINV, | |
928 | KVM_MIPS_TLBMOD, | |
929 | }; | |
930 | enum kvm_mips_fault_result kvm_trap_emul_gva_fault(struct kvm_vcpu *vcpu, | |
931 | unsigned long gva, | |
932 | bool write); | |
740765ce | 933 | |
411740f5 JH |
934 | #define KVM_ARCH_WANT_MMU_NOTIFIER |
935 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva); | |
936 | int kvm_unmap_hva_range(struct kvm *kvm, | |
937 | unsigned long start, unsigned long end); | |
938 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); | |
939 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); | |
940 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); | |
941 | ||
942 | static inline void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, | |
943 | unsigned long address) | |
944 | { | |
945 | } | |
946 | ||
740765ce | 947 | /* Emulation */ |
122e51d4 | 948 | int kvm_get_inst(u32 *opc, struct kvm_vcpu *vcpu, u32 *out); |
bdb7ed86 | 949 | enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause); |
6a97c775 JH |
950 | int kvm_get_badinstr(u32 *opc, struct kvm_vcpu *vcpu, u32 *out); |
951 | int kvm_get_badinstrp(u32 *opc, struct kvm_vcpu *vcpu, u32 *out); | |
740765ce | 952 | |
a1ecc54d JH |
953 | /** |
954 | * kvm_is_ifetch_fault() - Find whether a TLBL exception is due to ifetch fault. | |
955 | * @vcpu: Virtual CPU. | |
956 | * | |
957 | * Returns: Whether the TLBL exception was likely due to an instruction | |
958 | * fetch fault rather than a data load fault. | |
959 | */ | |
960 | static inline bool kvm_is_ifetch_fault(struct kvm_vcpu_arch *vcpu) | |
961 | { | |
962 | unsigned long badvaddr = vcpu->host_cp0_badvaddr; | |
963 | unsigned long epc = msk_isa16_mode(vcpu->pc); | |
964 | u32 cause = vcpu->host_cp0_cause; | |
965 | ||
966 | if (epc == badvaddr) | |
967 | return true; | |
968 | ||
969 | /* | |
970 | * Branches may be 32-bit or 16-bit instructions. | |
971 | * This isn't exact, but we don't really support MIPS16 or microMIPS yet | |
972 | * in KVM anyway. | |
973 | */ | |
974 | if ((cause & CAUSEF_BD) && badvaddr - epc <= 4) | |
975 | return true; | |
976 | ||
977 | return false; | |
978 | } | |
979 | ||
31cf7498 | 980 | extern enum emulation_result kvm_mips_emulate_inst(u32 cause, |
bdb7ed86 | 981 | u32 *opc, |
740765ce SL |
982 | struct kvm_run *run, |
983 | struct kvm_vcpu *vcpu); | |
984 | ||
7801bbe1 JH |
985 | long kvm_mips_guest_exception_base(struct kvm_vcpu *vcpu); |
986 | ||
31cf7498 | 987 | extern enum emulation_result kvm_mips_emulate_syscall(u32 cause, |
bdb7ed86 | 988 | u32 *opc, |
740765ce SL |
989 | struct kvm_run *run, |
990 | struct kvm_vcpu *vcpu); | |
991 | ||
31cf7498 | 992 | extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(u32 cause, |
bdb7ed86 | 993 | u32 *opc, |
740765ce SL |
994 | struct kvm_run *run, |
995 | struct kvm_vcpu *vcpu); | |
996 | ||
31cf7498 | 997 | extern enum emulation_result kvm_mips_emulate_tlbinv_ld(u32 cause, |
bdb7ed86 | 998 | u32 *opc, |
740765ce SL |
999 | struct kvm_run *run, |
1000 | struct kvm_vcpu *vcpu); | |
1001 | ||
31cf7498 | 1002 | extern enum emulation_result kvm_mips_emulate_tlbmiss_st(u32 cause, |
bdb7ed86 | 1003 | u32 *opc, |
740765ce SL |
1004 | struct kvm_run *run, |
1005 | struct kvm_vcpu *vcpu); | |
1006 | ||
31cf7498 | 1007 | extern enum emulation_result kvm_mips_emulate_tlbinv_st(u32 cause, |
bdb7ed86 | 1008 | u32 *opc, |
740765ce SL |
1009 | struct kvm_run *run, |
1010 | struct kvm_vcpu *vcpu); | |
1011 | ||
31cf7498 | 1012 | extern enum emulation_result kvm_mips_emulate_tlbmod(u32 cause, |
bdb7ed86 | 1013 | u32 *opc, |
740765ce SL |
1014 | struct kvm_run *run, |
1015 | struct kvm_vcpu *vcpu); | |
1016 | ||
31cf7498 | 1017 | extern enum emulation_result kvm_mips_emulate_fpu_exc(u32 cause, |
bdb7ed86 | 1018 | u32 *opc, |
740765ce SL |
1019 | struct kvm_run *run, |
1020 | struct kvm_vcpu *vcpu); | |
1021 | ||
31cf7498 | 1022 | extern enum emulation_result kvm_mips_handle_ri(u32 cause, |
bdb7ed86 | 1023 | u32 *opc, |
740765ce SL |
1024 | struct kvm_run *run, |
1025 | struct kvm_vcpu *vcpu); | |
1026 | ||
31cf7498 | 1027 | extern enum emulation_result kvm_mips_emulate_ri_exc(u32 cause, |
bdb7ed86 | 1028 | u32 *opc, |
740765ce SL |
1029 | struct kvm_run *run, |
1030 | struct kvm_vcpu *vcpu); | |
1031 | ||
31cf7498 | 1032 | extern enum emulation_result kvm_mips_emulate_bp_exc(u32 cause, |
bdb7ed86 | 1033 | u32 *opc, |
740765ce SL |
1034 | struct kvm_run *run, |
1035 | struct kvm_vcpu *vcpu); | |
1036 | ||
31cf7498 | 1037 | extern enum emulation_result kvm_mips_emulate_trap_exc(u32 cause, |
bdb7ed86 | 1038 | u32 *opc, |
0a560427 JH |
1039 | struct kvm_run *run, |
1040 | struct kvm_vcpu *vcpu); | |
1041 | ||
31cf7498 | 1042 | extern enum emulation_result kvm_mips_emulate_msafpe_exc(u32 cause, |
bdb7ed86 | 1043 | u32 *opc, |
c2537ed9 JH |
1044 | struct kvm_run *run, |
1045 | struct kvm_vcpu *vcpu); | |
1046 | ||
31cf7498 | 1047 | extern enum emulation_result kvm_mips_emulate_fpe_exc(u32 cause, |
bdb7ed86 | 1048 | u32 *opc, |
1c0cd66a JH |
1049 | struct kvm_run *run, |
1050 | struct kvm_vcpu *vcpu); | |
1051 | ||
31cf7498 | 1052 | extern enum emulation_result kvm_mips_emulate_msadis_exc(u32 cause, |
bdb7ed86 | 1053 | u32 *opc, |
c2537ed9 JH |
1054 | struct kvm_run *run, |
1055 | struct kvm_vcpu *vcpu); | |
1056 | ||
740765ce SL |
1057 | extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu, |
1058 | struct kvm_run *run); | |
1059 | ||
bdb7ed86 JH |
1060 | u32 kvm_mips_read_count(struct kvm_vcpu *vcpu); |
1061 | void kvm_mips_write_count(struct kvm_vcpu *vcpu, u32 count); | |
1062 | void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack); | |
a517c1ad | 1063 | void kvm_mips_init_count(struct kvm_vcpu *vcpu, unsigned long count_hz); |
f8239342 JH |
1064 | int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl); |
1065 | int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume); | |
f74a8e22 | 1066 | int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz); |
e30492bb JH |
1067 | void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu); |
1068 | void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu); | |
1069 | enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu); | |
740765ce | 1070 | |
31cf7498 | 1071 | enum emulation_result kvm_mips_check_privilege(u32 cause, |
bdb7ed86 | 1072 | u32 *opc, |
740765ce SL |
1073 | struct kvm_run *run, |
1074 | struct kvm_vcpu *vcpu); | |
1075 | ||
258f3a2e | 1076 | enum emulation_result kvm_mips_emulate_cache(union mips_instruction inst, |
bdb7ed86 JH |
1077 | u32 *opc, |
1078 | u32 cause, | |
740765ce SL |
1079 | struct kvm_run *run, |
1080 | struct kvm_vcpu *vcpu); | |
258f3a2e | 1081 | enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst, |
bdb7ed86 JH |
1082 | u32 *opc, |
1083 | u32 cause, | |
740765ce SL |
1084 | struct kvm_run *run, |
1085 | struct kvm_vcpu *vcpu); | |
258f3a2e | 1086 | enum emulation_result kvm_mips_emulate_store(union mips_instruction inst, |
bdb7ed86 | 1087 | u32 cause, |
740765ce SL |
1088 | struct kvm_run *run, |
1089 | struct kvm_vcpu *vcpu); | |
258f3a2e | 1090 | enum emulation_result kvm_mips_emulate_load(union mips_instruction inst, |
bdb7ed86 | 1091 | u32 cause, |
740765ce SL |
1092 | struct kvm_run *run, |
1093 | struct kvm_vcpu *vcpu); | |
1094 | ||
c992a4f6 JH |
1095 | /* COP0 */ |
1096 | enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu); | |
1097 | ||
c771607a JH |
1098 | unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu); |
1099 | unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu); | |
1100 | unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu); | |
1101 | unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu); | |
1102 | ||
955d8dc3 JH |
1103 | /* Hypercalls (hypcall.c) */ |
1104 | ||
1105 | enum emulation_result kvm_mips_emul_hypcall(struct kvm_vcpu *vcpu, | |
1106 | union mips_instruction inst); | |
1107 | int kvm_mips_handle_hypcall(struct kvm_vcpu *vcpu); | |
1108 | ||
740765ce | 1109 | /* Dynamic binary translation */ |
258f3a2e JH |
1110 | extern int kvm_mips_trans_cache_index(union mips_instruction inst, |
1111 | u32 *opc, struct kvm_vcpu *vcpu); | |
1112 | extern int kvm_mips_trans_cache_va(union mips_instruction inst, u32 *opc, | |
1113 | struct kvm_vcpu *vcpu); | |
1114 | extern int kvm_mips_trans_mfc0(union mips_instruction inst, u32 *opc, | |
1115 | struct kvm_vcpu *vcpu); | |
1116 | extern int kvm_mips_trans_mtc0(union mips_instruction inst, u32 *opc, | |
1117 | struct kvm_vcpu *vcpu); | |
740765ce SL |
1118 | |
1119 | /* Misc */ | |
d98403a5 | 1120 | extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu); |
740765ce SL |
1121 | extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm); |
1122 | ||
0865e636 RK |
1123 | static inline void kvm_arch_hardware_unsetup(void) {} |
1124 | static inline void kvm_arch_sync_events(struct kvm *kvm) {} | |
1125 | static inline void kvm_arch_free_memslot(struct kvm *kvm, | |
1126 | struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {} | |
15f46015 | 1127 | static inline void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) {} |
0865e636 | 1128 | static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} |
3217f7c2 CD |
1129 | static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {} |
1130 | static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {} | |
3491caf2 | 1131 | static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} |
740765ce SL |
1132 | |
1133 | #endif /* __MIPS_KVM_HOST_H__ */ |