[linux-2.6-block.git] / arch / mips / include / asm / cpu.h

/*
 * cpu.h: Values of the PRId register used to match up
 *	  various MIPS cpu types.
 *
 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
 * Copyright (C) 2004, 2013  Maciej W. Rozycki
 */
#ifndef _ASM_CPU_H
#define _ASM_CPU_H

/*
   As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0
   register 15, select 0) is defined in this (backwards compatible) way:

  +----------------+----------------+----------------+----------------+
  | Company Options| Company ID	    | Processor ID   | Revision	      |
  +----------------+----------------+----------------+----------------+
   31		 24 23		  16 15		    8 7

   I don't have docs for all the previous processors, but my impression is
   that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
   spec.
*/

#define PRID_OPT_MASK		0xff000000

/*
 * Assigned Company values for bits 23:16 of the PRId register.
 */

#define PRID_COMP_MASK		0xff0000

#define PRID_COMP_LEGACY	0x000000
#define PRID_COMP_MIPS		0x010000
#define PRID_COMP_BROADCOM	0x020000
#define PRID_COMP_ALCHEMY	0x030000
#define PRID_COMP_SIBYTE	0x040000
#define PRID_COMP_SANDCRAFT	0x050000
#define PRID_COMP_NXP		0x060000
#define PRID_COMP_TOSHIBA	0x070000
#define PRID_COMP_LSI		0x080000
#define PRID_COMP_LEXRA		0x0b0000
#define PRID_COMP_NETLOGIC	0x0c0000
#define PRID_COMP_CAVIUM	0x0d0000
#define PRID_COMP_LOONGSON	0x140000
#define PRID_COMP_INGENIC_D0	0xd00000	/* JZ4740, JZ4750 */
#define PRID_COMP_INGENIC_D1	0xd10000	/* JZ4770, JZ4775 */
#define PRID_COMP_INGENIC_E1	0xe10000	/* JZ4780 */

/*
 * Assigned Processor ID (implementation) values for bits 15:8 of the PRId
 * register.  In order to detect a certain CPU type exactly eventually
 * additional registers may need to be examined.
 */

#define PRID_IMP_MASK		0xff00

/*
 * These are valid when 23:16 == PRID_COMP_LEGACY
 */

#define PRID_IMP_R2000		0x0100
#define PRID_IMP_AU1_REV1	0x0100
#define PRID_IMP_AU1_REV2	0x0200
#define PRID_IMP_R3000		0x0200		/* Same as R2000A  */
#define PRID_IMP_R6000		0x0300		/* Same as R3000A  */
#define PRID_IMP_R4000		0x0400
#define PRID_IMP_R6000A		0x0600
#define PRID_IMP_R10000		0x0900
#define PRID_IMP_R4300		0x0b00
#define PRID_IMP_VR41XX		0x0c00
#define PRID_IMP_R12000		0x0e00
#define PRID_IMP_R14000		0x0f00		/* R14K && R16K */
#define PRID_IMP_R8000		0x1000
#define PRID_IMP_PR4450		0x1200
#define PRID_IMP_R4600		0x2000
#define PRID_IMP_R4700		0x2100
#define PRID_IMP_TX39		0x2200
#define PRID_IMP_R4640		0x2200
#define PRID_IMP_R4650		0x2200		/* Same as R4640 */
#define PRID_IMP_R5000		0x2300
#define PRID_IMP_TX49		0x2d00
#define PRID_IMP_SONIC		0x2400
#define PRID_IMP_MAGIC		0x2500
#define PRID_IMP_RM7000		0x2700
#define PRID_IMP_NEVADA		0x2800		/* RM5260 ??? */
#define PRID_IMP_RM9000		0x3400
#define PRID_IMP_LOONGSON_32	0x4200  /* Loongson-1 */
#define PRID_IMP_R5432		0x5400
#define PRID_IMP_R5500		0x5500
#define PRID_IMP_LOONGSON_64	0x6300  /* Loongson-2/3 */

#define PRID_IMP_UNKNOWN	0xff00

/*
 * These are the PRID's for when 23:16 == PRID_COMP_MIPS
 */

#define PRID_IMP_QEMU_GENERIC	0x0000
#define PRID_IMP_4KC		0x8000
#define PRID_IMP_5KC		0x8100
#define PRID_IMP_20KC		0x8200
#define PRID_IMP_4KEC		0x8400
#define PRID_IMP_4KSC		0x8600
#define PRID_IMP_25KF		0x8800
#define PRID_IMP_5KE		0x8900
#define PRID_IMP_4KECR2		0x9000
#define PRID_IMP_4KEMPR2	0x9100
#define PRID_IMP_4KSD		0x9200
#define PRID_IMP_24K		0x9300
#define PRID_IMP_34K		0x9500
#define PRID_IMP_24KE		0x9600
#define PRID_IMP_74K		0x9700
#define PRID_IMP_1004K		0x9900
#define PRID_IMP_1074K		0x9a00
#define PRID_IMP_M14KC		0x9c00
#define PRID_IMP_M14KEC		0x9e00
#define PRID_IMP_INTERAPTIV_UP	0xa000
#define PRID_IMP_INTERAPTIV_MP	0xa100
#define PRID_IMP_PROAPTIV_UP	0xa200
#define PRID_IMP_PROAPTIV_MP	0xa300
#define PRID_IMP_P6600		0xa400
#define PRID_IMP_M5150		0xa700
#define PRID_IMP_P5600		0xa800
#define PRID_IMP_I6400		0xa900
#define PRID_IMP_M6250		0xab00

/*
 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
 */

#define PRID_IMP_SB1		0x0100
#define PRID_IMP_SB1A		0x1100

/*
 * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
 */

#define PRID_IMP_SR71000	0x0400

/*
 * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
 */

#define PRID_IMP_BMIPS32_REV4	0x4000
#define PRID_IMP_BMIPS32_REV8	0x8000
#define PRID_IMP_BMIPS3300	0x9000
#define PRID_IMP_BMIPS3300_ALT	0x9100
#define PRID_IMP_BMIPS3300_BUG	0x0000
#define PRID_IMP_BMIPS43XX	0xa000
#define PRID_IMP_BMIPS5000	0x5a00
#define PRID_IMP_BMIPS5200	0x5b00

#define PRID_REV_BMIPS4380_LO	0x0040
#define PRID_REV_BMIPS4380_HI	0x006f

/*
 * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
 */

#define PRID_IMP_CAVIUM_CN38XX 0x0000
#define PRID_IMP_CAVIUM_CN31XX 0x0100
#define PRID_IMP_CAVIUM_CN30XX 0x0200
#define PRID_IMP_CAVIUM_CN58XX 0x0300
#define PRID_IMP_CAVIUM_CN56XX 0x0400
#define PRID_IMP_CAVIUM_CN50XX 0x0600
#define PRID_IMP_CAVIUM_CN52XX 0x0700
#define PRID_IMP_CAVIUM_CN63XX 0x9000
#define PRID_IMP_CAVIUM_CN68XX 0x9100
#define PRID_IMP_CAVIUM_CN66XX 0x9200
#define PRID_IMP_CAVIUM_CN61XX 0x9300
#define PRID_IMP_CAVIUM_CNF71XX 0x9400
#define PRID_IMP_CAVIUM_CN78XX 0x9500
#define PRID_IMP_CAVIUM_CN70XX 0x9600
#define PRID_IMP_CAVIUM_CN73XX 0x9700
#define PRID_IMP_CAVIUM_CNF75XX 0x9800

/*
 * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
 */

#define PRID_IMP_JZRISC	       0x0200

/*
 * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
 */
#define PRID_IMP_NETLOGIC_XLR732	0x0000
#define PRID_IMP_NETLOGIC_XLR716	0x0200
#define PRID_IMP_NETLOGIC_XLR532	0x0900
#define PRID_IMP_NETLOGIC_XLR308	0x0600
#define PRID_IMP_NETLOGIC_XLR532C	0x0800
#define PRID_IMP_NETLOGIC_XLR516C	0x0a00
#define PRID_IMP_NETLOGIC_XLR508C	0x0b00
#define PRID_IMP_NETLOGIC_XLR308C	0x0f00
#define PRID_IMP_NETLOGIC_XLS608	0x8000
#define PRID_IMP_NETLOGIC_XLS408	0x8800
#define PRID_IMP_NETLOGIC_XLS404	0x8c00
#define PRID_IMP_NETLOGIC_XLS208	0x8e00
#define PRID_IMP_NETLOGIC_XLS204	0x8f00
#define PRID_IMP_NETLOGIC_XLS108	0xce00
#define PRID_IMP_NETLOGIC_XLS104	0xcf00
#define PRID_IMP_NETLOGIC_XLS616B	0x4000
#define PRID_IMP_NETLOGIC_XLS608B	0x4a00
#define PRID_IMP_NETLOGIC_XLS416B	0x4400
#define PRID_IMP_NETLOGIC_XLS412B	0x4c00
#define PRID_IMP_NETLOGIC_XLS408B	0x4e00
#define PRID_IMP_NETLOGIC_XLS404B	0x4f00
#define PRID_IMP_NETLOGIC_AU13XX	0x8000

#define PRID_IMP_NETLOGIC_XLP8XX	0x1000
#define PRID_IMP_NETLOGIC_XLP3XX	0x1100
#define PRID_IMP_NETLOGIC_XLP2XX	0x1200
#define PRID_IMP_NETLOGIC_XLP9XX	0x1500
#define PRID_IMP_NETLOGIC_XLP5XX	0x1300

/*
 * Particular Revision values for bits 7:0 of the PRId register.
 */

#define PRID_REV_MASK		0x00ff

/*
 * Definitions for 7:0 on legacy processors
 */

#define PRID_REV_TX4927		0x0022
#define PRID_REV_TX4937		0x0030
#define PRID_REV_R4400		0x0040
#define PRID_REV_R3000A		0x0030
#define PRID_REV_R3000		0x0020
#define PRID_REV_R2000A		0x0010
#define PRID_REV_TX3912		0x0010
#define PRID_REV_TX3922		0x0030
#define PRID_REV_TX3927		0x0040
#define PRID_REV_VR4111		0x0050
#define PRID_REV_VR4181		0x0050	/* Same as VR4111 */
#define PRID_REV_VR4121		0x0060
#define PRID_REV_VR4122		0x0070
#define PRID_REV_VR4181A	0x0070	/* Same as VR4122 */
#define PRID_REV_VR4130		0x0080
#define PRID_REV_34K_V1_0_2	0x0022
#define PRID_REV_LOONGSON1B	0x0020
#define PRID_REV_LOONGSON2E	0x0002
#define PRID_REV_LOONGSON2F	0x0003
#define PRID_REV_LOONGSON3A_R1	0x0005
#define PRID_REV_LOONGSON3B_R1	0x0006
#define PRID_REV_LOONGSON3B_R2	0x0007
#define PRID_REV_LOONGSON3A_R2	0x0008

/*
 * Older processors used to encode processor version and revision in two
 * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
 * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
 * the patch number.  *ARGH*
 */
#define PRID_REV_ENCODE_44(ver, rev)					\
	((ver) << 4 | (rev))
#define PRID_REV_ENCODE_332(ver, rev, patch)				\
	((ver) << 5 | (rev) << 2 | (patch))

/*
 * FPU implementation/revision register (CP1 control register 0).
 *
 * +---------------------------------+----------------+----------------+
 * | 0				     | Implementation | Revision       |
 * +---------------------------------+----------------+----------------+
 *  31				   16 15	     8 7	      0
 */

#define FPIR_IMP_MASK		0xff00

#define FPIR_IMP_NONE		0x0000

#if !defined(__ASSEMBLY__)

enum cpu_type_enum {
	CPU_UNKNOWN,

	/*
	 * R2000 class processors
	 */
	CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
	CPU_R3081, CPU_R3081E,

	/*
	 * R6000 class processors
	 */
	CPU_R6000, CPU_R6000A,

	/*
	 * R4000 class processors
	 */
	CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
	CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
	CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000,
	CPU_R12000, CPU_R14000, CPU_R16000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
	CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
	CPU_SR71000, CPU_TX49XX,

	/*
	 * R8000 class processors
	 */
	CPU_R8000,

	/*
	 * TX3900 class processors
	 */
	CPU_TX3912, CPU_TX3922, CPU_TX3927,

	/*
	 * MIPS32 class processors
	 */
	CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
	CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
	CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
	CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K,
	CPU_M5150, CPU_I6400, CPU_P6600, CPU_M6250,

	/*
	 * MIPS64 class processors
	 */
	CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
	CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
	CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,

	CPU_QEMU_GENERIC,

	CPU_LAST
};

#endif /* !__ASSEMBLY */

/*
 * ISA Level encodings
 *
 */
#define MIPS_CPU_ISA_II		0x00000001
#define MIPS_CPU_ISA_III	0x00000002
#define MIPS_CPU_ISA_IV		0x00000004
#define MIPS_CPU_ISA_V		0x00000008
#define MIPS_CPU_ISA_M32R1	0x00000010
#define MIPS_CPU_ISA_M32R2	0x00000020
#define MIPS_CPU_ISA_M64R1	0x00000040
#define MIPS_CPU_ISA_M64R2	0x00000080
#define MIPS_CPU_ISA_M32R6	0x00000100
#define MIPS_CPU_ISA_M64R6	0x00000200

#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \
	MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R6)
#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
	MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \
	MIPS_CPU_ISA_M64R6)

/*
 * Private version of BIT_ULL() to escape include file recursion hell.
 * We soon will have to switch to another mechanism that will work with
 * more than 64 bits anyway.
 */
#define MBIT_ULL(bit)		(1ULL << (bit))

/*
 * CPU Option encodings
 */
#define MIPS_CPU_TLB		MBIT_ULL( 0)	/* CPU has TLB */
#define MIPS_CPU_4KEX		MBIT_ULL( 1)	/* "R4K" exception model */
#define MIPS_CPU_3K_CACHE	MBIT_ULL( 2)	/* R3000-style caches */
#define MIPS_CPU_4K_CACHE	MBIT_ULL( 3)	/* R4000-style caches */
#define MIPS_CPU_TX39_CACHE	MBIT_ULL( 4)	/* TX3900-style caches */
#define MIPS_CPU_FPU		MBIT_ULL( 5)	/* CPU has FPU */
#define MIPS_CPU_32FPR		MBIT_ULL( 6)	/* 32 dbl. prec. FP registers */
#define MIPS_CPU_COUNTER	MBIT_ULL( 7)	/* Cycle count/compare */
#define MIPS_CPU_WATCH		MBIT_ULL( 8)	/* watchpoint registers */
#define MIPS_CPU_DIVEC		MBIT_ULL( 9)	/* dedicated interrupt vector */
#define MIPS_CPU_VCE		MBIT_ULL(10)	/* virt. coherence conflict possible */
#define MIPS_CPU_CACHE_CDEX_P	MBIT_ULL(11)	/* Create_Dirty_Exclusive CACHE op */
#define MIPS_CPU_CACHE_CDEX_S	MBIT_ULL(12)	/* ... same for seconary cache ... */
#define MIPS_CPU_MCHECK		MBIT_ULL(13)	/* Machine check exception */
#define MIPS_CPU_EJTAG		MBIT_ULL(14)	/* EJTAG exception */
#define MIPS_CPU_NOFPUEX	MBIT_ULL(15)	/* no FPU exception */
#define MIPS_CPU_LLSC		MBIT_ULL(16)	/* CPU has ll/sc instructions */
#define MIPS_CPU_INCLUSIVE_CACHES	MBIT_ULL(17)	/* P-cache subset enforced */
#define MIPS_CPU_PREFETCH	MBIT_ULL(18)	/* CPU has usable prefetch */
#define MIPS_CPU_VINT		MBIT_ULL(19)	/* CPU supports MIPSR2 vectored interrupts */
#define MIPS_CPU_VEIC		MBIT_ULL(20)	/* CPU supports MIPSR2 external interrupt controller mode */
#define MIPS_CPU_ULRI		MBIT_ULL(21)	/* CPU has ULRI feature */
#define MIPS_CPU_PCI		MBIT_ULL(22)	/* CPU has Perf Ctr Int indicator */
#define MIPS_CPU_RIXI		MBIT_ULL(23)	/* CPU has TLB Read/eXec Inhibit */
#define MIPS_CPU_MICROMIPS	MBIT_ULL(24)	/* CPU has microMIPS capability */
#define MIPS_CPU_TLBINV		MBIT_ULL(25)	/* CPU supports TLBINV/F */
#define MIPS_CPU_SEGMENTS	MBIT_ULL(26)	/* CPU supports Segmentation Control registers */
#define MIPS_CPU_EVA		MBIT_ULL(27)	/* CPU supports Enhanced Virtual Addressing */
#define MIPS_CPU_HTW		MBIT_ULL(28)	/* CPU support Hardware Page Table Walker */
#define MIPS_CPU_RIXIEX		MBIT_ULL(29)	/* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
#define MIPS_CPU_MAAR		MBIT_ULL(30)	/* MAAR(I) registers are present */
#define MIPS_CPU_FRE		MBIT_ULL(31)	/* FRE & UFE bits implemented */
#define MIPS_CPU_RW_LLB		MBIT_ULL(32)	/* LLADDR/LLB writes are allowed */
#define MIPS_CPU_LPA		MBIT_ULL(33)	/* CPU supports Large Physical Addressing */
#define MIPS_CPU_CDMM		MBIT_ULL(34)	/* CPU has Common Device Memory Map */
#define MIPS_CPU_BP_GHIST	MBIT_ULL(35)	/* R12K+ Branch Prediction Global History */
#define MIPS_CPU_SP		MBIT_ULL(36)	/* Small (1KB) page support */
#define MIPS_CPU_FTLB		MBIT_ULL(37)	/* CPU has Fixed-page-size TLB */
#define MIPS_CPU_NAN_LEGACY	MBIT_ULL(38)	/* Legacy NaN implemented */
#define MIPS_CPU_NAN_2008	MBIT_ULL(39)	/* 2008 NaN implemented */
#define MIPS_CPU_VP		MBIT_ULL(40)	/* MIPSr6 Virtual Processors (multi-threading) */
#define MIPS_CPU_LDPTE		MBIT_ULL(41)	/* CPU has ldpte/lddir instructions */
#define MIPS_CPU_MVH		MBIT_ULL(42)	/* CPU supports MFHC0/MTHC0 */
#define MIPS_CPU_EBASE_WG	MBIT_ULL(43)	/* CPU has EBase.WG */
#define MIPS_CPU_BADINSTR	MBIT_ULL(44)	/* CPU has BadInstr register */
#define MIPS_CPU_BADINSTRP	MBIT_ULL(45)	/* CPU has BadInstrP register */
#define MIPS_CPU_CTXTC		MBIT_ULL(46)	/* CPU has [X]ConfigContext registers */
#define MIPS_CPU_PERF		MBIT_ULL(47)	/* CPU has MIPS performance counters */
#define MIPS_CPU_GUESTCTL0EXT	MBIT_ULL(48)	/* CPU has VZ GuestCtl0Ext register */
#define MIPS_CPU_GUESTCTL1	MBIT_ULL(49)	/* CPU has VZ GuestCtl1 register */
#define MIPS_CPU_GUESTCTL2	MBIT_ULL(50)	/* CPU has VZ GuestCtl2 register */
#define MIPS_CPU_GUESTID	MBIT_ULL(51)	/* CPU uses VZ ASE GuestID feature */
#define MIPS_CPU_DRG		MBIT_ULL(52)	/* CPU has VZ Direct Root to Guest (DRG) */

/*
 * CPU ASE encodings
 */
#define MIPS_ASE_MIPS16		0x00000001 /* code compression */
#define MIPS_ASE_MDMX		0x00000002 /* MIPS digital media extension */
#define MIPS_ASE_MIPS3D		0x00000004 /* MIPS-3D */
#define MIPS_ASE_SMARTMIPS	0x00000008 /* SmartMIPS */
#define MIPS_ASE_DSP		0x00000010 /* Signal Processing ASE */
#define MIPS_ASE_MIPSMT		0x00000020 /* CPU supports MIPS MT */
#define MIPS_ASE_DSP2P		0x00000040 /* Signal Processing ASE Rev 2 */
#define MIPS_ASE_VZ		0x00000080 /* Virtualization ASE */
#define MIPS_ASE_MSA		0x00000100 /* MIPS SIMD Architecture */
#define MIPS_ASE_DSP3		0x00000200 /* Signal Processing ASE Rev 3*/

#endif /* _ASM_CPU_H */
Commit	Line	Data
1da177e4 LT	1	/*
1da177e4 LT	2	* cpu.h: Values of the PRId register used to match up
70342287	3	* various MIPS cpu types.
1da177e4	4	*
79add627	5	* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
8ff374b9	6	* Copyright (C) 2004, 2013 Maciej W. Rozycki
1da177e4 LT	7	*/
	8	#ifndef _ASM_CPU_H
	9	#define _ASM_CPU_H
	10
8ff374b9 MR	11	/*
	12	As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0
	13	register 15, select 0) is defined in this (backwards compatible) way:
1da177e4 LT	14
1da177e4 LT	15	+----------------+----------------+----------------+----------------+
70342287	16	\| Company Options\| Company ID \| Processor ID \| Revision \|
1da177e4	17	+----------------+----------------+----------------+----------------+
70342287	18	31 24 23 16 15 8 7
1da177e4 LT	19
	20	I don't have docs for all the previous processors, but my impression is
	21	that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
	22	spec.
	23	*/
	24
8ff374b9 MR	25	#define PRID_OPT_MASK 0xff000000
	26
	27	/*
	28	* Assigned Company values for bits 23:16 of the PRId register.
	29	*/
	30
	31	#define PRID_COMP_MASK 0xff0000
	32
55a6feb6 RB	33	#define PRID_COMP_LEGACY 0x000000
	34	#define PRID_COMP_MIPS 0x010000
	35	#define PRID_COMP_BROADCOM 0x020000
	36	#define PRID_COMP_ALCHEMY 0x030000
	37	#define PRID_COMP_SIBYTE 0x040000
	38	#define PRID_COMP_SANDCRAFT 0x050000
70342287	39	#define PRID_COMP_NXP 0x060000
55a6feb6 RB	40	#define PRID_COMP_TOSHIBA 0x070000
	41	#define PRID_COMP_LSI 0x080000
	42	#define PRID_COMP_LEXRA 0x0b0000
a7117c6b	43	#define PRID_COMP_NETLOGIC 0x0c0000
0dd4781b	44	#define PRID_COMP_CAVIUM 0x0d0000
b2edcfc8	45	#define PRID_COMP_LOONGSON 0x140000
252617a4 PB	46	#define PRID_COMP_INGENIC_D0 0xd00000 /* JZ4740, JZ4750 */
	47	#define PRID_COMP_INGENIC_D1 0xd10000 /* JZ4770, JZ4775 */
	48	#define PRID_COMP_INGENIC_E1 0xe10000 /* JZ4780 */
1da177e4 LT	49
1da177e4 LT	50	/*
8ff374b9 MR	51	* Assigned Processor ID (implementation) values for bits 15:8 of the PRId
	52	* register. In order to detect a certain CPU type exactly eventually
	53	* additional registers may need to be examined.
1da177e4	54	*/
8ff374b9 MR	55
	56	#define PRID_IMP_MASK 0xff00
	57
	58	/*
	59	* These are valid when 23:16 == PRID_COMP_LEGACY
	60	*/
	61
1da177e4 LT	62	#define PRID_IMP_R2000 0x0100
	63	#define PRID_IMP_AU1_REV1 0x0100
	64	#define PRID_IMP_AU1_REV2 0x0200
	65	#define PRID_IMP_R3000 0x0200 /* Same as R2000A */
	66	#define PRID_IMP_R6000 0x0300 /* Same as R3000A */
	67	#define PRID_IMP_R4000 0x0400
	68	#define PRID_IMP_R6000A 0x0600
	69	#define PRID_IMP_R10000 0x0900
	70	#define PRID_IMP_R4300 0x0b00
	71	#define PRID_IMP_VR41XX 0x0c00
	72	#define PRID_IMP_R12000 0x0e00
30577391	73	#define PRID_IMP_R14000 0x0f00 /* R14K && R16K */
1da177e4	74	#define PRID_IMP_R8000 0x1000
bdf21b18	75	#define PRID_IMP_PR4450 0x1200
1da177e4 LT	76	#define PRID_IMP_R4600 0x2000
	77	#define PRID_IMP_R4700 0x2100
	78	#define PRID_IMP_TX39 0x2200
	79	#define PRID_IMP_R4640 0x2200
	80	#define PRID_IMP_R4650 0x2200 /* Same as R4640 */
	81	#define PRID_IMP_R5000 0x2300
	82	#define PRID_IMP_TX49 0x2d00
	83	#define PRID_IMP_SONIC 0x2400
	84	#define PRID_IMP_MAGIC 0x2500
	85	#define PRID_IMP_RM7000 0x2700
	86	#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
	87	#define PRID_IMP_RM9000 0x3400
26859198	88	#define PRID_IMP_LOONGSON_32 0x4200 /* Loongson-1 */
1da177e4 LT	89	#define PRID_IMP_R5432 0x5400
1da177e4 LT	90	#define PRID_IMP_R5500 0x5500
26859198	91	#define PRID_IMP_LOONGSON_64 0x6300 /* Loongson-2/3 */
98e316d4 MR	92
	93	#define PRID_IMP_UNKNOWN 0xff00
	94
	95	/*
	96	* These are the PRID's for when 23:16 == PRID_COMP_MIPS
	97	*/
	98
aca5721e	99	#define PRID_IMP_QEMU_GENERIC 0x0000
1da177e4 LT	100	#define PRID_IMP_4KC 0x8000
	101	#define PRID_IMP_5KC 0x8100
	102	#define PRID_IMP_20KC 0x8200
	103	#define PRID_IMP_4KEC 0x8400
	104	#define PRID_IMP_4KSC 0x8600
	105	#define PRID_IMP_25KF 0x8800
	106	#define PRID_IMP_5KE 0x8900
	107	#define PRID_IMP_4KECR2 0x9000
	108	#define PRID_IMP_4KEMPR2 0x9100
	109	#define PRID_IMP_4KSD 0x9200
	110	#define PRID_IMP_24K 0x9300
bbc7f22f	111	#define PRID_IMP_34K 0x9500
e50c0a8f	112	#define PRID_IMP_24KE 0x9600
c620953c	113	#define PRID_IMP_74K 0x9700
39b8d525	114	#define PRID_IMP_1004K 0x9900
006a851b	115	#define PRID_IMP_1074K 0x9a00
113c62d9	116	#define PRID_IMP_M14KC 0x9c00
f8fa4811	117	#define PRID_IMP_M14KEC 0x9e00
0ce7d58e LY	118	#define PRID_IMP_INTERAPTIV_UP 0xa000
0ce7d58e LY	119	#define PRID_IMP_INTERAPTIV_MP 0xa100
76f59e32 LY	120	#define PRID_IMP_PROAPTIV_UP 0xa200
76f59e32 LY	121	#define PRID_IMP_PROAPTIV_MP 0xa300
5cd0d5be	122	#define PRID_IMP_P6600 0xa400
4975b86a	123	#define PRID_IMP_M5150 0xa700
f43e4dfd	124	#define PRID_IMP_P5600 0xa800
90b8baa2	125	#define PRID_IMP_I6400 0xa900
df8b1a5e	126	#define PRID_IMP_M6250 0xab00
1da177e4	127
1da177e4 LT	128	/*
	129	* These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
	130	*/
	131
70342287 RB	132	#define PRID_IMP_SB1 0x0100
70342287 RB	133	#define PRID_IMP_SB1A 0x1100
1da177e4 LT	134
	135	/*
	136	* These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
	137	*/
	138
70342287	139	#define PRID_IMP_SR71000 0x0400
1da177e4	140
1c0c13eb AJ	141	/*
	142	* These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
	143	*/
	144
190fca3e KC	145	#define PRID_IMP_BMIPS32_REV4 0x4000
190fca3e KC	146	#define PRID_IMP_BMIPS32_REV8 0x8000
602977b0 KC	147	#define PRID_IMP_BMIPS3300 0x9000
	148	#define PRID_IMP_BMIPS3300_ALT 0x9100
	149	#define PRID_IMP_BMIPS3300_BUG 0x0000
	150	#define PRID_IMP_BMIPS43XX 0xa000
	151	#define PRID_IMP_BMIPS5000 0x5a00
68e6a783	152	#define PRID_IMP_BMIPS5200 0x5b00
602977b0 KC	153
	154	#define PRID_REV_BMIPS4380_LO 0x0040
	155	#define PRID_REV_BMIPS4380_HI 0x006f
1c0c13eb	156
0dd4781b DD	157	/*
	158	* These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
	159	*/
	160
	161	#define PRID_IMP_CAVIUM_CN38XX 0x0000
	162	#define PRID_IMP_CAVIUM_CN31XX 0x0100
	163	#define PRID_IMP_CAVIUM_CN30XX 0x0200
	164	#define PRID_IMP_CAVIUM_CN58XX 0x0300
	165	#define PRID_IMP_CAVIUM_CN56XX 0x0400
	166	#define PRID_IMP_CAVIUM_CN50XX 0x0600
	167	#define PRID_IMP_CAVIUM_CN52XX 0x0700
1584d7f2	168	#define PRID_IMP_CAVIUM_CN63XX 0x9000
074ef0d2 DD	169	#define PRID_IMP_CAVIUM_CN68XX 0x9100
	170	#define PRID_IMP_CAVIUM_CN66XX 0x9200
	171	#define PRID_IMP_CAVIUM_CN61XX 0x9300
71a8b7d8 DD	172	#define PRID_IMP_CAVIUM_CNF71XX 0x9400
	173	#define PRID_IMP_CAVIUM_CN78XX 0x9500
	174	#define PRID_IMP_CAVIUM_CN70XX 0x9600
b8c8f665 DD	175	#define PRID_IMP_CAVIUM_CN73XX 0x9700
b8c8f665 DD	176	#define PRID_IMP_CAVIUM_CNF75XX 0x9800
0dd4781b	177
83ccf69d	178	/*
252617a4	179	* These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
83ccf69d LPC	180	*/
83ccf69d LPC	181
70342287	182	#define PRID_IMP_JZRISC 0x0200
83ccf69d	183
a7117c6b J	184	/*
	185	* These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
	186	*/
	187	#define PRID_IMP_NETLOGIC_XLR732 0x0000
	188	#define PRID_IMP_NETLOGIC_XLR716 0x0200
	189	#define PRID_IMP_NETLOGIC_XLR532 0x0900
	190	#define PRID_IMP_NETLOGIC_XLR308 0x0600
	191	#define PRID_IMP_NETLOGIC_XLR532C 0x0800
	192	#define PRID_IMP_NETLOGIC_XLR516C 0x0a00
	193	#define PRID_IMP_NETLOGIC_XLR508C 0x0b00
	194	#define PRID_IMP_NETLOGIC_XLR308C 0x0f00
	195	#define PRID_IMP_NETLOGIC_XLS608 0x8000
	196	#define PRID_IMP_NETLOGIC_XLS408 0x8800
	197	#define PRID_IMP_NETLOGIC_XLS404 0x8c00
	198	#define PRID_IMP_NETLOGIC_XLS208 0x8e00
	199	#define PRID_IMP_NETLOGIC_XLS204 0x8f00
	200	#define PRID_IMP_NETLOGIC_XLS108 0xce00
	201	#define PRID_IMP_NETLOGIC_XLS104 0xcf00
	202	#define PRID_IMP_NETLOGIC_XLS616B 0x4000
	203	#define PRID_IMP_NETLOGIC_XLS608B 0x4a00
	204	#define PRID_IMP_NETLOGIC_XLS416B 0x4400
	205	#define PRID_IMP_NETLOGIC_XLS412B 0x4c00
	206	#define PRID_IMP_NETLOGIC_XLS408B 0x4e00
	207	#define PRID_IMP_NETLOGIC_XLS404B 0x4f00
809f36c6	208	#define PRID_IMP_NETLOGIC_AU13XX 0x8000
a7117c6b	209
2aa54b20 J	210	#define PRID_IMP_NETLOGIC_XLP8XX 0x1000
2aa54b20 J	211	#define PRID_IMP_NETLOGIC_XLP3XX 0x1100
4ca86a2f	212	#define PRID_IMP_NETLOGIC_XLP2XX 0x1200
8907c55e	213	#define PRID_IMP_NETLOGIC_XLP9XX 0x1500
1c983986	214	#define PRID_IMP_NETLOGIC_XLP5XX 0x1300
a7117c6b	215
1da177e4	216	/*
8ff374b9	217	* Particular Revision values for bits 7:0 of the PRId register.
1da177e4 LT	218	*/
1da177e4 LT	219
9267a30d	220	#define PRID_REV_MASK 0x00ff
1da177e4	221
8ff374b9 MR	222	/*
	223	* Definitions for 7:0 on legacy processors
	224	*/
	225
1da177e4 LT	226	#define PRID_REV_TX4927 0x0022
	227	#define PRID_REV_TX4937 0x0030
	228	#define PRID_REV_R4400 0x0040
	229	#define PRID_REV_R3000A 0x0030
	230	#define PRID_REV_R3000 0x0020
	231	#define PRID_REV_R2000A 0x0010
70342287 RB	232	#define PRID_REV_TX3912 0x0010
	233	#define PRID_REV_TX3922 0x0030
	234	#define PRID_REV_TX3927 0x0040
1da177e4 LT	235	#define PRID_REV_VR4111 0x0050
	236	#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */
	237	#define PRID_REV_VR4121 0x0060
	238	#define PRID_REV_VR4122 0x0070
	239	#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
	240	#define PRID_REV_VR4130 0x0080
9267a30d	241	#define PRID_REV_34K_V1_0_2 0x0022
2fa36399	242	#define PRID_REV_LOONGSON1B 0x0020
f8ede0f7 WZ	243	#define PRID_REV_LOONGSON2E 0x0002
f8ede0f7 WZ	244	#define PRID_REV_LOONGSON2F 0x0003
b2edcfc8	245	#define PRID_REV_LOONGSON3A_R1 0x0005
e7841be5 HC	246	#define PRID_REV_LOONGSON3B_R1 0x0006
e7841be5 HC	247	#define PRID_REV_LOONGSON3B_R2 0x0007
b2edcfc8	248	#define PRID_REV_LOONGSON3A_R2 0x0008
1da177e4	249
fde97822 RB	250	/*
	251	* Older processors used to encode processor version and revision in two
	252	* 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
	253	* have switched to use the 8-bits as 3:3:2 bitfield with the last field as
	254	* the patch number. ARGH
	255	*/
	256	#define PRID_REV_ENCODE_44(ver, rev) \
	257	((ver) << 4 \| (rev))
	258	#define PRID_REV_ENCODE_332(ver, rev, patch) \
	259	((ver) << 5 \| (rev) << 2 \| (patch))
	260
1da177e4 LT	261	/*
	262	* FPU implementation/revision register (CP1 control register 0).
	263	*
	264	* +---------------------------------+----------------+----------------+
70342287	265	* \| 0 \| Implementation \| Revision \|
1da177e4	266	* +---------------------------------+----------------+----------------+
70342287	267	* 31 16 15 8 7 0
1da177e4 LT	268	*/
1da177e4 LT	269
8ff374b9 MR	270	#define FPIR_IMP_MASK 0xff00
8ff374b9 MR	271
1da177e4 LT	272	#define FPIR_IMP_NONE 0x0000
1da177e4 LT	273
68248d0c JG	274	#if !defined(__ASSEMBLY__)
68248d0c JG	275
36cfbaad RB	276	enum cpu_type_enum {
	277	CPU_UNKNOWN,
	278
	279	/*
	280	* R2000 class processors
	281	*/
	282	CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
	283	CPU_R3081, CPU_R3081E,
	284
	285	/*
	286	* R6000 class processors
	287	*/
	288	CPU_R6000, CPU_R6000A,
	289
	290	/*
	291	* R4000 class processors
	292	*/
	293	CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
	294	CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
fb2b1dba	295	CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000,
30577391 JK	296	CPU_R12000, CPU_R14000, CPU_R16000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
30577391 JK	297	CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
321b1863	298	CPU_SR71000, CPU_TX49XX,
36cfbaad RB	299
	300	/*
	301	* R8000 class processors
	302	*/
	303	CPU_R8000,
	304
	305	/*
	306	* TX3900 class processors
	307	*/
	308	CPU_TX3912, CPU_TX3922, CPU_TX3927,
	309
	310	/*
	311	* MIPS32 class processors
	312	*/
39b8d525	313	CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
602977b0	314	CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
2fa36399	315	CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
bff3d472	316	CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K,
df8b1a5e	317	CPU_M5150, CPU_I6400, CPU_P6600, CPU_M6250,
36cfbaad RB	318
	319	/*
	320	* MIPS64 class processors
	321	*/
78d4803f	322	CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
152ebb44 HC	323	CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
152ebb44 HC	324	CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,
36cfbaad	325
aca5721e LY	326	CPU_QEMU_GENERIC,
aca5721e LY	327
36cfbaad RB	328	CPU_LAST
	329	};
	330
68248d0c	331	#endif /* !__ASSEMBLY */
1da177e4 LT	332
	333	/*
	334	* ISA Level encodings
	335	*
	336	*/
1990e542 RB	337	#define MIPS_CPU_ISA_II 0x00000001
	338	#define MIPS_CPU_ISA_III 0x00000002
	339	#define MIPS_CPU_ISA_IV 0x00000004
	340	#define MIPS_CPU_ISA_V 0x00000008
	341	#define MIPS_CPU_ISA_M32R1 0x00000010
	342	#define MIPS_CPU_ISA_M32R2 0x00000020
	343	#define MIPS_CPU_ISA_M64R1 0x00000040
	344	#define MIPS_CPU_ISA_M64R2 0x00000080
34c56fc1 LY	345	#define MIPS_CPU_ISA_M32R6 0x00000100
34c56fc1 LY	346	#define MIPS_CPU_ISA_M64R6 0x00000200
1990e542 RB	347
1990e542 RB	348	#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II \| MIPS_CPU_ISA_M32R1 \| \
34c56fc1	349	MIPS_CPU_ISA_M32R2 \| MIPS_CPU_ISA_M32R6)
0401572a	350	#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III \| MIPS_CPU_ISA_IV \| \
34c56fc1 LY	351	MIPS_CPU_ISA_V \| MIPS_CPU_ISA_M64R1 \| MIPS_CPU_ISA_M64R2 \| \
34c56fc1 LY	352	MIPS_CPU_ISA_M64R6)
1da177e4	353
0c94fa33 JH	354	/*
	355	* Private version of BIT_ULL() to escape include file recursion hell.
	356	* We soon will have to switch to another mechanism that will work with
	357	* more than 64 bits anyway.
	358	*/
	359	#define MBIT_ULL(bit) (1ULL << (bit))
	360
1da177e4 LT	361	/*
	362	* CPU Option encodings
	363	*/
0c94fa33 JH	364	#define MIPS_CPU_TLB MBIT_ULL( 0) /* CPU has TLB */
	365	#define MIPS_CPU_4KEX MBIT_ULL( 1) /* "R4K" exception model */
	366	#define MIPS_CPU_3K_CACHE MBIT_ULL( 2) /* R3000-style caches */
	367	#define MIPS_CPU_4K_CACHE MBIT_ULL( 3) /* R4000-style caches */
	368	#define MIPS_CPU_TX39_CACHE MBIT_ULL( 4) /* TX3900-style caches */
	369	#define MIPS_CPU_FPU MBIT_ULL( 5) /* CPU has FPU */
	370	#define MIPS_CPU_32FPR MBIT_ULL( 6) /* 32 dbl. prec. FP registers */
	371	#define MIPS_CPU_COUNTER MBIT_ULL( 7) /* Cycle count/compare */
	372	#define MIPS_CPU_WATCH MBIT_ULL( 8) /* watchpoint registers */
	373	#define MIPS_CPU_DIVEC MBIT_ULL( 9) /* dedicated interrupt vector */
	374	#define MIPS_CPU_VCE MBIT_ULL(10) /* virt. coherence conflict possible */
	375	#define MIPS_CPU_CACHE_CDEX_P MBIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */
	376	#define MIPS_CPU_CACHE_CDEX_S MBIT_ULL(12) /* ... same for seconary cache ... */
	377	#define MIPS_CPU_MCHECK MBIT_ULL(13) /* Machine check exception */
	378	#define MIPS_CPU_EJTAG MBIT_ULL(14) /* EJTAG exception */
	379	#define MIPS_CPU_NOFPUEX MBIT_ULL(15) /* no FPU exception */
	380	#define MIPS_CPU_LLSC MBIT_ULL(16) /* CPU has ll/sc instructions */
	381	#define MIPS_CPU_INCLUSIVE_CACHES MBIT_ULL(17) /* P-cache subset enforced */
	382	#define MIPS_CPU_PREFETCH MBIT_ULL(18) /* CPU has usable prefetch */
	383	#define MIPS_CPU_VINT MBIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */
	384	#define MIPS_CPU_VEIC MBIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */
	385	#define MIPS_CPU_ULRI MBIT_ULL(21) /* CPU has ULRI feature */
	386	#define MIPS_CPU_PCI MBIT_ULL(22) /* CPU has Perf Ctr Int indicator */
	387	#define MIPS_CPU_RIXI MBIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */
	388	#define MIPS_CPU_MICROMIPS MBIT_ULL(24) /* CPU has microMIPS capability */
	389	#define MIPS_CPU_TLBINV MBIT_ULL(25) /* CPU supports TLBINV/F */
	390	#define MIPS_CPU_SEGMENTS MBIT_ULL(26) /* CPU supports Segmentation Control registers */
	391	#define MIPS_CPU_EVA MBIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */
	392	#define MIPS_CPU_HTW MBIT_ULL(28) /* CPU support Hardware Page Table Walker */
	393	#define MIPS_CPU_RIXIEX MBIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
	394	#define MIPS_CPU_MAAR MBIT_ULL(30) /* MAAR(I) registers are present */
	395	#define MIPS_CPU_FRE MBIT_ULL(31) /* FRE & UFE bits implemented */
	396	#define MIPS_CPU_RW_LLB MBIT_ULL(32) /* LLADDR/LLB writes are allowed */
12822570	397	#define MIPS_CPU_LPA MBIT_ULL(33) /* CPU supports Large Physical Addressing */
0c94fa33 JH	398	#define MIPS_CPU_CDMM MBIT_ULL(34) /* CPU has Common Device Memory Map */
	399	#define MIPS_CPU_BP_GHIST MBIT_ULL(35) /* R12K+ Branch Prediction Global History */
	400	#define MIPS_CPU_SP MBIT_ULL(36) /* Small (1KB) page support */
	401	#define MIPS_CPU_FTLB MBIT_ULL(37) /* CPU has Fixed-page-size TLB */
	402	#define MIPS_CPU_NAN_LEGACY MBIT_ULL(38) /* Legacy NaN implemented */
	403	#define MIPS_CPU_NAN_2008 MBIT_ULL(39) /* 2008 NaN implemented */
	404	#define MIPS_CPU_VP MBIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */
380cd582	405	#define MIPS_CPU_LDPTE MBIT_ULL(41) /* CPU has ldpte/lddir instructions */
12822570	406	#define MIPS_CPU_MVH MBIT_ULL(42) /* CPU supports MFHC0/MTHC0 */
37fb60f8	407	#define MIPS_CPU_EBASE_WG MBIT_ULL(43) /* CPU has EBase.WG */
e06a1548 JH	408	#define MIPS_CPU_BADINSTR MBIT_ULL(44) /* CPU has BadInstr register */
e06a1548 JH	409	#define MIPS_CPU_BADINSTRP MBIT_ULL(45) /* CPU has BadInstrP register */
f18bdfa1	410	#define MIPS_CPU_CTXTC MBIT_ULL(46) /* CPU has [X]ConfigContext registers */
30228c40	411	#define MIPS_CPU_PERF MBIT_ULL(47) /* CPU has MIPS performance counters */
6ad816e7 JH	412	#define MIPS_CPU_GUESTCTL0EXT MBIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */
	413	#define MIPS_CPU_GUESTCTL1 MBIT_ULL(49) /* CPU has VZ GuestCtl1 register */
	414	#define MIPS_CPU_GUESTCTL2 MBIT_ULL(50) /* CPU has VZ GuestCtl2 register */
	415	#define MIPS_CPU_GUESTID MBIT_ULL(51) /* CPU uses VZ ASE GuestID feature */
	416	#define MIPS_CPU_DRG MBIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */
1da177e4	417
4194318c RB	418	/*
	419	* CPU ASE encodings
	420	*/
	421	#define MIPS_ASE_MIPS16 0x00000001 /* code compression */
	422	#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */
	423	#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */
	424	#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */
e50c0a8f	425	#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
8f40611d	426	#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
ee80f7c7	427	#define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */
1e7decdb	428	#define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */
a5e9a69e	429	#define MIPS_ASE_MSA 0x00000100 /* MIPS SIMD Architecture */
b5a6455c	430	#define MIPS_ASE_DSP3 0x00000200 /* Signal Processing ASE Rev 3*/
4194318c	431
1da177e4	432	#endif /* _ASM_CPU_H */