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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1994 Waldorf GMBH | |
7 | * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle | |
8 | * Copyright (C) 1996 Paul M. Antoine | |
9 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. | |
4194318c | 10 | * Copyright (C) 2004 Maciej W. Rozycki |
1da177e4 LT |
11 | */ |
12 | #ifndef __ASM_CPU_INFO_H | |
13 | #define __ASM_CPU_INFO_H | |
14 | ||
6aa3524c DD |
15 | #include <linux/types.h> |
16 | ||
1da177e4 LT |
17 | #include <asm/cache.h> |
18 | ||
1da177e4 LT |
19 | /* |
20 | * Descriptor for a cache | |
21 | */ | |
22 | struct cache_desc { | |
1da177e4 | 23 | unsigned int waysize; /* Bytes per way */ |
6f2c3fa0 RB |
24 | unsigned short sets; /* Number of lines per set */ |
25 | unsigned char ways; /* Number of ways */ | |
26 | unsigned char linesz; /* Size of line in bytes */ | |
27 | unsigned char waybit; /* Bits to select in a cache set */ | |
28 | unsigned char flags; /* Flags describing cache properties */ | |
1da177e4 LT |
29 | }; |
30 | ||
31 | /* | |
32 | * Flag definitions | |
33 | */ | |
34 | #define MIPS_CACHE_NOT_PRESENT 0x00000001 | |
35 | #define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */ | |
36 | #define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */ | |
37 | #define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */ | |
38 | #define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */ | |
de62893b | 39 | #define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */ |
1da177e4 LT |
40 | |
41 | struct cpuinfo_mips { | |
e5eb925a | 42 | unsigned long asid_cache; |
2db003a5 PB |
43 | #ifdef CONFIG_MIPS_ASID_BITS_VARIABLE |
44 | unsigned long asid_mask; | |
45 | #endif | |
1da177e4 LT |
46 | |
47 | /* | |
48 | * Capability and feature descriptor structure for MIPS CPU | |
49 | */ | |
4194318c | 50 | unsigned long ases; |
03a58777 | 51 | unsigned long long options; |
e5eb925a | 52 | unsigned int udelay_val; |
1da177e4 LT |
53 | unsigned int processor_id; |
54 | unsigned int fpu_id; | |
9b26616c MR |
55 | unsigned int fpu_csr31; |
56 | unsigned int fpu_msk31; | |
a5e9a69e | 57 | unsigned int msa_id; |
1da177e4 LT |
58 | unsigned int cputype; |
59 | int isa_level; | |
60 | int tlbsize; | |
75b5b5e0 LY |
61 | int tlbsizevtlb; |
62 | int tlbsizeftlbsets; | |
63 | int tlbsizeftlbways; | |
70342287 RB |
64 | struct cache_desc icache; /* Primary I-cache */ |
65 | struct cache_desc dcache; /* Primary D or combined I/D cache */ | |
b2edcfc8 | 66 | struct cache_desc vcache; /* Victim cache, between pcache and scache */ |
70342287 RB |
67 | struct cache_desc scache; /* Secondary cache */ |
68 | struct cache_desc tcache; /* Tertiary/split secondary cache */ | |
69 | int srsets; /* Shadow register sets */ | |
bda4584c | 70 | int package;/* physical package number */ |
0ab7aefc | 71 | int core; /* physical core number */ |
91dfc423 | 72 | #ifdef CONFIG_64BIT |
70342287 | 73 | int vmbits; /* Virtual memory size in bits */ |
91dfc423 | 74 | #endif |
5a3e7c02 | 75 | #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6) |
41c594ab | 76 | /* |
b633648c RB |
77 | * There is not necessarily a 1:1 mapping of VPE num to CPU number |
78 | * in particular on multi-core systems. | |
41c594ab | 79 | */ |
70342287 | 80 | int vpe_id; /* Virtual Processor number */ |
0ab7aefc | 81 | #endif |
70342287 | 82 | void *data; /* Additional data */ |
6aa3524c DD |
83 | unsigned int watch_reg_count; /* Number that exist */ |
84 | unsigned int watch_reg_use_cnt; /* Usable by ptrace */ | |
85 | #define NUM_WATCH_REGS 4 | |
86 | u16 watch_reg_masks[NUM_WATCH_REGS]; | |
e77c32fe | 87 | unsigned int kscratch_mask; /* Usable KScratch mask. */ |
4f12b91d MC |
88 | /* |
89 | * Cache Coherency attribute for write-combine memory writes. | |
90 | * (shifted by _CACHE_SHIFT) | |
91 | */ | |
92 | unsigned int writecombine; | |
ed4cbc81 MC |
93 | /* |
94 | * Simple counter to prevent enabling HTW in nested | |
95 | * htw_start/htw_stop calls | |
96 | */ | |
97 | unsigned int htw_seq; | |
1da177e4 LT |
98 | } __attribute__((aligned(SMP_CACHE_BYTES))); |
99 | ||
100 | extern struct cpuinfo_mips cpu_data[]; | |
101 | #define current_cpu_data cpu_data[smp_processor_id()] | |
53dc8028 | 102 | #define raw_current_cpu_data cpu_data[raw_smp_processor_id()] |
c5f66596 | 103 | #define boot_cpu_data cpu_data[0] |
1da177e4 LT |
104 | |
105 | extern void cpu_probe(void); | |
106 | extern void cpu_report(void); | |
107 | ||
9966db25 | 108 | extern const char *__cpu_name[]; |
e95008a1 | 109 | #define cpu_name_string() __cpu_name[raw_smp_processor_id()] |
9966db25 | 110 | |
d6d3c9af RB |
111 | struct seq_file; |
112 | struct notifier_block; | |
113 | ||
114 | extern int register_proc_cpuinfo_notifier(struct notifier_block *nb); | |
115 | extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v); | |
116 | ||
117 | #define proc_cpuinfo_notifier(fn, pri) \ | |
118 | ({ \ | |
119 | static struct notifier_block fn##_nb = { \ | |
120 | .notifier_call = fn, \ | |
121 | .priority = pri \ | |
122 | }; \ | |
123 | \ | |
124 | register_proc_cpuinfo_notifier(&fn##_nb); \ | |
125 | }) | |
126 | ||
127 | struct proc_cpuinfo_notifier_args { | |
128 | struct seq_file *m; | |
129 | unsigned long n; | |
130 | }; | |
131 | ||
5a3e7c02 | 132 | #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6) |
b86c2247 PB |
133 | # define cpu_vpe_id(cpuinfo) ((cpuinfo)->vpe_id) |
134 | #else | |
34bd3e6b | 135 | # define cpu_vpe_id(cpuinfo) ({ (void)cpuinfo; 0; }) |
b86c2247 PB |
136 | #endif |
137 | ||
4edf00a4 PB |
138 | static inline unsigned long cpu_asid_inc(void) |
139 | { | |
140 | return 1 << CONFIG_MIPS_ASID_SHIFT; | |
141 | } | |
142 | ||
143 | static inline unsigned long cpu_asid_mask(struct cpuinfo_mips *cpuinfo) | |
144 | { | |
2db003a5 PB |
145 | #ifdef CONFIG_MIPS_ASID_BITS_VARIABLE |
146 | return cpuinfo->asid_mask; | |
147 | #endif | |
4edf00a4 PB |
148 | return ((1 << CONFIG_MIPS_ASID_BITS) - 1) << CONFIG_MIPS_ASID_SHIFT; |
149 | } | |
150 | ||
2db003a5 PB |
151 | static inline void set_cpu_asid_mask(struct cpuinfo_mips *cpuinfo, |
152 | unsigned long asid_mask) | |
153 | { | |
154 | #ifdef CONFIG_MIPS_ASID_BITS_VARIABLE | |
155 | cpuinfo->asid_mask = asid_mask; | |
156 | #endif | |
157 | } | |
158 | ||
1da177e4 | 159 | #endif /* __ASM_CPU_INFO_H */ |