Commit | Line | Data |
---|---|---|
b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
484d83b3 ÁFR |
2 | / { |
3 | #address-cells = <1>; | |
4 | #size-cells = <1>; | |
5 | compatible = "brcm,bcm3368"; | |
6 | ||
7 | cpus { | |
8 | #address-cells = <1>; | |
9 | #size-cells = <0>; | |
10 | ||
11 | mips-hpt-frequency = <150000000>; | |
12 | ||
13 | cpu@0 { | |
14 | compatible = "brcm,bmips4350"; | |
15 | device_type = "cpu"; | |
16 | reg = <0>; | |
17 | }; | |
18 | ||
19 | cpu@1 { | |
20 | compatible = "brcm,bmips4350"; | |
21 | device_type = "cpu"; | |
22 | reg = <1>; | |
23 | }; | |
24 | }; | |
25 | ||
26 | clocks { | |
27 | periph_clk: periph-clk { | |
28 | compatible = "fixed-clock"; | |
29 | #clock-cells = <0>; | |
30 | clock-frequency = <50000000>; | |
31 | }; | |
32 | }; | |
33 | ||
34 | aliases { | |
35 | serial0 = &uart0; | |
36 | serial1 = &uart1; | |
37 | }; | |
38 | ||
39 | cpu_intc: interrupt-controller { | |
40 | #address-cells = <0>; | |
41 | compatible = "mti,cpu-interrupt-controller"; | |
42 | ||
43 | interrupt-controller; | |
44 | #interrupt-cells = <1>; | |
45 | }; | |
46 | ||
47 | ubus { | |
48 | #address-cells = <1>; | |
49 | #size-cells = <1>; | |
50 | ||
51 | compatible = "simple-bus"; | |
52 | ranges; | |
53 | ||
54 | periph_cntl: syscon@fff8c000 { | |
55 | compatible = "syscon"; | |
56 | reg = <0xfff8c000 0xc>; | |
57 | native-endian; | |
58 | }; | |
59 | ||
60 | reboot: syscon-reboot@fff8c008 { | |
61 | compatible = "syscon-reboot"; | |
62 | regmap = <&periph_cntl>; | |
63 | offset = <0x8>; | |
64 | mask = <0x1>; | |
65 | }; | |
66 | ||
67 | periph_intc: interrupt-controller@fff8c00c { | |
68 | compatible = "brcm,bcm6345-l1-intc"; | |
69 | reg = <0xfff8c00c 0x8>; | |
70 | ||
71 | interrupt-controller; | |
72 | #interrupt-cells = <1>; | |
73 | ||
74 | interrupt-parent = <&cpu_intc>; | |
75 | interrupts = <2>; | |
76 | }; | |
77 | ||
78 | uart0: serial@fff8c100 { | |
79 | compatible = "brcm,bcm6345-uart"; | |
80 | reg = <0xfff8c100 0x18>; | |
81 | ||
82 | interrupt-parent = <&periph_intc>; | |
83 | interrupts = <2>; | |
84 | ||
85 | clocks = <&periph_clk>; | |
86 | ||
87 | status = "disabled"; | |
88 | }; | |
89 | ||
90 | uart1: serial@fff8c120 { | |
91 | compatible = "brcm,bcm6345-uart"; | |
92 | reg = <0xfff8c120 0x18>; | |
93 | ||
94 | interrupt-parent = <&periph_intc>; | |
95 | interrupts = <3>; | |
96 | ||
97 | clocks = <&periph_clk>; | |
98 | ||
99 | status = "disabled"; | |
100 | }; | |
101 | }; | |
102 | }; |