[linux-2.6-block.git] / arch / mips / alchemy / common / time.c

/*
 * Copyright (C) 2008-2009 Manuel Lauss <manuel.lauss@gmail.com>
 *
 * Previous incarnations were:
 * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
 * Copied and modified Carsten Langgaard's time.c
 *
 * Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
 *
 * ########################################################################
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * ########################################################################
 *
 * Clocksource/event using the 32.768kHz-clocked Counter1 ('RTC' in the
 * databooks).  Firmware/Board init code must enable the counters in the
 * counter control register, otherwise the CP0 counter clocksource/event
 * will be installed instead (and use of 'wait' instruction is prohibited).
 */

#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>

#include <asm/idle.h>
#include <asm/processor.h>
#include <asm/time.h>
#include <asm/mach-au1x00/au1000.h>

/* 32kHz clock enabled and detected */
#define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)

static u64 au1x_counter1_read(struct clocksource *cs)
{
	return alchemy_rdsys(AU1000_SYS_RTCREAD);
}

static struct clocksource au1x_counter1_clocksource = {
	.name		= "alchemy-counter1",
	.read		= au1x_counter1_read,
	.mask		= CLOCKSOURCE_MASK(32),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
	.rating		= 1500,
};

static int au1x_rtcmatch2_set_next_event(unsigned long delta,
					 struct clock_event_device *cd)
{
	delta += alchemy_rdsys(AU1000_SYS_RTCREAD);
	/* wait for register access */
	while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_M21)
		;
	alchemy_wrsys(delta, AU1000_SYS_RTCMATCH2);

	return 0;
}

static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id)
{
	struct clock_event_device *cd = dev_id;
	cd->event_handler(cd);
	return IRQ_HANDLED;
}

static struct clock_event_device au1x_rtcmatch2_clockdev = {
	.name		= "rtcmatch2",
	.features	= CLOCK_EVT_FEAT_ONESHOT,
	.rating		= 1500,
	.set_next_event = au1x_rtcmatch2_set_next_event,
	.cpumask	= cpu_all_mask,
};

static struct irqaction au1x_rtcmatch2_irqaction = {
	.handler	= au1x_rtcmatch2_irq,
	.flags		= IRQF_TIMER,
	.name		= "timer",
	.dev_id		= &au1x_rtcmatch2_clockdev,
};

static int __init alchemy_time_init(unsigned int m2int)
{
	struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;
	unsigned long t;

	au1x_rtcmatch2_clockdev.irq = m2int;

	/* Check if firmware (YAMON, ...) has enabled 32kHz and clock
	 * has been detected.  If so install the rtcmatch2 clocksource,
	 * otherwise don't bother.  Note that both bits being set is by
	 * no means a definite guarantee that the counters actually work
	 * (the 32S bit seems to be stuck set to 1 once a single clock-
	 * edge is detected, hence the timeouts).
	 */
	if (CNTR_OK != (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & CNTR_OK))
		goto cntr_err;

	/*
	 * setup counter 1 (RTC) to tick at full speed
	 */
	t = 0xffffff;
	while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_T1S) && --t)
		asm volatile ("nop");
	if (!t)
		goto cntr_err;

	alchemy_wrsys(0, AU1000_SYS_RTCTRIM);	/* 32.768 kHz */

	t = 0xffffff;
	while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C1S) && --t)
		asm volatile ("nop");
	if (!t)
		goto cntr_err;
	alchemy_wrsys(0, AU1000_SYS_RTCWRITE);

	t = 0xffffff;
	while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C1S) && --t)
		asm volatile ("nop");
	if (!t)
		goto cntr_err;

	/* register counter1 clocksource and event device */
	clocksource_register_hz(&au1x_counter1_clocksource, 32768);

	cd->shift = 32;
	cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift);
	cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd);
	cd->min_delta_ns = clockevent_delta2ns(9, cd);	/* ~0.28ms */
	clockevents_register_device(cd);
	setup_irq(m2int, &au1x_rtcmatch2_irqaction);

	printk(KERN_INFO "Alchemy clocksource installed\n");

	return 0;

cntr_err:
	return -1;
}

static int alchemy_m2inttab[] __initdata = {
	AU1000_RTC_MATCH2_INT,
	AU1500_RTC_MATCH2_INT,
	AU1100_RTC_MATCH2_INT,
	AU1550_RTC_MATCH2_INT,
	AU1200_RTC_MATCH2_INT,
	AU1300_RTC_MATCH2_INT,
};

void __init plat_time_init(void)
{
	int t;

	t = alchemy_get_cputype();
	if (t == ALCHEMY_CPU_UNKNOWN ||
	    alchemy_time_init(alchemy_m2inttab[t]))
		cpu_wait = NULL;	/* wait doesn't work with r4k timer */
}
Commit	Line	Data
1da177e4	1	/*
78814465	2	* Copyright (C) 2008-2009 Manuel Lauss <manuel.lauss@gmail.com>
1da177e4	3	*
0c694de1	4	* Previous incarnations were:
01675095	5	* Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
1da177e4 LT	6	* Copied and modified Carsten Langgaard's time.c
	7	*
	8	* Carsten Langgaard, carstenl@mips.com
	9	* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
	10	*
	11	* ########################################################################
	12	*
	13	* This program is free software; you can distribute it and/or modify it
	14	* under the terms of the GNU General Public License (Version 2) as
	15	* published by the Free Software Foundation.
	16	*
	17	* This program is distributed in the hope it will be useful, but WITHOUT
	18	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	19	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	20	* for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License along
	23	* with this program; if not, write to the Free Software Foundation, Inc.,
	24	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
	25	*
	26	* ########################################################################
	27	*
0c694de1 ML	28	* Clocksource/event using the 32.768kHz-clocked Counter1 ('RTC' in the
	29	* databooks). Firmware/Board init code must enable the counters in the
	30	* counter control register, otherwise the CP0 counter clocksource/event
	31	* will be installed instead (and use of 'wait' instruction is prohibited).
1da177e4 LT	32	*/
1da177e4 LT	33
0c694de1 ML	34	#include <linux/clockchips.h>
	35	#include <linux/clocksource.h>
	36	#include <linux/interrupt.h>
1da177e4	37	#include <linux/spinlock.h>
1da177e4	38
bdc92d74	39	#include <asm/idle.h>
2882b0c6	40	#include <asm/processor.h>
1da177e4	41	#include <asm/time.h>
1da177e4 LT	42	#include <asm/mach-au1x00/au1000.h>
1da177e4 LT	43
0c694de1 ML	44	/* 32kHz clock enabled and detected */
0c694de1 ML	45	#define CNTR_OK (SYS_CNTRL_E0 \| SYS_CNTRL_32S)
1da177e4	46
a5a1d1c2	47	static u64 au1x_counter1_read(struct clocksource *cs)
0c694de1	48	{
1d09de7d	49	return alchemy_rdsys(AU1000_SYS_RTCREAD);
0c694de1 ML	50	}
	51
	52	static struct clocksource au1x_counter1_clocksource = {
	53	.name = "alchemy-counter1",
	54	.read = au1x_counter1_read,
	55	.mask = CLOCKSOURCE_MASK(32),
	56	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
8e0d7372	57	.rating = 1500,
0c694de1 ML	58	};
	59
	60	static int au1x_rtcmatch2_set_next_event(unsigned long delta,
	61	struct clock_event_device *cd)
	62	{
1d09de7d	63	delta += alchemy_rdsys(AU1000_SYS_RTCREAD);
0c694de1	64	/* wait for register access */
1d09de7d	65	while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_M21)
0c694de1	66	;
1d09de7d	67	alchemy_wrsys(delta, AU1000_SYS_RTCMATCH2);
0c694de1 ML	68
	69	return 0;
	70	}
	71
0c694de1 ML	72	static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id)
	73	{
	74	struct clock_event_device *cd = dev_id;
	75	cd->event_handler(cd);
	76	return IRQ_HANDLED;
	77	}
	78
	79	static struct clock_event_device au1x_rtcmatch2_clockdev = {
	80	.name = "rtcmatch2",
	81	.features = CLOCK_EVT_FEAT_ONESHOT,
8e0d7372	82	.rating = 1500,
70342287	83	.set_next_event = au1x_rtcmatch2_set_next_event,
51c870a2	84	.cpumask = cpu_all_mask,
0c694de1 ML	85	};
	86
	87	static struct irqaction au1x_rtcmatch2_irqaction = {
	88	.handler = au1x_rtcmatch2_irq,
8b5690f8	89	.flags = IRQF_TIMER,
0c694de1 ML	90	.name = "timer",
	91	.dev_id = &au1x_rtcmatch2_clockdev,
	92	};
	93
78814465	94	static int __init alchemy_time_init(unsigned int m2int)
1da177e4	95	{
0c694de1 ML	96	struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;
0c694de1 ML	97	unsigned long t;
1da177e4	98
78814465 ML	99	au1x_rtcmatch2_clockdev.irq = m2int;
78814465 ML	100
0c694de1 ML	101	/* Check if firmware (YAMON, ...) has enabled 32kHz and clock
	102	* has been detected. If so install the rtcmatch2 clocksource,
	103	* otherwise don't bother. Note that both bits being set is by
	104	* no means a definite guarantee that the counters actually work
	105	* (the 32S bit seems to be stuck set to 1 once a single clock-
	106	* edge is detected, hence the timeouts).
1da177e4	107	*/
1d09de7d	108	if (CNTR_OK != (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & CNTR_OK))
0c694de1	109	goto cntr_err;
1da177e4	110
0c694de1 ML	111	/*
	112	* setup counter 1 (RTC) to tick at full speed
	113	*/
	114	t = 0xffffff;
1d09de7d	115	while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_T1S) && --t)
0c694de1 ML	116	asm volatile ("nop");
	117	if (!t)
	118	goto cntr_err;
1da177e4	119
1d09de7d	120	alchemy_wrsys(0, AU1000_SYS_RTCTRIM); /* 32.768 kHz */
1da177e4	121
0c694de1	122	t = 0xffffff;
1d09de7d	123	while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C1S) && --t)
0c694de1 ML	124	asm volatile ("nop");
	125	if (!t)
	126	goto cntr_err;
1d09de7d	127	alchemy_wrsys(0, AU1000_SYS_RTCWRITE);
1da177e4	128
0c694de1	129	t = 0xffffff;
1d09de7d	130	while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C1S) && --t)
0c694de1 ML	131	asm volatile ("nop");
	132	if (!t)
	133	goto cntr_err;
	134
	135	/* register counter1 clocksource and event device */
75c4fd8c	136	clocksource_register_hz(&au1x_counter1_clocksource, 32768);
0c694de1 ML	137
	138	cd->shift = 32;
	139	cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift);
	140	cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd);
8e365790	141	cd->min_delta_ns = clockevent_delta2ns(9, cd); /* ~0.28ms */
0c694de1	142	clockevents_register_device(cd);
78814465	143	setup_irq(m2int, &au1x_rtcmatch2_irqaction);
0c694de1 ML	144
	145	printk(KERN_INFO "Alchemy clocksource installed\n");
	146
78814465	147	return 0;
0c694de1 ML	148
0c694de1 ML	149	cntr_err:
78814465 ML	150	return -1;
	151	}
	152
78814465 ML	153	static int alchemy_m2inttab[] __initdata = {
	154	AU1000_RTC_MATCH2_INT,
	155	AU1500_RTC_MATCH2_INT,
	156	AU1100_RTC_MATCH2_INT,
	157	AU1550_RTC_MATCH2_INT,
	158	AU1200_RTC_MATCH2_INT,
809f36c6	159	AU1300_RTC_MATCH2_INT,
78814465 ML	160	};
	161
	162	void __init plat_time_init(void)
	163	{
	164	int t;
	165
	166	t = alchemy_get_cputype();
8e0d7372 ML	167	if (t == ALCHEMY_CPU_UNKNOWN \|\|
	168	alchemy_time_init(alchemy_m2inttab[t]))
	169	cpu_wait = NULL; /* wait doesn't work with r4k timer */
78814465	170	}