Commit | Line | Data |
---|---|---|
b2441318 | 1 | # SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | config MIPS |
3 | bool | |
4 | default y | |
942fa985 | 5 | select ARCH_32BIT_OFF_T if !64BIT |
ea6a3737 | 6 | select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT |
8690bbcf | 7 | select ARCH_HAS_CPU_CACHE_ALIASING |
7f066a22 | 8 | select ARCH_HAS_CPU_FINALIZE_INIT |
b847bd64 | 9 | select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000 |
dfad83cb | 10 | select ARCH_HAS_DEBUG_VIRTUAL if !64BIT |
34c01e41 AL |
11 | select ARCH_HAS_FORTIFY_SOURCE |
12 | select ARCH_HAS_KCOV | |
66633abd | 13 | select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA |
34c01e41 | 14 | select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI) |
e6226997 AB |
15 | select ARCH_HAS_STRNCPY_FROM_USER |
16 | select ARCH_HAS_STRNLEN_USER | |
12597988 | 17 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
918327e9 | 18 | select ARCH_HAS_UBSAN |
8b3165e5 | 19 | select ARCH_HAS_GCOV_PROFILE_ALL |
c55944cc | 20 | select ARCH_KEEP_MEMBLOCK |
1ee3630a | 21 | select ARCH_USE_BUILTIN_BSWAP |
12597988 | 22 | select ARCH_USE_CMPXCHG_LOCKREF if 64BIT |
dce44566 | 23 | select ARCH_USE_MEMTEST |
25da4e9d | 24 | select ARCH_USE_QUEUED_RWLOCKS |
0b17c967 | 25 | select ARCH_USE_QUEUED_SPINLOCKS |
855f9a8e | 26 | select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES |
9035bd29 | 27 | select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU |
12597988 | 28 | select ARCH_WANT_IPC_PARSE_VERSION |
d3a4e0f1 | 29 | select ARCH_WANT_LD_ORPHAN_WARN |
10916706 | 30 | select BUILDTIME_TABLE_SORT |
12597988 | 31 | select CLONE_BACKWARDS |
57eeaced | 32 | select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1) |
12597988 MR |
33 | select CPU_PM if CPU_IDLE |
34 | select GENERIC_ATOMIC64 if !64BIT | |
12597988 MR |
35 | select GENERIC_CMOS_UPDATE |
36 | select GENERIC_CPU_AUTOPROBE | |
24640f23 | 37 | select GENERIC_GETTIMEOFDAY |
b962aeb0 | 38 | select GENERIC_IOMAP |
12597988 MR |
39 | select GENERIC_IRQ_PROBE |
40 | select GENERIC_IRQ_SHOW | |
6630a8e5 | 41 | select GENERIC_ISA_DMA if EISA |
740129b3 AP |
42 | select GENERIC_LIB_ASHLDI3 |
43 | select GENERIC_LIB_ASHRDI3 | |
44 | select GENERIC_LIB_CMPDI2 | |
45 | select GENERIC_LIB_LSHRDI3 | |
46 | select GENERIC_LIB_UCMPDI2 | |
12597988 MR |
47 | select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC |
48 | select GENERIC_SMP_IDLE_THREAD | |
975fd3c2 | 49 | select GENERIC_IDLE_POLL_SETUP |
12597988 | 50 | select GENERIC_TIME_VSYSCALL |
6ca297d4 | 51 | select GUP_GET_PXX_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT |
fcbfe812 | 52 | select HAS_IOPORT if !NO_IOPORT_MAP || ISA |
906d441f | 53 | select HAVE_ARCH_COMPILER_H |
12597988 | 54 | select HAVE_ARCH_JUMP_LABEL |
42b20995 | 55 | select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT |
109c32ff MR |
56 | select HAVE_ARCH_MMAP_RND_BITS if MMU |
57 | select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT | |
490b004f | 58 | select HAVE_ARCH_SECCOMP_FILTER |
c0ff3c53 | 59 | select HAVE_ARCH_TRACEHOOK |
45e03e62 | 60 | select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES |
2ff2b7ec | 61 | select HAVE_ASM_MODVERSIONS |
24a9c541 | 62 | select HAVE_CONTEXT_TRACKING_USER |
490f561b | 63 | select HAVE_TIF_NOHZ |
12597988 MR |
64 | select HAVE_C_RECORDMCOUNT |
65 | select HAVE_DEBUG_KMEMLEAK | |
66 | select HAVE_DEBUG_STACKOVERFLOW | |
12597988 | 67 | select HAVE_DMA_CONTIGUOUS |
538f1952 | 68 | select HAVE_DYNAMIC_FTRACE |
7364d60c | 69 | select HAVE_EBPF_JIT if !CPU_MICROMIPS |
12597988 | 70 | select HAVE_EXIT_THREAD |
25176ad0 | 71 | select HAVE_GUP_FAST |
538f1952 | 72 | select HAVE_FTRACE_MCOUNT_RECORD |
29c5d346 | 73 | select HAVE_FUNCTION_GRAPH_TRACER |
12597988 | 74 | select HAVE_FUNCTION_TRACER |
34c01e41 AL |
75 | select HAVE_GCC_PLUGINS |
76 | select HAVE_GENERIC_VDSO | |
b3a428b4 | 77 | select HAVE_IOREMAP_PROT |
12597988 MR |
78 | select HAVE_IRQ_EXIT_ON_IRQ_STACK |
79 | select HAVE_IRQ_TIME_ACCOUNTING | |
c1bf207d DD |
80 | select HAVE_KPROBES |
81 | select HAVE_KRETPROBES | |
c0436b50 | 82 | select HAVE_LD_DEAD_CODE_DATA_ELIMINATION |
786d35d4 | 83 | select HAVE_MOD_ARCH_SPECIFIC |
42a0bb3f | 84 | select HAVE_NMI |
ba89f9c8 AB |
85 | select HAVE_PAGE_SIZE_4KB if !CPU_LOONGSON2EF && !CPU_LOONGSON64 |
86 | select HAVE_PAGE_SIZE_16KB if !CPU_R3000 | |
87 | select HAVE_PAGE_SIZE_64KB if !CPU_R3000 | |
12597988 | 88 | select HAVE_PERF_EVENTS |
1ddc96bd TY |
89 | select HAVE_PERF_REGS |
90 | select HAVE_PERF_USER_STACK_DUMP | |
12597988 | 91 | select HAVE_REGS_AND_STACK_ACCESS_API |
9ea141ad | 92 | select HAVE_RSEQ |
16c0f03f | 93 | select HAVE_SPARSE_SYSCALL_NR |
d148eac0 | 94 | select HAVE_STACKPROTECTOR |
12597988 | 95 | select HAVE_SYSCALL_TRACEPOINTS |
a3f14310 | 96 | select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP |
12597988 | 97 | select IRQ_FORCED_THREADING |
6630a8e5 | 98 | select ISA if EISA |
4bce37a6 | 99 | select LOCK_MM_AND_FIND_VMA |
12597988 | 100 | select MODULES_USE_ELF_REL if MODULES |
34c01e41 | 101 | select MODULES_USE_ELF_RELA if MODULES && 64BIT |
12597988 | 102 | select PERF_USE_VMALLOC |
981aa1d3 | 103 | select PCI_MSI_ARCH_FALLBACKS if PCI_MSI |
05a0a344 | 104 | select RTC_LIB |
d79d853d | 105 | select SYSCTL_EXCEPTION_TRACE |
4aae683f | 106 | select TRACE_IRQFLAGS_SUPPORT |
0bb87f05 | 107 | select ARCH_HAS_ELFCORE_COMPAT |
e0a8b93e | 108 | select HAVE_ARCH_KCSAN if 64BIT |
1da177e4 | 109 | |
d3991572 CH |
110 | config MIPS_FIXUP_BIGPHYS_ADDR |
111 | bool | |
112 | ||
c434b9f8 PC |
113 | config MIPS_GENERIC |
114 | bool | |
115 | ||
80f2e4cd GC |
116 | config MACH_GENERIC_CORE |
117 | bool | |
118 | ||
f0f4a753 PC |
119 | config MACH_INGENIC |
120 | bool | |
121 | select SYS_SUPPORTS_32BIT_KERNEL | |
122 | select SYS_SUPPORTS_LITTLE_ENDIAN | |
123 | select SYS_SUPPORTS_ZBOOT | |
f0f4a753 PC |
124 | select DMA_NONCOHERENT |
125 | select IRQ_MIPS_CPU | |
126 | select PINCTRL | |
127 | select GPIOLIB | |
128 | select COMMON_CLK | |
129 | select GENERIC_IRQ_CHIP | |
130 | select BUILTIN_DTB if MIPS_NO_APPENDED_DTB | |
131 | select USE_OF | |
132 | select CPU_SUPPORTS_CPUFREQ | |
133 | select MIPS_EXTERNAL_TIMER | |
134 | ||
1da177e4 LT |
135 | menu "Machine selection" |
136 | ||
5e83d430 RB |
137 | choice |
138 | prompt "System type" | |
c434b9f8 | 139 | default MIPS_GENERIC_KERNEL |
1da177e4 | 140 | |
c434b9f8 | 141 | config MIPS_GENERIC_KERNEL |
eed0eabd | 142 | bool "Generic board-agnostic MIPS kernel" |
c434b9f8 | 143 | select MIPS_GENERIC |
eed0eabd PB |
144 | select BOOT_RAW |
145 | select BUILTIN_DTB | |
146 | select CEVT_R4K | |
147 | select CLKSRC_MIPS_GIC | |
148 | select COMMON_CLK | |
eed0eabd | 149 | select CPU_MIPSR2_IRQ_EI |
34c01e41 | 150 | select CPU_MIPSR2_IRQ_VI |
eed0eabd | 151 | select CSRC_R4K |
4e066441 | 152 | select DMA_NONCOHERENT |
eb01d42a | 153 | select HAVE_PCI |
eed0eabd | 154 | select IRQ_MIPS_CPU |
80f2e4cd | 155 | select MACH_GENERIC_CORE |
0211d49e | 156 | select MIPS_AUTO_PFN_OFFSET |
eed0eabd PB |
157 | select MIPS_CPU_SCACHE |
158 | select MIPS_GIC | |
159 | select MIPS_L1_CACHE_SHIFT_7 | |
160 | select NO_EXCEPT_FILL | |
161 | select PCI_DRIVERS_GENERIC | |
eed0eabd | 162 | select SMP_UP if SMP |
a3078e59 | 163 | select SWAP_IO_SPACE |
eed0eabd PB |
164 | select SYS_HAS_CPU_MIPS32_R1 |
165 | select SYS_HAS_CPU_MIPS32_R2 | |
fb6700c5 | 166 | select SYS_HAS_CPU_MIPS32_R5 |
eed0eabd PB |
167 | select SYS_HAS_CPU_MIPS32_R6 |
168 | select SYS_HAS_CPU_MIPS64_R1 | |
169 | select SYS_HAS_CPU_MIPS64_R2 | |
fb6700c5 | 170 | select SYS_HAS_CPU_MIPS64_R5 |
eed0eabd PB |
171 | select SYS_HAS_CPU_MIPS64_R6 |
172 | select SYS_SUPPORTS_32BIT_KERNEL | |
173 | select SYS_SUPPORTS_64BIT_KERNEL | |
174 | select SYS_SUPPORTS_BIG_ENDIAN | |
175 | select SYS_SUPPORTS_HIGHMEM | |
176 | select SYS_SUPPORTS_LITTLE_ENDIAN | |
177 | select SYS_SUPPORTS_MICROMIPS | |
eed0eabd | 178 | select SYS_SUPPORTS_MIPS16 |
34c01e41 | 179 | select SYS_SUPPORTS_MIPS_CPS |
eed0eabd PB |
180 | select SYS_SUPPORTS_MULTITHREADING |
181 | select SYS_SUPPORTS_RELOCATABLE | |
182 | select SYS_SUPPORTS_SMARTMIPS | |
c3e2ee65 | 183 | select SYS_SUPPORTS_ZBOOT |
34c01e41 | 184 | select UHI_BOOT |
2e6522c5 CL |
185 | select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN |
186 | select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN | |
187 | select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN | |
188 | select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN | |
189 | select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN | |
190 | select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN | |
eed0eabd PB |
191 | select USE_OF |
192 | help | |
193 | Select this to build a kernel which aims to support multiple boards, | |
194 | generally using a flattened device tree passed from the bootloader | |
195 | using the boot protocol defined in the UHI (Unified Hosting | |
196 | Interface) specification. | |
197 | ||
42a4f17d | 198 | config MIPS_ALCHEMY |
c3543e25 | 199 | bool "Alchemy processor based machines" |
d4a451d5 | 200 | select PHYS_ADDR_T_64BIT |
f772cdb2 | 201 | select CEVT_R4K |
d7ea335c | 202 | select CSRC_R4K |
67e38cf2 | 203 | select IRQ_MIPS_CPU |
a86497d6 | 204 | select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is |
d3991572 | 205 | select MIPS_FIXUP_BIGPHYS_ADDR if PCI |
42a4f17d ML |
206 | select SYS_HAS_CPU_MIPS32_R1 |
207 | select SYS_SUPPORTS_32BIT_KERNEL | |
208 | select SYS_SUPPORTS_APM_EMULATION | |
d30a2b47 | 209 | select GPIOLIB |
1b93b3c3 | 210 | select SYS_SUPPORTS_ZBOOT |
47440229 | 211 | select COMMON_CLK |
1da177e4 | 212 | |
43cc739f SR |
213 | config ATH25 |
214 | bool "Atheros AR231x/AR531x SoC support" | |
215 | select CEVT_R4K | |
216 | select CSRC_R4K | |
217 | select DMA_NONCOHERENT | |
67e38cf2 | 218 | select IRQ_MIPS_CPU |
1753e74e | 219 | select IRQ_DOMAIN |
43cc739f SR |
220 | select SYS_HAS_CPU_MIPS32_R1 |
221 | select SYS_SUPPORTS_BIG_ENDIAN | |
222 | select SYS_SUPPORTS_32BIT_KERNEL | |
8aaa7278 | 223 | select SYS_HAS_EARLY_PRINTK |
43cc739f SR |
224 | help |
225 | Support for Atheros AR231x and Atheros AR531x based boards | |
226 | ||
d4a67d9d GJ |
227 | config ATH79 |
228 | bool "Atheros AR71XX/AR724X/AR913X based boards" | |
ff591a91 | 229 | select ARCH_HAS_RESET_CONTROLLER |
d4a67d9d GJ |
230 | select BOOT_RAW |
231 | select CEVT_R4K | |
232 | select CSRC_R4K | |
233 | select DMA_NONCOHERENT | |
d30a2b47 | 234 | select GPIOLIB |
a08227a2 | 235 | select PINCTRL |
411520af | 236 | select COMMON_CLK |
67e38cf2 | 237 | select IRQ_MIPS_CPU |
d4a67d9d GJ |
238 | select SYS_HAS_CPU_MIPS32_R2 |
239 | select SYS_HAS_EARLY_PRINTK | |
240 | select SYS_SUPPORTS_32BIT_KERNEL | |
241 | select SYS_SUPPORTS_BIG_ENDIAN | |
377cb1b6 | 242 | select SYS_SUPPORTS_MIPS16 |
b3f0a250 | 243 | select SYS_SUPPORTS_ZBOOT_UART_PROM |
03c8c407 | 244 | select USE_OF |
53d473fc | 245 | select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM |
d4a67d9d GJ |
246 | help |
247 | Support for the Atheros AR71XX/AR724X/AR913X SoCs. | |
248 | ||
5f2d4459 KC |
249 | config BMIPS_GENERIC |
250 | bool "Broadcom Generic BMIPS kernel" | |
29906e1a | 251 | select ARCH_HAS_RESET_CONTROLLER |
d59098a0 | 252 | select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL |
d666cd02 KC |
253 | select BOOT_RAW |
254 | select NO_EXCEPT_FILL | |
255 | select USE_OF | |
256 | select CEVT_R4K | |
257 | select CSRC_R4K | |
258 | select SYNC_R4K | |
259 | select COMMON_CLK | |
c7c42ec2 | 260 | select BCM6345_L1_IRQ |
60b858f2 KC |
261 | select BCM7038_L1_IRQ |
262 | select BCM7120_L2_IRQ | |
263 | select BRCMSTB_L2_IRQ | |
67e38cf2 | 264 | select IRQ_MIPS_CPU |
60b858f2 | 265 | select DMA_NONCOHERENT |
d666cd02 | 266 | select SYS_SUPPORTS_32BIT_KERNEL |
60b858f2 | 267 | select SYS_SUPPORTS_LITTLE_ENDIAN |
d666cd02 KC |
268 | select SYS_SUPPORTS_BIG_ENDIAN |
269 | select SYS_SUPPORTS_HIGHMEM | |
60b858f2 KC |
270 | select SYS_HAS_CPU_BMIPS32_3300 |
271 | select SYS_HAS_CPU_BMIPS4350 | |
272 | select SYS_HAS_CPU_BMIPS4380 | |
d666cd02 KC |
273 | select SYS_HAS_CPU_BMIPS5000 |
274 | select SWAP_IO_SPACE | |
60b858f2 KC |
275 | select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN |
276 | select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN | |
277 | select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN | |
278 | select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN | |
4dc4704c | 279 | select HARDIRQS_SW_RESEND |
1d987052 FF |
280 | select HAVE_PCI |
281 | select PCI_DRIVERS_GENERIC | |
466ab2ea | 282 | select FW_CFE |
d666cd02 | 283 | help |
5f2d4459 KC |
284 | Build a generic DT-based kernel image that boots on select |
285 | BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top | |
286 | box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN | |
287 | must be set appropriately for your board. | |
d666cd02 | 288 | |
1c0c13eb | 289 | config BCM47XX |
c619366e | 290 | bool "Broadcom BCM47XX based boards" |
fe08f8c2 | 291 | select BOOT_RAW |
42f77542 | 292 | select CEVT_R4K |
940f6b48 | 293 | select CSRC_R4K |
1c0c13eb | 294 | select DMA_NONCOHERENT |
eb01d42a | 295 | select HAVE_PCI |
67e38cf2 | 296 | select IRQ_MIPS_CPU |
314878d2 | 297 | select SYS_HAS_CPU_MIPS32_R1 |
dd54dedd | 298 | select NO_EXCEPT_FILL |
1c0c13eb AJ |
299 | select SYS_SUPPORTS_32BIT_KERNEL |
300 | select SYS_SUPPORTS_LITTLE_ENDIAN | |
377cb1b6 | 301 | select SYS_SUPPORTS_MIPS16 |
6507831f | 302 | select SYS_SUPPORTS_ZBOOT |
25e5fb97 | 303 | select SYS_HAS_EARLY_PRINTK |
e6086557 | 304 | select USE_GENERIC_EARLY_PRINTK_8250 |
c949c0bc RM |
305 | select GPIOLIB |
306 | select LEDS_GPIO_REGISTER | |
f6e734a8 | 307 | select BCM47XX_NVRAM |
2ab71a02 | 308 | select BCM47XX_SPROM |
dfe00495 | 309 | select BCM47XX_SSB if !BCM47XX_BCMA |
1c0c13eb | 310 | help |
371a4151 | 311 | Support for BCM47XX based boards |
1c0c13eb | 312 | |
e7300d04 MB |
313 | config BCM63XX |
314 | bool "Broadcom BCM63XX based boards" | |
ae8de61c | 315 | select BOOT_RAW |
e7300d04 MB |
316 | select CEVT_R4K |
317 | select CSRC_R4K | |
fc264022 | 318 | select SYNC_R4K |
e7300d04 | 319 | select DMA_NONCOHERENT |
67e38cf2 | 320 | select IRQ_MIPS_CPU |
e7300d04 MB |
321 | select SYS_SUPPORTS_32BIT_KERNEL |
322 | select SYS_SUPPORTS_BIG_ENDIAN | |
323 | select SYS_HAS_EARLY_PRINTK | |
5eeaafc8 RD |
324 | select SYS_HAS_CPU_BMIPS32_3300 |
325 | select SYS_HAS_CPU_BMIPS4350 | |
326 | select SYS_HAS_CPU_BMIPS4380 | |
e7300d04 | 327 | select SWAP_IO_SPACE |
d30a2b47 | 328 | select GPIOLIB |
af2418be | 329 | select MIPS_L1_CACHE_SHIFT_4 |
bbd7ffdb | 330 | select HAVE_LEGACY_CLK |
e7300d04 | 331 | help |
371a4151 | 332 | Support for BCM63XX based boards |
e7300d04 | 333 | |
1da177e4 | 334 | config MIPS_COBALT |
3fa986fa | 335 | bool "Cobalt Server" |
42f77542 | 336 | select CEVT_R4K |
940f6b48 | 337 | select CSRC_R4K |
1097c6ac | 338 | select CEVT_GT641XX |
1da177e4 | 339 | select DMA_NONCOHERENT |
eb01d42a | 340 | select FORCE_PCI |
d865bea4 | 341 | select I8253 |
1da177e4 | 342 | select I8259 |
67e38cf2 | 343 | select IRQ_MIPS_CPU |
d5ab1a69 | 344 | select IRQ_GT641XX |
252161ec | 345 | select PCI_GT64XXX_PCI0 |
7cf8053b | 346 | select SYS_HAS_CPU_NEVADA |
0a22e0d4 | 347 | select SYS_HAS_EARLY_PRINTK |
ed5ba2fb | 348 | select SYS_SUPPORTS_32BIT_KERNEL |
0e8774b6 | 349 | select SYS_SUPPORTS_64BIT_KERNEL |
5e83d430 | 350 | select SYS_SUPPORTS_LITTLE_ENDIAN |
e6086557 | 351 | select USE_GENERIC_EARLY_PRINTK_8250 |
1da177e4 LT |
352 | |
353 | config MACH_DECSTATION | |
3fa986fa | 354 | bool "DECstations" |
1da177e4 | 355 | select BOOT_ELF32 |
6457d9fc | 356 | select CEVT_DS1287 |
81d10bad | 357 | select CEVT_R4K if CPU_R4X00 |
4247417d | 358 | select CSRC_IOASIC |
81d10bad | 359 | select CSRC_R4K if CPU_R4X00 |
20d60d99 MR |
360 | select CPU_DADDI_WORKAROUNDS if 64BIT |
361 | select CPU_R4000_WORKAROUNDS if 64BIT | |
362 | select CPU_R4400_WORKAROUNDS if 64BIT | |
1da177e4 | 363 | select DMA_NONCOHERENT |
ce816fa8 | 364 | select NO_IOPORT_MAP |
67e38cf2 | 365 | select IRQ_MIPS_CPU |
7cf8053b RB |
366 | select SYS_HAS_CPU_R3000 |
367 | select SYS_HAS_CPU_R4X00 | |
ed5ba2fb | 368 | select SYS_SUPPORTS_32BIT_KERNEL |
7d60717e | 369 | select SYS_SUPPORTS_64BIT_KERNEL |
5e83d430 | 370 | select SYS_SUPPORTS_LITTLE_ENDIAN |
1723b4a3 AN |
371 | select SYS_SUPPORTS_128HZ |
372 | select SYS_SUPPORTS_256HZ | |
373 | select SYS_SUPPORTS_1024HZ | |
930beb5a | 374 | select MIPS_L1_CACHE_SHIFT_4 |
5e83d430 | 375 | help |
1da177e4 LT |
376 | This enables support for DEC's MIPS based workstations. For details |
377 | see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the | |
378 | DECstation porting pages on <http://decstation.unix-ag.org/>. | |
379 | ||
380 | If you have one of the following DECstation Models you definitely | |
381 | want to choose R4xx0 for the CPU Type: | |
382 | ||
9308816c RB |
383 | DECstation 5000/50 |
384 | DECstation 5000/150 | |
385 | DECstation 5000/260 | |
386 | DECsystem 5900/260 | |
1da177e4 LT |
387 | |
388 | otherwise choose R3000. | |
389 | ||
5e83d430 | 390 | config MACH_JAZZ |
3fa986fa | 391 | bool "Jazz family of machines" |
39b2d756 TB |
392 | select ARC_MEMORY |
393 | select ARC_PROMLIB | |
a211a082 | 394 | select ARCH_MIGHT_HAVE_PC_PARPORT |
7a407aa5 | 395 | select ARCH_MIGHT_HAVE_PC_SERIO |
2f9237d4 | 396 | select DMA_OPS |
0e2794b0 RB |
397 | select FW_ARC |
398 | select FW_ARC32 | |
5e83d430 | 399 | select ARCH_MAY_HAVE_PC_FDC |
42f77542 | 400 | select CEVT_R4K |
940f6b48 | 401 | select CSRC_R4K |
e2defae5 | 402 | select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN |
5e83d430 | 403 | select GENERIC_ISA_DMA |
8a118c38 | 404 | select HAVE_PCSPKR_PLATFORM |
67e38cf2 | 405 | select IRQ_MIPS_CPU |
d865bea4 | 406 | select I8253 |
5e83d430 RB |
407 | select I8259 |
408 | select ISA | |
7cf8053b | 409 | select SYS_HAS_CPU_R4X00 |
5e83d430 | 410 | select SYS_SUPPORTS_32BIT_KERNEL |
7d60717e | 411 | select SYS_SUPPORTS_64BIT_KERNEL |
1723b4a3 | 412 | select SYS_SUPPORTS_100HZ |
aadfe4b5 | 413 | select SYS_SUPPORTS_LITTLE_ENDIAN |
1da177e4 | 414 | help |
371a4151 EWI |
415 | This a family of machines based on the MIPS R4030 chipset which was |
416 | used by several vendors to build RISC/os and Windows NT workstations. | |
417 | Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and | |
418 | Olivetti M700-10 workstations. | |
5e83d430 | 419 | |
f0f4a753 | 420 | config MACH_INGENIC_SOC |
de361e8b | 421 | bool "Ingenic SoC based machines" |
f0f4a753 PC |
422 | select MIPS_GENERIC |
423 | select MACH_INGENIC | |
80f2e4cd | 424 | select MACH_GENERIC_CORE |
f9c9affc | 425 | select SYS_SUPPORTS_ZBOOT_UART16550 |
eb384937 PC |
426 | select CPU_SUPPORTS_CPUFREQ |
427 | select MIPS_EXTERNAL_TIMER | |
5ebabe59 | 428 | |
171bb2f1 JC |
429 | config LANTIQ |
430 | bool "Lantiq based platforms" | |
431 | select DMA_NONCOHERENT | |
67e38cf2 | 432 | select IRQ_MIPS_CPU |
171bb2f1 JC |
433 | select CEVT_R4K |
434 | select CSRC_R4K | |
b74cc639 | 435 | select NO_EXCEPT_FILL |
171bb2f1 JC |
436 | select SYS_HAS_CPU_MIPS32_R1 |
437 | select SYS_HAS_CPU_MIPS32_R2 | |
438 | select SYS_SUPPORTS_BIG_ENDIAN | |
439 | select SYS_SUPPORTS_32BIT_KERNEL | |
377cb1b6 | 440 | select SYS_SUPPORTS_MIPS16 |
171bb2f1 | 441 | select SYS_SUPPORTS_MULTITHREADING |
f35764e7 | 442 | select SYS_SUPPORTS_VPE_LOADER |
171bb2f1 | 443 | select SYS_HAS_EARLY_PRINTK |
d30a2b47 | 444 | select GPIOLIB |
171bb2f1 JC |
445 | select SWAP_IO_SPACE |
446 | select BOOT_RAW | |
bbd7ffdb | 447 | select HAVE_LEGACY_CLK |
a0392222 | 448 | select USE_OF |
3f8c50c9 JC |
449 | select PINCTRL |
450 | select PINCTRL_LANTIQ | |
c530781c JC |
451 | select ARCH_HAS_RESET_CONTROLLER |
452 | select RESET_CONTROLLER | |
171bb2f1 | 453 | |
30ad29bb | 454 | config MACH_LOONGSON32 |
caed1d1b | 455 | bool "Loongson 32-bit family of machines" |
c7e8c668 | 456 | select SYS_SUPPORTS_ZBOOT |
ade299d8 | 457 | help |
30ad29bb | 458 | This enables support for the Loongson-1 family of machines. |
85749d24 | 459 | |
30ad29bb HC |
460 | Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by |
461 | the Institute of Computing Technology (ICT), Chinese Academy of | |
462 | Sciences (CAS). | |
ade299d8 | 463 | |
71e2f4dd JY |
464 | config MACH_LOONGSON2EF |
465 | bool "Loongson-2E/F family of machines" | |
ca585cf9 KC |
466 | select SYS_SUPPORTS_ZBOOT |
467 | help | |
71e2f4dd | 468 | This enables the support of early Loongson-2E/F family of machines. |
ca585cf9 | 469 | |
71e2f4dd | 470 | config MACH_LOONGSON64 |
caed1d1b | 471 | bool "Loongson 64-bit family of machines" |
edc0378e | 472 | select ARCH_DMA_DEFAULT_COHERENT |
6fbde6b4 JY |
473 | select ARCH_SPARSEMEM_ENABLE |
474 | select ARCH_MIGHT_HAVE_PC_PARPORT | |
475 | select ARCH_MIGHT_HAVE_PC_SERIO | |
476 | select GENERIC_ISA_DMA_SUPPORT_BROKEN | |
477 | select BOOT_ELF32 | |
478 | select BOARD_SCACHE | |
479 | select CSRC_R4K | |
480 | select CEVT_R4K | |
6fbde6b4 JY |
481 | select FORCE_PCI |
482 | select ISA | |
483 | select I8259 | |
484 | select IRQ_MIPS_CPU | |
7d6d2837 | 485 | select NO_EXCEPT_FILL |
5125bfee | 486 | select NR_CPUS_DEFAULT_64 |
6fbde6b4 | 487 | select USE_GENERIC_EARLY_PRINTK_8250 |
6423e59a | 488 | select PCI_DRIVERS_GENERIC |
6fbde6b4 JY |
489 | select SYS_HAS_CPU_LOONGSON64 |
490 | select SYS_HAS_EARLY_PRINTK | |
491 | select SYS_SUPPORTS_SMP | |
492 | select SYS_SUPPORTS_HOTPLUG_CPU | |
493 | select SYS_SUPPORTS_NUMA | |
494 | select SYS_SUPPORTS_64BIT_KERNEL | |
495 | select SYS_SUPPORTS_HIGHMEM | |
496 | select SYS_SUPPORTS_LITTLE_ENDIAN | |
71e2f4dd | 497 | select SYS_SUPPORTS_ZBOOT |
a307a4ce | 498 | select SYS_SUPPORTS_RELOCATABLE |
6fbde6b4 | 499 | select ZONE_DMA32 |
87fcfa7b JY |
500 | select COMMON_CLK |
501 | select USE_OF | |
502 | select BUILTIN_DTB | |
39c1485c | 503 | select PCI_HOST_GENERIC |
f8f9f21c | 504 | select HAVE_ARCH_NODEDATA_EXTENSION if NUMA |
71e2f4dd | 505 | help |
caed1d1b HC |
506 | This enables the support of Loongson-2/3 family of machines. |
507 | ||
508 | Loongson-2 and Loongson-3 are 64-bit general-purpose processors with | |
509 | GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E | |
510 | and Loongson-2F which will be removed), developed by the Institute | |
511 | of Computing Technology (ICT), Chinese Academy of Sciences (CAS). | |
ca585cf9 | 512 | |
1da177e4 | 513 | config MIPS_MALTA |
3fa986fa | 514 | bool "MIPS Malta board" |
61ed242d | 515 | select ARCH_MAY_HAVE_PC_FDC |
a211a082 | 516 | select ARCH_MIGHT_HAVE_PC_PARPORT |
7a407aa5 | 517 | select ARCH_MIGHT_HAVE_PC_SERIO |
1da177e4 | 518 | select BOOT_ELF32 |
fa71c960 | 519 | select BOOT_RAW |
e8823d26 | 520 | select BUILTIN_DTB |
42f77542 | 521 | select CEVT_R4K |
fa5635a2 | 522 | select CLKSRC_MIPS_GIC |
42b002ab | 523 | select COMMON_CLK |
47bf2b03 | 524 | select CSRC_R4K |
a86497d6 | 525 | select DMA_NONCOHERENT |
1da177e4 | 526 | select GENERIC_ISA_DMA |
8a118c38 | 527 | select HAVE_PCSPKR_PLATFORM |
eb01d42a | 528 | select HAVE_PCI |
d865bea4 | 529 | select I8253 |
1da177e4 | 530 | select I8259 |
47bf2b03 | 531 | select IRQ_MIPS_CPU |
5e83d430 | 532 | select MIPS_BONITO64 |
9318c51a | 533 | select MIPS_CPU_SCACHE |
47bf2b03 | 534 | select MIPS_GIC |
a7ef1ead | 535 | select MIPS_L1_CACHE_SHIFT_6 |
5e83d430 | 536 | select MIPS_MSC |
47bf2b03 | 537 | select PCI_GT64XXX_PCI0 |
ecafe3e9 | 538 | select SMP_UP if SMP |
1da177e4 | 539 | select SWAP_IO_SPACE |
7cf8053b RB |
540 | select SYS_HAS_CPU_MIPS32_R1 |
541 | select SYS_HAS_CPU_MIPS32_R2 | |
bfc3c5a6 | 542 | select SYS_HAS_CPU_MIPS32_R3_5 |
c5b36783 | 543 | select SYS_HAS_CPU_MIPS32_R5 |
575509b6 | 544 | select SYS_HAS_CPU_MIPS32_R6 |
7cf8053b | 545 | select SYS_HAS_CPU_MIPS64_R1 |
5d9fbed1 | 546 | select SYS_HAS_CPU_MIPS64_R2 |
575509b6 | 547 | select SYS_HAS_CPU_MIPS64_R6 |
7cf8053b RB |
548 | select SYS_HAS_CPU_NEVADA |
549 | select SYS_HAS_CPU_RM7000 | |
ed5ba2fb YY |
550 | select SYS_SUPPORTS_32BIT_KERNEL |
551 | select SYS_SUPPORTS_64BIT_KERNEL | |
5e83d430 | 552 | select SYS_SUPPORTS_BIG_ENDIAN |
c5b36783 | 553 | select SYS_SUPPORTS_HIGHMEM |
5e83d430 | 554 | select SYS_SUPPORTS_LITTLE_ENDIAN |
424ebcdf | 555 | select SYS_SUPPORTS_MICROMIPS |
47bf2b03 | 556 | select SYS_SUPPORTS_MIPS16 |
e56b6aa6 | 557 | select SYS_SUPPORTS_MIPS_CPS |
f41ae0b2 | 558 | select SYS_SUPPORTS_MULTITHREADING |
47bf2b03 | 559 | select SYS_SUPPORTS_RELOCATABLE |
9693a853 | 560 | select SYS_SUPPORTS_SMARTMIPS |
f35764e7 | 561 | select SYS_SUPPORTS_VPE_LOADER |
1b93b3c3 | 562 | select SYS_SUPPORTS_ZBOOT |
e8823d26 | 563 | select USE_OF |
886ee136 | 564 | select WAR_ICACHE_REFILLS |
abcc82b1 | 565 | select ZONE_DMA32 if 64BIT |
1da177e4 | 566 | help |
f638d197 | 567 | This enables support for the MIPS Technologies Malta evaluation |
1da177e4 LT |
568 | board. |
569 | ||
2572f00d JH |
570 | config MACH_PIC32 |
571 | bool "Microchip PIC32 Family" | |
572 | help | |
573 | This enables support for the Microchip PIC32 family of platforms. | |
574 | ||
575 | Microchip PIC32 is a family of general-purpose 32 bit MIPS core | |
576 | microcontrollers. | |
577 | ||
101bd58f GC |
578 | config MACH_EYEQ5 |
579 | bool "Mobileye EyeQ5 SoC" | |
580 | select MACH_GENERIC_CORE | |
581 | select ARM_AMBA | |
582 | select PHYSICAL_START_BOOL | |
583 | select ARCH_SPARSEMEM_DEFAULT if 64BIT | |
584 | select BOOT_RAW | |
585 | select BUILTIN_DTB | |
586 | select CEVT_R4K | |
587 | select CLKSRC_MIPS_GIC | |
588 | select COMMON_CLK | |
589 | select CPU_MIPSR2_IRQ_EI | |
590 | select CPU_MIPSR2_IRQ_VI | |
591 | select CSRC_R4K | |
592 | select DMA_NONCOHERENT | |
593 | select HAVE_PCI | |
594 | select IRQ_MIPS_CPU | |
595 | select MIPS_AUTO_PFN_OFFSET | |
596 | select MIPS_CPU_SCACHE | |
597 | select MIPS_GIC | |
598 | select MIPS_L1_CACHE_SHIFT_7 | |
599 | select PCI_DRIVERS_GENERIC | |
600 | select SMP_UP if SMP | |
601 | select SWAP_IO_SPACE | |
602 | select SYS_HAS_CPU_MIPS64_R6 | |
603 | select SYS_SUPPORTS_64BIT_KERNEL | |
604 | select SYS_SUPPORTS_HIGHMEM | |
605 | select SYS_SUPPORTS_LITTLE_ENDIAN | |
606 | select SYS_SUPPORTS_MIPS_CPS | |
607 | select SYS_SUPPORTS_RELOCATABLE | |
608 | select SYS_SUPPORTS_ZBOOT | |
609 | select UHI_BOOT | |
610 | select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN | |
611 | select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN | |
612 | select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN | |
613 | select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN | |
614 | select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN | |
615 | select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN | |
616 | select USE_OF | |
617 | help | |
618 | Select this to build a kernel supporting EyeQ5 SoC from Mobileye. | |
619 | ||
620 | bool | |
621 | ||
baec970a LK |
622 | config MACH_NINTENDO64 |
623 | bool "Nintendo 64 console" | |
624 | select CEVT_R4K | |
625 | select CSRC_R4K | |
626 | select SYS_HAS_CPU_R4300 | |
627 | select SYS_SUPPORTS_BIG_ENDIAN | |
628 | select SYS_SUPPORTS_ZBOOT | |
629 | select SYS_SUPPORTS_32BIT_KERNEL | |
630 | select SYS_SUPPORTS_64BIT_KERNEL | |
631 | select DMA_NONCOHERENT | |
632 | select IRQ_MIPS_CPU | |
633 | ||
ae2b5bb6 JC |
634 | config RALINK |
635 | bool "Ralink based machines" | |
636 | select CEVT_R4K | |
35f752be | 637 | select COMMON_CLK |
ae2b5bb6 JC |
638 | select CSRC_R4K |
639 | select BOOT_RAW | |
640 | select DMA_NONCOHERENT | |
67e38cf2 | 641 | select IRQ_MIPS_CPU |
ae2b5bb6 | 642 | select USE_OF |
ae2b5bb6 JC |
643 | select SYS_HAS_CPU_MIPS32_R2 |
644 | select SYS_SUPPORTS_32BIT_KERNEL | |
645 | select SYS_SUPPORTS_LITTLE_ENDIAN | |
377cb1b6 | 646 | select SYS_SUPPORTS_MIPS16 |
1f0400d0 | 647 | select SYS_SUPPORTS_ZBOOT |
ae2b5bb6 | 648 | select SYS_HAS_EARLY_PRINTK |
2a153f1c JC |
649 | select ARCH_HAS_RESET_CONTROLLER |
650 | select RESET_CONTROLLER | |
ae2b5bb6 | 651 | |
4042147a BV |
652 | config MACH_REALTEK_RTL |
653 | bool "Realtek RTL838x/RTL839x based machines" | |
654 | select MIPS_GENERIC | |
80f2e4cd | 655 | select MACH_GENERIC_CORE |
4042147a BV |
656 | select DMA_NONCOHERENT |
657 | select IRQ_MIPS_CPU | |
658 | select CSRC_R4K | |
659 | select CEVT_R4K | |
660 | select SYS_HAS_CPU_MIPS32_R1 | |
661 | select SYS_HAS_CPU_MIPS32_R2 | |
662 | select SYS_SUPPORTS_BIG_ENDIAN | |
663 | select SYS_SUPPORTS_32BIT_KERNEL | |
664 | select SYS_SUPPORTS_MIPS16 | |
665 | select SYS_SUPPORTS_MULTITHREADING | |
666 | select SYS_SUPPORTS_VPE_LOADER | |
4042147a BV |
667 | select BOOT_RAW |
668 | select PINCTRL | |
669 | select USE_OF | |
670 | ||
1da177e4 | 671 | config SGI_IP22 |
3fa986fa | 672 | bool "SGI IP22 (Indy/Indigo2)" |
c0de00b2 | 673 | select ARC_MEMORY |
39b2d756 | 674 | select ARC_PROMLIB |
0e2794b0 RB |
675 | select FW_ARC |
676 | select FW_ARC32 | |
7a407aa5 | 677 | select ARCH_MIGHT_HAVE_PC_SERIO |
1da177e4 | 678 | select BOOT_ELF32 |
42f77542 | 679 | select CEVT_R4K |
940f6b48 | 680 | select CSRC_R4K |
e2defae5 | 681 | select DEFAULT_SGI_PARTITION |
1da177e4 | 682 | select DMA_NONCOHERENT |
6630a8e5 | 683 | select HAVE_EISA |
d865bea4 | 684 | select I8253 |
68de4803 | 685 | select I8259 |
1da177e4 | 686 | select IP22_CPU_SCACHE |
67e38cf2 | 687 | select IRQ_MIPS_CPU |
aa414dff | 688 | select GENERIC_ISA_DMA_SUPPORT_BROKEN |
e2defae5 TB |
689 | select SGI_HAS_I8042 |
690 | select SGI_HAS_INDYDOG | |
36e5c21d | 691 | select SGI_HAS_HAL2 |
e2defae5 TB |
692 | select SGI_HAS_SEEQ |
693 | select SGI_HAS_WD93 | |
694 | select SGI_HAS_ZILOG | |
1da177e4 | 695 | select SWAP_IO_SPACE |
7cf8053b RB |
696 | select SYS_HAS_CPU_R4X00 |
697 | select SYS_HAS_CPU_R5000 | |
c0de00b2 | 698 | select SYS_HAS_EARLY_PRINTK |
ed5ba2fb YY |
699 | select SYS_SUPPORTS_32BIT_KERNEL |
700 | select SYS_SUPPORTS_64BIT_KERNEL | |
5e83d430 | 701 | select SYS_SUPPORTS_BIG_ENDIAN |
802b8362 | 702 | select WAR_R4600_V1_INDEX_ICACHEOP |
5e5b6527 | 703 | select WAR_R4600_V1_HIT_CACHEOP |
44def342 | 704 | select WAR_R4600_V2_HIT_CACHEOP |
930beb5a | 705 | select MIPS_L1_CACHE_SHIFT_7 |
1da177e4 LT |
706 | help |
707 | This are the SGI Indy, Challenge S and Indigo2, as well as certain | |
708 | OEM variants like the Tandem CMN B006S. To compile a Linux kernel | |
709 | that runs on these, say Y here. | |
710 | ||
711 | config SGI_IP27 | |
3fa986fa | 712 | bool "SGI IP27 (Origin200/2000)" |
54aed4dd | 713 | select ARCH_HAS_PHYS_TO_DMA |
397dc00e | 714 | select ARCH_SPARSEMEM_ENABLE |
0e2794b0 RB |
715 | select FW_ARC |
716 | select FW_ARC64 | |
e9422427 | 717 | select ARC_CMDLINE_ONLY |
5e83d430 | 718 | select BOOT_ELF64 |
e2defae5 | 719 | select DEFAULT_SGI_PARTITION |
04100459 | 720 | select FORCE_PCI |
36a88530 | 721 | select SYS_HAS_EARLY_PRINTK |
eb01d42a | 722 | select HAVE_PCI |
69a07a41 | 723 | select IRQ_MIPS_CPU |
e6308b6d | 724 | select IRQ_DOMAIN_HIERARCHY |
130e2fb7 | 725 | select NR_CPUS_DEFAULT_64 |
a57140e9 TB |
726 | select PCI_DRIVERS_GENERIC |
727 | select PCI_XTALK_BRIDGE | |
7cf8053b | 728 | select SYS_HAS_CPU_R10000 |
ed5ba2fb | 729 | select SYS_SUPPORTS_64BIT_KERNEL |
5e83d430 | 730 | select SYS_SUPPORTS_BIG_ENDIAN |
d8cb4e11 | 731 | select SYS_SUPPORTS_NUMA |
1a5c5de1 | 732 | select SYS_SUPPORTS_SMP |
256ec489 | 733 | select WAR_R10000_LLSC |
930beb5a | 734 | select MIPS_L1_CACHE_SHIFT_7 |
6c86a302 | 735 | select NUMA |
f8f9f21c | 736 | select HAVE_ARCH_NODEDATA_EXTENSION |
1da177e4 LT |
737 | help |
738 | This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics | |
739 | workstations. To compile a Linux kernel that runs on these, say Y | |
740 | here. | |
741 | ||
e2defae5 | 742 | config SGI_IP28 |
7d60717e | 743 | bool "SGI IP28 (Indigo2 R10k)" |
c0de00b2 | 744 | select ARC_MEMORY |
39b2d756 | 745 | select ARC_PROMLIB |
0e2794b0 RB |
746 | select FW_ARC |
747 | select FW_ARC64 | |
7a407aa5 | 748 | select ARCH_MIGHT_HAVE_PC_SERIO |
e2defae5 TB |
749 | select BOOT_ELF64 |
750 | select CEVT_R4K | |
751 | select CSRC_R4K | |
752 | select DEFAULT_SGI_PARTITION | |
753 | select DMA_NONCOHERENT | |
754 | select GENERIC_ISA_DMA_SUPPORT_BROKEN | |
67e38cf2 | 755 | select IRQ_MIPS_CPU |
6630a8e5 | 756 | select HAVE_EISA |
e2defae5 TB |
757 | select I8253 |
758 | select I8259 | |
e2defae5 TB |
759 | select SGI_HAS_I8042 |
760 | select SGI_HAS_INDYDOG | |
5b438c44 | 761 | select SGI_HAS_HAL2 |
e2defae5 TB |
762 | select SGI_HAS_SEEQ |
763 | select SGI_HAS_WD93 | |
764 | select SGI_HAS_ZILOG | |
765 | select SWAP_IO_SPACE | |
766 | select SYS_HAS_CPU_R10000 | |
c0de00b2 | 767 | select SYS_HAS_EARLY_PRINTK |
e2defae5 TB |
768 | select SYS_SUPPORTS_64BIT_KERNEL |
769 | select SYS_SUPPORTS_BIG_ENDIAN | |
256ec489 | 770 | select WAR_R10000_LLSC |
dc24d68d | 771 | select MIPS_L1_CACHE_SHIFT_7 |
371a4151 EWI |
772 | help |
773 | This is the SGI Indigo2 with R10000 processor. To compile a Linux | |
774 | kernel that runs on these, say Y here. | |
e2defae5 | 775 | |
7505576d TB |
776 | config SGI_IP30 |
777 | bool "SGI IP30 (Octane/Octane2)" | |
778 | select ARCH_HAS_PHYS_TO_DMA | |
779 | select FW_ARC | |
780 | select FW_ARC64 | |
781 | select BOOT_ELF64 | |
782 | select CEVT_R4K | |
783 | select CSRC_R4K | |
04100459 | 784 | select FORCE_PCI |
7505576d TB |
785 | select SYNC_R4K if SMP |
786 | select ZONE_DMA32 | |
787 | select HAVE_PCI | |
788 | select IRQ_MIPS_CPU | |
789 | select IRQ_DOMAIN_HIERARCHY | |
7505576d TB |
790 | select PCI_DRIVERS_GENERIC |
791 | select PCI_XTALK_BRIDGE | |
792 | select SYS_HAS_EARLY_PRINTK | |
793 | select SYS_HAS_CPU_R10000 | |
794 | select SYS_SUPPORTS_64BIT_KERNEL | |
795 | select SYS_SUPPORTS_BIG_ENDIAN | |
796 | select SYS_SUPPORTS_SMP | |
256ec489 | 797 | select WAR_R10000_LLSC |
7505576d TB |
798 | select MIPS_L1_CACHE_SHIFT_7 |
799 | select ARC_MEMORY | |
800 | help | |
801 | These are the SGI Octane and Octane2 graphics workstations. To | |
802 | compile a Linux kernel that runs on these, say Y here. | |
803 | ||
1da177e4 | 804 | config SGI_IP32 |
cfd2afc0 | 805 | bool "SGI IP32 (O2)" |
39b2d756 TB |
806 | select ARC_MEMORY |
807 | select ARC_PROMLIB | |
03df8229 | 808 | select ARCH_HAS_PHYS_TO_DMA |
0e2794b0 RB |
809 | select FW_ARC |
810 | select FW_ARC32 | |
1da177e4 | 811 | select BOOT_ELF32 |
42f77542 | 812 | select CEVT_R4K |
940f6b48 | 813 | select CSRC_R4K |
1da177e4 | 814 | select DMA_NONCOHERENT |
eb01d42a | 815 | select HAVE_PCI |
67e38cf2 | 816 | select IRQ_MIPS_CPU |
1da177e4 LT |
817 | select R5000_CPU_SCACHE |
818 | select RM7000_CPU_SCACHE | |
7cf8053b RB |
819 | select SYS_HAS_CPU_R5000 |
820 | select SYS_HAS_CPU_R10000 if BROKEN | |
821 | select SYS_HAS_CPU_RM7000 | |
dd2f18fe | 822 | select SYS_HAS_CPU_NEVADA |
ed5ba2fb | 823 | select SYS_SUPPORTS_64BIT_KERNEL |
23fbee9d | 824 | select SYS_SUPPORTS_BIG_ENDIAN |
886ee136 | 825 | select WAR_ICACHE_REFILLS |
23fbee9d | 826 | help |
5e83d430 | 827 | If you want this kernel to run on SGI O2 workstation, say Y here. |
1da177e4 | 828 | |
ade299d8 YY |
829 | config SIBYTE_CRHONE |
830 | bool "Sibyte BCM91125C-CRhone" | |
5e83d430 | 831 | select BOOT_ELF32 |
ade299d8 | 832 | select SIBYTE_BCM1125 |
5e83d430 | 833 | select SWAP_IO_SPACE |
7cf8053b | 834 | select SYS_HAS_CPU_SB1 |
5e83d430 | 835 | select SYS_SUPPORTS_BIG_ENDIAN |
ade299d8 | 836 | select SYS_SUPPORTS_HIGHMEM |
5e83d430 | 837 | select SYS_SUPPORTS_LITTLE_ENDIAN |
1da177e4 | 838 | |
5e83d430 | 839 | config SIBYTE_RHONE |
3fa986fa | 840 | bool "Sibyte BCM91125E-Rhone" |
5e83d430 | 841 | select BOOT_ELF32 |
03452347 | 842 | select SIBYTE_SB1250 |
5e83d430 | 843 | select SWAP_IO_SPACE |
7cf8053b | 844 | select SYS_HAS_CPU_SB1 |
5e83d430 RB |
845 | select SYS_SUPPORTS_BIG_ENDIAN |
846 | select SYS_SUPPORTS_LITTLE_ENDIAN | |
1da177e4 | 847 | |
ade299d8 YY |
848 | config SIBYTE_SWARM |
849 | bool "Sibyte BCM91250A-SWARM" | |
5e83d430 | 850 | select BOOT_ELF32 |
fcf3ca4c | 851 | select HAVE_PATA_PLATFORM |
ade299d8 | 852 | select SIBYTE_SB1250 |
5e83d430 | 853 | select SWAP_IO_SPACE |
7cf8053b | 854 | select SYS_HAS_CPU_SB1 |
5e83d430 | 855 | select SYS_SUPPORTS_BIG_ENDIAN |
ade299d8 | 856 | select SYS_SUPPORTS_HIGHMEM |
e3ad1c23 | 857 | select SYS_SUPPORTS_LITTLE_ENDIAN |
cce335ae | 858 | select ZONE_DMA32 if 64BIT |
e4849aff | 859 | select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI |
e3ad1c23 | 860 | |
ade299d8 YY |
861 | config SIBYTE_LITTLESUR |
862 | bool "Sibyte BCM91250C2-LittleSur" | |
5e83d430 | 863 | select BOOT_ELF32 |
fcf3ca4c | 864 | select HAVE_PATA_PLATFORM |
5e83d430 RB |
865 | select SIBYTE_SB1250 |
866 | select SWAP_IO_SPACE | |
7cf8053b | 867 | select SYS_HAS_CPU_SB1 |
5e83d430 RB |
868 | select SYS_SUPPORTS_BIG_ENDIAN |
869 | select SYS_SUPPORTS_HIGHMEM | |
870 | select SYS_SUPPORTS_LITTLE_ENDIAN | |
756d6d83 | 871 | select ZONE_DMA32 if 64BIT |
1da177e4 | 872 | |
ade299d8 YY |
873 | config SIBYTE_SENTOSA |
874 | bool "Sibyte BCM91250E-Sentosa" | |
5e83d430 | 875 | select BOOT_ELF32 |
5e83d430 RB |
876 | select SIBYTE_SB1250 |
877 | select SWAP_IO_SPACE | |
7cf8053b | 878 | select SYS_HAS_CPU_SB1 |
5e83d430 | 879 | select SYS_SUPPORTS_BIG_ENDIAN |
5e83d430 | 880 | select SYS_SUPPORTS_LITTLE_ENDIAN |
e4849aff | 881 | select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI |
1da177e4 | 882 | |
ade299d8 YY |
883 | config SIBYTE_BIGSUR |
884 | bool "Sibyte BCM91480B-BigSur" | |
5e83d430 | 885 | select BOOT_ELF32 |
ade299d8 | 886 | select NR_CPUS_DEFAULT_4 |
ade299d8 | 887 | select SIBYTE_BCM1x80 |
5e83d430 | 888 | select SWAP_IO_SPACE |
7cf8053b | 889 | select SYS_HAS_CPU_SB1 |
5e83d430 | 890 | select SYS_SUPPORTS_BIG_ENDIAN |
651194f8 | 891 | select SYS_SUPPORTS_HIGHMEM |
5e83d430 | 892 | select SYS_SUPPORTS_LITTLE_ENDIAN |
cce335ae | 893 | select ZONE_DMA32 if 64BIT |
e4849aff | 894 | select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI |
1da177e4 | 895 | |
14b36af4 TB |
896 | config SNI_RM |
897 | bool "SNI RM200/300/400" | |
39b2d756 TB |
898 | select ARC_MEMORY |
899 | select ARC_PROMLIB | |
0e2794b0 RB |
900 | select FW_ARC if CPU_LITTLE_ENDIAN |
901 | select FW_ARC32 if CPU_LITTLE_ENDIAN | |
aaa9fad3 | 902 | select FW_SNIPROM if CPU_BIG_ENDIAN |
61ed242d | 903 | select ARCH_MAY_HAVE_PC_FDC |
a211a082 | 904 | select ARCH_MIGHT_HAVE_PC_PARPORT |
7a407aa5 | 905 | select ARCH_MIGHT_HAVE_PC_SERIO |
1da177e4 | 906 | select BOOT_ELF32 |
42f77542 | 907 | select CEVT_R4K |
940f6b48 | 908 | select CSRC_R4K |
e2defae5 | 909 | select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN |
1da177e4 LT |
910 | select DMA_NONCOHERENT |
911 | select GENERIC_ISA_DMA | |
6630a8e5 | 912 | select HAVE_EISA |
8a118c38 | 913 | select HAVE_PCSPKR_PLATFORM |
eb01d42a | 914 | select HAVE_PCI |
67e38cf2 | 915 | select IRQ_MIPS_CPU |
d865bea4 | 916 | select I8253 |
1da177e4 LT |
917 | select I8259 |
918 | select ISA | |
564c836f | 919 | select MIPS_L1_CACHE_SHIFT_6 |
4a0312fc | 920 | select SWAP_IO_SPACE if CPU_BIG_ENDIAN |
7cf8053b | 921 | select SYS_HAS_CPU_R4X00 |
4a0312fc | 922 | select SYS_HAS_CPU_R5000 |
c066a32a | 923 | select SYS_HAS_CPU_R10000 |
4a0312fc | 924 | select R5000_CPU_SCACHE |
36a88530 | 925 | select SYS_HAS_EARLY_PRINTK |
ed5ba2fb | 926 | select SYS_SUPPORTS_32BIT_KERNEL |
7d60717e | 927 | select SYS_SUPPORTS_64BIT_KERNEL |
4a0312fc | 928 | select SYS_SUPPORTS_BIG_ENDIAN |
797798c1 | 929 | select SYS_SUPPORTS_HIGHMEM |
5e83d430 | 930 | select SYS_SUPPORTS_LITTLE_ENDIAN |
44def342 | 931 | select WAR_R4600_V2_HIT_CACHEOP |
1da177e4 | 932 | help |
14b36af4 TB |
933 | The SNI RM200/300/400 are MIPS-based machines manufactured by |
934 | Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid | |
1da177e4 LT |
935 | Technology and now in turn merged with Fujitsu. Say Y here to |
936 | support this machine type. | |
937 | ||
edcaf1a6 AN |
938 | config MACH_TX49XX |
939 | bool "Toshiba TX49 series based machines" | |
24a1c023 | 940 | select WAR_TX49XX_ICACHE_INDEX_INV |
5e83d430 | 941 | |
73b4390f RB |
942 | config MIKROTIK_RB532 |
943 | bool "Mikrotik RB532 boards" | |
944 | select CEVT_R4K | |
945 | select CSRC_R4K | |
946 | select DMA_NONCOHERENT | |
eb01d42a | 947 | select HAVE_PCI |
67e38cf2 | 948 | select IRQ_MIPS_CPU |
73b4390f RB |
949 | select SYS_HAS_CPU_MIPS32_R1 |
950 | select SYS_SUPPORTS_32BIT_KERNEL | |
951 | select SYS_SUPPORTS_LITTLE_ENDIAN | |
952 | select SWAP_IO_SPACE | |
953 | select BOOT_RAW | |
d30a2b47 | 954 | select GPIOLIB |
930beb5a | 955 | select MIPS_L1_CACHE_SHIFT_4 |
73b4390f RB |
956 | help |
957 | Support the Mikrotik(tm) RouterBoard 532 series, | |
958 | based on the IDT RC32434 SoC. | |
959 | ||
9ddebc46 DD |
960 | config CAVIUM_OCTEON_SOC |
961 | bool "Cavium Networks Octeon SoC based boards" | |
a86c7f72 | 962 | select CEVT_R4K |
ea8c64ac | 963 | select ARCH_HAS_PHYS_TO_DMA |
1753d50c | 964 | select HAVE_RAPIDIO |
d4a451d5 | 965 | select PHYS_ADDR_T_64BIT |
a86c7f72 DD |
966 | select SYS_SUPPORTS_64BIT_KERNEL |
967 | select SYS_SUPPORTS_BIG_ENDIAN | |
f65aad41 | 968 | select EDAC_SUPPORT |
b01aec9b | 969 | select EDAC_ATOMIC_SCRUB |
73569d87 DD |
970 | select SYS_SUPPORTS_LITTLE_ENDIAN |
971 | select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN | |
a86c7f72 | 972 | select SYS_HAS_EARLY_PRINTK |
5e683389 | 973 | select SYS_HAS_CPU_CAVIUM_OCTEON |
eb01d42a | 974 | select HAVE_PCI |
78bdbbac MY |
975 | select HAVE_PLAT_DELAY |
976 | select HAVE_PLAT_FW_INIT_CMDLINE | |
977 | select HAVE_PLAT_MEMCPY | |
f00e001e | 978 | select ZONE_DMA32 |
d30a2b47 | 979 | select GPIOLIB |
6e511163 DD |
980 | select USE_OF |
981 | select ARCH_SPARSEMEM_ENABLE | |
982 | select SYS_SUPPORTS_SMP | |
7820b84b DD |
983 | select NR_CPUS_DEFAULT_64 |
984 | select MIPS_NR_CPU_NR_MAP_1024 | |
e326479f | 985 | select BUILTIN_DTB |
f766b28a | 986 | select MTD |
8c1e6b14 | 987 | select MTD_COMPLEX_MAPPINGS |
09230cbc | 988 | select SWIOTLB |
3ff72be4 | 989 | select SYS_SUPPORTS_RELOCATABLE |
a86c7f72 DD |
990 | help |
991 | This option supports all of the Octeon reference boards from Cavium | |
992 | Networks. It builds a kernel that dynamically determines the Octeon | |
993 | CPU type and supports all known board reference implementations. | |
994 | Some of the supported boards are: | |
995 | EBT3000 | |
996 | EBH3000 | |
997 | EBH3100 | |
998 | Thunder | |
999 | Kodama | |
1000 | Hikari | |
1001 | Say Y here for most Octeon reference boards. | |
1002 | ||
5e83d430 | 1003 | endchoice |
1da177e4 | 1004 | |
9a88b338 MY |
1005 | config FIT_IMAGE_FDT_EPM5 |
1006 | bool "Include FDT for Mobileye EyeQ5 development platforms" | |
1007 | depends on MACH_EYEQ5 | |
1008 | default n | |
1009 | help | |
1010 | Enable this to include the FDT for the EyeQ5 development platforms | |
1011 | from Mobileye in the FIT kernel image. | |
1012 | This requires u-boot on the platform. | |
1013 | ||
e8c7c482 | 1014 | source "arch/mips/alchemy/Kconfig" |
3b12308f | 1015 | source "arch/mips/ath25/Kconfig" |
d4a67d9d | 1016 | source "arch/mips/ath79/Kconfig" |
a656ffcb | 1017 | source "arch/mips/bcm47xx/Kconfig" |
e7300d04 | 1018 | source "arch/mips/bcm63xx/Kconfig" |
8945e37e | 1019 | source "arch/mips/bmips/Kconfig" |
eed0eabd | 1020 | source "arch/mips/generic/Kconfig" |
a103e9b9 | 1021 | source "arch/mips/ingenic/Kconfig" |
5e83d430 | 1022 | source "arch/mips/jazz/Kconfig" |
8ec6d935 | 1023 | source "arch/mips/lantiq/Kconfig" |
2572f00d | 1024 | source "arch/mips/pic32/Kconfig" |
ae2b5bb6 | 1025 | source "arch/mips/ralink/Kconfig" |
29c48699 | 1026 | source "arch/mips/sgi-ip27/Kconfig" |
38b18f72 | 1027 | source "arch/mips/sibyte/Kconfig" |
22b1d707 | 1028 | source "arch/mips/txx9/Kconfig" |
a86c7f72 | 1029 | source "arch/mips/cavium-octeon/Kconfig" |
71e2f4dd | 1030 | source "arch/mips/loongson2ef/Kconfig" |
30ad29bb HC |
1031 | source "arch/mips/loongson32/Kconfig" |
1032 | source "arch/mips/loongson64/Kconfig" | |
38b18f72 | 1033 | |
5e83d430 RB |
1034 | endmenu |
1035 | ||
3c9ee7ef AM |
1036 | config GENERIC_HWEIGHT |
1037 | bool | |
1038 | default y | |
1039 | ||
1da177e4 LT |
1040 | config GENERIC_CALIBRATE_DELAY |
1041 | bool | |
1042 | default y | |
1043 | ||
ae1e9130 | 1044 | config SCHED_OMIT_FRAME_POINTER |
1cc89038 AN |
1045 | bool |
1046 | default y | |
1047 | ||
1da177e4 LT |
1048 | # |
1049 | # Select some configuration options automatically based on user selections. | |
1050 | # | |
0e2794b0 | 1051 | config FW_ARC |
1da177e4 | 1052 | bool |
1da177e4 | 1053 | |
61ed242d RB |
1054 | config ARCH_MAY_HAVE_PC_FDC |
1055 | bool | |
1056 | ||
9267a30d MSJ |
1057 | config BOOT_RAW |
1058 | bool | |
1059 | ||
217dd11e RB |
1060 | config CEVT_BCM1480 |
1061 | bool | |
1062 | ||
6457d9fc YY |
1063 | config CEVT_DS1287 |
1064 | bool | |
1065 | ||
1097c6ac YY |
1066 | config CEVT_GT641XX |
1067 | bool | |
1068 | ||
42f77542 RB |
1069 | config CEVT_R4K |
1070 | bool | |
1071 | ||
217dd11e RB |
1072 | config CEVT_SB1250 |
1073 | bool | |
1074 | ||
229f773e AN |
1075 | config CEVT_TXX9 |
1076 | bool | |
1077 | ||
217dd11e RB |
1078 | config CSRC_BCM1480 |
1079 | bool | |
1080 | ||
4247417d YY |
1081 | config CSRC_IOASIC |
1082 | bool | |
1083 | ||
940f6b48 | 1084 | config CSRC_R4K |
38586428 | 1085 | select CLOCKSOURCE_WATCHDOG if CPU_FREQ |
940f6b48 RB |
1086 | bool |
1087 | ||
217dd11e RB |
1088 | config CSRC_SB1250 |
1089 | bool | |
1090 | ||
a7f4df4e AS |
1091 | config MIPS_CLOCK_VSYSCALL |
1092 | def_bool CSRC_R4K || CLKSRC_MIPS_GIC | |
1093 | ||
a9aec7fe | 1094 | config GPIO_TXX9 |
d30a2b47 | 1095 | select GPIOLIB |
a9aec7fe AN |
1096 | bool |
1097 | ||
0e2794b0 | 1098 | config FW_CFE |
df78b5c8 AJ |
1099 | bool |
1100 | ||
40e084a5 | 1101 | config ARCH_SUPPORTS_UPROBES |
f5748b8c | 1102 | def_bool y |
40e084a5 | 1103 | |
4ce588cd RB |
1104 | config DMA_NONCOHERENT |
1105 | bool | |
db91427b CH |
1106 | # |
1107 | # MIPS allows mixing "slightly different" Cacheability and Coherency | |
1108 | # Attribute bits. It is believed that the uncached access through | |
1109 | # KSEG1 and the implementation specific "uncached accelerated" used | |
1110 | # by pgprot_writcombine can be mixed, and the latter sometimes provides | |
1111 | # significant advantages. | |
1112 | # | |
6be87d61 | 1113 | select ARCH_HAS_SETUP_DMA_OPS |
419e2f18 | 1114 | select ARCH_HAS_DMA_WRITE_COMBINE |
fa7e2247 | 1115 | select ARCH_HAS_DMA_PREP_COHERENT |
e0b7fd12 | 1116 | select ARCH_HAS_SYNC_DMA_FOR_CPU |
f8c55dc6 | 1117 | select ARCH_HAS_SYNC_DMA_FOR_DEVICE |
fa7e2247 | 1118 | select ARCH_HAS_DMA_SET_UNCACHED |
34dc0ea6 | 1119 | select DMA_NONCOHERENT_MMAP |
34dc0ea6 | 1120 | select NEED_DMA_MAP_STATE |
4ce588cd | 1121 | |
36a88530 | 1122 | config SYS_HAS_EARLY_PRINTK |
1da177e4 | 1123 | bool |
1da177e4 | 1124 | |
1b2bc75c | 1125 | config SYS_SUPPORTS_HOTPLUG_CPU |
dbb74540 | 1126 | bool |
dbb74540 | 1127 | |
1da177e4 LT |
1128 | config MIPS_BONITO64 |
1129 | bool | |
1da177e4 LT |
1130 | |
1131 | config MIPS_MSC | |
1132 | bool | |
1da177e4 | 1133 | |
39b8d525 RB |
1134 | config SYNC_R4K |
1135 | bool | |
1136 | ||
ce816fa8 | 1137 | config NO_IOPORT_MAP |
d388d685 MR |
1138 | def_bool n |
1139 | ||
4e0748f5 | 1140 | config GENERIC_CSUM |
18d84e2e | 1141 | def_bool CPU_NO_LOAD_STORE_LR |
4e0748f5 | 1142 | |
8313da30 RB |
1143 | config GENERIC_ISA_DMA |
1144 | bool | |
1145 | select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n | |
a35bee8a | 1146 | select ISA_DMA_API |
8313da30 | 1147 | |
aa414dff RB |
1148 | config GENERIC_ISA_DMA_SUPPORT_BROKEN |
1149 | bool | |
8313da30 | 1150 | select GENERIC_ISA_DMA |
aa414dff | 1151 | |
78bdbbac MY |
1152 | config HAVE_PLAT_DELAY |
1153 | bool | |
1154 | ||
1155 | config HAVE_PLAT_FW_INIT_CMDLINE | |
1156 | bool | |
1157 | ||
1158 | config HAVE_PLAT_MEMCPY | |
1159 | bool | |
1160 | ||
a35bee8a NK |
1161 | config ISA_DMA_API |
1162 | bool | |
1163 | ||
8c530ea3 MR |
1164 | config SYS_SUPPORTS_RELOCATABLE |
1165 | bool | |
1166 | help | |
371a4151 EWI |
1167 | Selected if the platform supports relocating the kernel. |
1168 | The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF | |
1169 | to allow access to command line and entropy sources. | |
8c530ea3 | 1170 | |
5e83d430 | 1171 | # |
6b2aac42 | 1172 | # Endianness selection. Sufficiently obscure so many users don't know what to |
5e83d430 RB |
1173 | # answer,so we try hard to limit the available choices. Also the use of a |
1174 | # choice statement should be more obvious to the user. | |
1175 | # | |
1176 | choice | |
6b2aac42 | 1177 | prompt "Endianness selection" |
1da177e4 LT |
1178 | help |
1179 | Some MIPS machines can be configured for either little or big endian | |
5e83d430 | 1180 | byte order. These modes require different kernels and a different |
3cb2fccc | 1181 | Linux distribution. In general there is one preferred byteorder for a |
5e83d430 | 1182 | particular system but some systems are just as commonly used in the |
3dde6ad8 | 1183 | one or the other endianness. |
5e83d430 RB |
1184 | |
1185 | config CPU_BIG_ENDIAN | |
1186 | bool "Big endian" | |
1187 | depends on SYS_SUPPORTS_BIG_ENDIAN | |
1188 | ||
1189 | config CPU_LITTLE_ENDIAN | |
1190 | bool "Little endian" | |
1191 | depends on SYS_SUPPORTS_LITTLE_ENDIAN | |
5e83d430 RB |
1192 | |
1193 | endchoice | |
1194 | ||
22b0763a DD |
1195 | config EXPORT_UASM |
1196 | bool | |
1197 | ||
2116245e RB |
1198 | config SYS_SUPPORTS_APM_EMULATION |
1199 | bool | |
1200 | ||
5e83d430 RB |
1201 | config SYS_SUPPORTS_BIG_ENDIAN |
1202 | bool | |
1203 | ||
1204 | config SYS_SUPPORTS_LITTLE_ENDIAN | |
1205 | bool | |
1da177e4 | 1206 | |
aa1762f4 DD |
1207 | config MIPS_HUGE_TLB_SUPPORT |
1208 | def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE | |
1209 | ||
8420fd00 AN |
1210 | config IRQ_TXX9 |
1211 | bool | |
1212 | ||
d5ab1a69 YY |
1213 | config IRQ_GT641XX |
1214 | bool | |
1215 | ||
252161ec | 1216 | config PCI_GT64XXX_PCI0 |
1da177e4 | 1217 | bool |
1da177e4 | 1218 | |
a57140e9 TB |
1219 | config PCI_XTALK_BRIDGE |
1220 | bool | |
1221 | ||
9267a30d MSJ |
1222 | config NO_EXCEPT_FILL |
1223 | bool | |
1224 | ||
a7e07b1a MC |
1225 | config MIPS_SPRAM |
1226 | bool | |
1227 | ||
1da177e4 LT |
1228 | config SWAP_IO_SPACE |
1229 | bool | |
1230 | ||
e2defae5 TB |
1231 | config SGI_HAS_INDYDOG |
1232 | bool | |
1233 | ||
5b438c44 TB |
1234 | config SGI_HAS_HAL2 |
1235 | bool | |
1236 | ||
e2defae5 TB |
1237 | config SGI_HAS_SEEQ |
1238 | bool | |
1239 | ||
1240 | config SGI_HAS_WD93 | |
1241 | bool | |
1242 | ||
1243 | config SGI_HAS_ZILOG | |
1244 | bool | |
1245 | ||
1246 | config SGI_HAS_I8042 | |
1247 | bool | |
1248 | ||
1249 | config DEFAULT_SGI_PARTITION | |
1250 | bool | |
1251 | ||
0e2794b0 | 1252 | config FW_ARC32 |
5e83d430 RB |
1253 | bool |
1254 | ||
aaa9fad3 | 1255 | config FW_SNIPROM |
231a35d3 TB |
1256 | bool |
1257 | ||
1da177e4 LT |
1258 | config BOOT_ELF32 |
1259 | bool | |
1da177e4 | 1260 | |
930beb5a FF |
1261 | config MIPS_L1_CACHE_SHIFT_4 |
1262 | bool | |
1263 | ||
1264 | config MIPS_L1_CACHE_SHIFT_5 | |
1265 | bool | |
1266 | ||
1267 | config MIPS_L1_CACHE_SHIFT_6 | |
1268 | bool | |
1269 | ||
1270 | config MIPS_L1_CACHE_SHIFT_7 | |
1271 | bool | |
1272 | ||
1da177e4 LT |
1273 | config MIPS_L1_CACHE_SHIFT |
1274 | int | |
a4c0201e | 1275 | default "7" if MIPS_L1_CACHE_SHIFT_7 |
5432eeb6 KC |
1276 | default "6" if MIPS_L1_CACHE_SHIFT_6 |
1277 | default "5" if MIPS_L1_CACHE_SHIFT_5 | |
1278 | default "4" if MIPS_L1_CACHE_SHIFT_4 | |
1da177e4 LT |
1279 | default "5" |
1280 | ||
e9422427 TB |
1281 | config ARC_CMDLINE_ONLY |
1282 | bool | |
1283 | ||
1da177e4 LT |
1284 | config ARC_CONSOLE |
1285 | bool "ARC console support" | |
e2defae5 | 1286 | depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN) |
1da177e4 LT |
1287 | |
1288 | config ARC_MEMORY | |
1289 | bool | |
1da177e4 LT |
1290 | |
1291 | config ARC_PROMLIB | |
1292 | bool | |
1da177e4 | 1293 | |
0e2794b0 | 1294 | config FW_ARC64 |
1da177e4 | 1295 | bool |
1da177e4 LT |
1296 | |
1297 | config BOOT_ELF64 | |
1298 | bool | |
1da177e4 | 1299 | |
1da177e4 LT |
1300 | menu "CPU selection" |
1301 | ||
1302 | choice | |
1303 | prompt "CPU type" | |
1304 | default CPU_R4X00 | |
1305 | ||
268a2d60 | 1306 | config CPU_LOONGSON64 |
caed1d1b | 1307 | bool "Loongson 64-bit CPU" |
268a2d60 | 1308 | depends on SYS_HAS_CPU_LOONGSON64 |
d3bc81be | 1309 | select ARCH_HAS_PHYS_TO_DMA |
51522217 JY |
1310 | select CPU_MIPSR2 |
1311 | select CPU_HAS_PREFETCH | |
0e476d91 HC |
1312 | select CPU_SUPPORTS_64BIT_KERNEL |
1313 | select CPU_SUPPORTS_HIGHMEM | |
1314 | select CPU_SUPPORTS_HUGEPAGES | |
7507445b | 1315 | select CPU_SUPPORTS_MSA |
a6d54338 | 1316 | select CPU_SUPPORTS_VZ |
51522217 JY |
1317 | select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT |
1318 | select CPU_MIPSR2_IRQ_VI | |
edc0378e | 1319 | select DMA_NONCOHERENT |
0e476d91 HC |
1320 | select WEAK_ORDERING |
1321 | select WEAK_REORDERING_BEYOND_LLSC | |
7507445b | 1322 | select MIPS_ASID_BITS_VARIABLE |
b2edcfc8 | 1323 | select MIPS_PGD_C0_CONTEXT |
17c99d94 | 1324 | select MIPS_L1_CACHE_SHIFT_6 |
7f3b3c2b | 1325 | select MIPS_FP_SUPPORT |
d30a2b47 | 1326 | select GPIOLIB |
09230cbc | 1327 | select SWIOTLB |
0e476d91 | 1328 | help |
31f12fdc JH |
1329 | The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor |
1330 | cores implements the MIPS64R2 instruction set with many extensions, | |
1331 | including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000, | |
1332 | 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old | |
1333 | Loongson-2E/2F is not covered here and will be removed in future. | |
caed1d1b | 1334 | |
3702bba5 WZ |
1335 | config CPU_LOONGSON2E |
1336 | bool "Loongson 2E" | |
1337 | depends on SYS_HAS_CPU_LOONGSON2E | |
268a2d60 | 1338 | select CPU_LOONGSON2EF |
2a21c730 FZ |
1339 | help |
1340 | The Loongson 2E processor implements the MIPS III instruction set | |
1341 | with many extensions. | |
1342 | ||
25985edc | 1343 | It has an internal FPGA northbridge, which is compatible to |
6f7a251a WZ |
1344 | bonito64. |
1345 | ||
1346 | config CPU_LOONGSON2F | |
1347 | bool "Loongson 2F" | |
1348 | depends on SYS_HAS_CPU_LOONGSON2F | |
268a2d60 | 1349 | select CPU_LOONGSON2EF |
6f7a251a WZ |
1350 | help |
1351 | The Loongson 2F processor implements the MIPS III instruction set | |
1352 | with many extensions. | |
1353 | ||
1354 | Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller | |
1355 | have a similar programming interface with FPGA northbridge used in | |
1356 | Loongson2E. | |
1357 | ||
ca585cf9 KC |
1358 | config CPU_LOONGSON1B |
1359 | bool "Loongson 1B" | |
1360 | depends on SYS_HAS_CPU_LOONGSON1B | |
b2afb64c | 1361 | select CPU_LOONGSON32 |
9ec88b60 | 1362 | select LEDS_GPIO_REGISTER |
ca585cf9 KC |
1363 | help |
1364 | The Loongson 1B is a 32-bit SoC, which implements the MIPS32 | |
968dc5a0 XZ |
1365 | Release 1 instruction set and part of the MIPS32 Release 2 |
1366 | instruction set. | |
ca585cf9 | 1367 | |
12e3280b YL |
1368 | config CPU_LOONGSON1C |
1369 | bool "Loongson 1C" | |
1370 | depends on SYS_HAS_CPU_LOONGSON1C | |
b2afb64c | 1371 | select CPU_LOONGSON32 |
12e3280b YL |
1372 | select LEDS_GPIO_REGISTER |
1373 | help | |
1374 | The Loongson 1C is a 32-bit SoC, which implements the MIPS32 | |
968dc5a0 XZ |
1375 | Release 1 instruction set and part of the MIPS32 Release 2 |
1376 | instruction set. | |
12e3280b | 1377 | |
6e760c8d RB |
1378 | config CPU_MIPS32_R1 |
1379 | bool "MIPS32 Release 1" | |
7cf8053b | 1380 | depends on SYS_HAS_CPU_MIPS32_R1 |
6e760c8d | 1381 | select CPU_HAS_PREFETCH |
797798c1 | 1382 | select CPU_SUPPORTS_32BIT_KERNEL |
ec28f306 | 1383 | select CPU_SUPPORTS_HIGHMEM |
1e5f1caa | 1384 | help |
5e83d430 | 1385 | Choose this option to build a kernel for release 1 or later of the |
1e5f1caa RB |
1386 | MIPS32 architecture. Most modern embedded systems with a 32-bit |
1387 | MIPS processor are based on a MIPS32 processor. If you know the | |
1388 | specific type of processor in your system, choose those that one | |
1389 | otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system. | |
1390 | Release 2 of the MIPS32 architecture is available since several | |
1391 | years so chances are you even have a MIPS32 Release 2 processor | |
1392 | in which case you should choose CPU_MIPS32_R2 instead for better | |
1393 | performance. | |
1394 | ||
1395 | config CPU_MIPS32_R2 | |
1396 | bool "MIPS32 Release 2" | |
7cf8053b | 1397 | depends on SYS_HAS_CPU_MIPS32_R2 |
1e5f1caa | 1398 | select CPU_HAS_PREFETCH |
797798c1 | 1399 | select CPU_SUPPORTS_32BIT_KERNEL |
ec28f306 | 1400 | select CPU_SUPPORTS_HIGHMEM |
a5e9a69e | 1401 | select CPU_SUPPORTS_MSA |
6e760c8d | 1402 | help |
5e83d430 | 1403 | Choose this option to build a kernel for release 2 or later of the |
6e760c8d RB |
1404 | MIPS32 architecture. Most modern embedded systems with a 32-bit |
1405 | MIPS processor are based on a MIPS32 processor. If you know the | |
1406 | specific type of processor in your system, choose those that one | |
1407 | otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system. | |
1408 | ||
ab7c01fd SS |
1409 | config CPU_MIPS32_R5 |
1410 | bool "MIPS32 Release 5" | |
1411 | depends on SYS_HAS_CPU_MIPS32_R5 | |
1412 | select CPU_HAS_PREFETCH | |
1413 | select CPU_SUPPORTS_32BIT_KERNEL | |
1414 | select CPU_SUPPORTS_HIGHMEM | |
1415 | select CPU_SUPPORTS_MSA | |
a6d54338 | 1416 | select CPU_SUPPORTS_VZ |
ab7c01fd SS |
1417 | select MIPS_O32_FP64_SUPPORT |
1418 | help | |
1419 | Choose this option to build a kernel for release 5 or later of the | |
1420 | MIPS32 architecture. New MIPS processors, starting with the Warrior | |
1421 | family, are based on a MIPS32r5 processor. If you own an older | |
1422 | processor, you probably need to select MIPS32r1 or MIPS32r2 instead. | |
1423 | ||
7fd08ca5 | 1424 | config CPU_MIPS32_R6 |
674d10e2 | 1425 | bool "MIPS32 Release 6" |
7fd08ca5 LY |
1426 | depends on SYS_HAS_CPU_MIPS32_R6 |
1427 | select CPU_HAS_PREFETCH | |
18d84e2e | 1428 | select CPU_NO_LOAD_STORE_LR |
7fd08ca5 LY |
1429 | select CPU_SUPPORTS_32BIT_KERNEL |
1430 | select CPU_SUPPORTS_HIGHMEM | |
1431 | select CPU_SUPPORTS_MSA | |
a6d54338 | 1432 | select CPU_SUPPORTS_VZ |
7fd08ca5 LY |
1433 | select MIPS_O32_FP64_SUPPORT |
1434 | help | |
1435 | Choose this option to build a kernel for release 6 or later of the | |
1436 | MIPS32 architecture. New MIPS processors, starting with the Warrior | |
1437 | family, are based on a MIPS32r6 processor. If you own an older | |
1438 | processor, you probably need to select MIPS32r1 or MIPS32r2 instead. | |
1439 | ||
6e760c8d RB |
1440 | config CPU_MIPS64_R1 |
1441 | bool "MIPS64 Release 1" | |
7cf8053b | 1442 | depends on SYS_HAS_CPU_MIPS64_R1 |
797798c1 | 1443 | select CPU_HAS_PREFETCH |
ed5ba2fb YY |
1444 | select CPU_SUPPORTS_32BIT_KERNEL |
1445 | select CPU_SUPPORTS_64BIT_KERNEL | |
ec28f306 | 1446 | select CPU_SUPPORTS_HIGHMEM |
9cffd154 | 1447 | select CPU_SUPPORTS_HUGEPAGES |
6e760c8d RB |
1448 | help |
1449 | Choose this option to build a kernel for release 1 or later of the | |
1450 | MIPS64 architecture. Many modern embedded systems with a 64-bit | |
1451 | MIPS processor are based on a MIPS64 processor. If you know the | |
1452 | specific type of processor in your system, choose those that one | |
1453 | otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system. | |
1e5f1caa RB |
1454 | Release 2 of the MIPS64 architecture is available since several |
1455 | years so chances are you even have a MIPS64 Release 2 processor | |
1456 | in which case you should choose CPU_MIPS64_R2 instead for better | |
1457 | performance. | |
1458 | ||
1459 | config CPU_MIPS64_R2 | |
1460 | bool "MIPS64 Release 2" | |
7cf8053b | 1461 | depends on SYS_HAS_CPU_MIPS64_R2 |
797798c1 | 1462 | select CPU_HAS_PREFETCH |
1e5f1caa RB |
1463 | select CPU_SUPPORTS_32BIT_KERNEL |
1464 | select CPU_SUPPORTS_64BIT_KERNEL | |
ec28f306 | 1465 | select CPU_SUPPORTS_HIGHMEM |
9cffd154 | 1466 | select CPU_SUPPORTS_HUGEPAGES |
a5e9a69e | 1467 | select CPU_SUPPORTS_MSA |
1e5f1caa RB |
1468 | help |
1469 | Choose this option to build a kernel for release 2 or later of the | |
1470 | MIPS64 architecture. Many modern embedded systems with a 64-bit | |
1471 | MIPS processor are based on a MIPS64 processor. If you know the | |
1472 | specific type of processor in your system, choose those that one | |
1473 | otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system. | |
1da177e4 | 1474 | |
ab7c01fd SS |
1475 | config CPU_MIPS64_R5 |
1476 | bool "MIPS64 Release 5" | |
1477 | depends on SYS_HAS_CPU_MIPS64_R5 | |
1478 | select CPU_HAS_PREFETCH | |
1479 | select CPU_SUPPORTS_32BIT_KERNEL | |
1480 | select CPU_SUPPORTS_64BIT_KERNEL | |
1481 | select CPU_SUPPORTS_HIGHMEM | |
1482 | select CPU_SUPPORTS_HUGEPAGES | |
1483 | select CPU_SUPPORTS_MSA | |
1484 | select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32 | |
a6d54338 | 1485 | select CPU_SUPPORTS_VZ |
ab7c01fd SS |
1486 | help |
1487 | Choose this option to build a kernel for release 5 or later of the | |
1488 | MIPS64 architecture. This is a intermediate MIPS architecture | |
1489 | release partly implementing release 6 features. Though there is no | |
1490 | any hardware known to be based on this release. | |
1491 | ||
7fd08ca5 | 1492 | config CPU_MIPS64_R6 |
674d10e2 | 1493 | bool "MIPS64 Release 6" |
7fd08ca5 LY |
1494 | depends on SYS_HAS_CPU_MIPS64_R6 |
1495 | select CPU_HAS_PREFETCH | |
18d84e2e | 1496 | select CPU_NO_LOAD_STORE_LR |
7fd08ca5 LY |
1497 | select CPU_SUPPORTS_32BIT_KERNEL |
1498 | select CPU_SUPPORTS_64BIT_KERNEL | |
1499 | select CPU_SUPPORTS_HIGHMEM | |
afd375dc | 1500 | select CPU_SUPPORTS_HUGEPAGES |
7fd08ca5 | 1501 | select CPU_SUPPORTS_MSA |
2e6c7747 | 1502 | select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32 |
a6d54338 | 1503 | select CPU_SUPPORTS_VZ |
7fd08ca5 LY |
1504 | help |
1505 | Choose this option to build a kernel for release 6 or later of the | |
1506 | MIPS64 architecture. New MIPS processors, starting with the Warrior | |
1507 | family, are based on a MIPS64r6 processor. If you own an older | |
1508 | processor, you probably need to select MIPS64r1 or MIPS64r2 instead. | |
1509 | ||
281e3aea SS |
1510 | config CPU_P5600 |
1511 | bool "MIPS Warrior P5600" | |
1512 | depends on SYS_HAS_CPU_P5600 | |
1513 | select CPU_HAS_PREFETCH | |
1514 | select CPU_SUPPORTS_32BIT_KERNEL | |
1515 | select CPU_SUPPORTS_HIGHMEM | |
1516 | select CPU_SUPPORTS_MSA | |
281e3aea | 1517 | select CPU_SUPPORTS_CPUFREQ |
a6d54338 | 1518 | select CPU_SUPPORTS_VZ |
281e3aea SS |
1519 | select CPU_MIPSR2_IRQ_VI |
1520 | select CPU_MIPSR2_IRQ_EI | |
281e3aea SS |
1521 | select MIPS_O32_FP64_SUPPORT |
1522 | help | |
1523 | Choose this option to build a kernel for MIPS Warrior P5600 CPU. | |
1524 | It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes, | |
1525 | MMU with two-levels TLB, UCA, MSA, MDU core level features and system | |
1526 | level features like up to six P5600 calculation cores, CM2 with L2 | |
1527 | cache, IOCU/IOMMU (though might be unused depending on the system- | |
1528 | specific IP core configuration), GIC, CPC, virtualisation module, | |
1529 | eJTAG and PDtrace. | |
1530 | ||
1da177e4 LT |
1531 | config CPU_R3000 |
1532 | bool "R3000" | |
7cf8053b | 1533 | depends on SYS_HAS_CPU_R3000 |
f7062ddb | 1534 | select CPU_HAS_WB |
54746829 | 1535 | select CPU_R3K_TLB |
ed5ba2fb | 1536 | select CPU_SUPPORTS_32BIT_KERNEL |
797798c1 | 1537 | select CPU_SUPPORTS_HIGHMEM |
1da177e4 LT |
1538 | help |
1539 | Please make sure to pick the right CPU type. Linux/MIPS is not | |
1540 | designed to be generic, i.e. Kernels compiled for R3000 CPUs will | |
1541 | *not* work on R4000 machines and vice versa. However, since most | |
1542 | of the supported machines have an R4000 (or similar) CPU, R4x00 | |
1543 | might be a safe bet. If the resulting kernel does not work, | |
1544 | try to recompile with R3000. | |
1545 | ||
65ce6197 LK |
1546 | config CPU_R4300 |
1547 | bool "R4300" | |
1548 | depends on SYS_HAS_CPU_R4300 | |
1549 | select CPU_SUPPORTS_32BIT_KERNEL | |
1550 | select CPU_SUPPORTS_64BIT_KERNEL | |
65ce6197 LK |
1551 | help |
1552 | MIPS Technologies R4300-series processors. | |
1553 | ||
1da177e4 LT |
1554 | config CPU_R4X00 |
1555 | bool "R4x00" | |
7cf8053b | 1556 | depends on SYS_HAS_CPU_R4X00 |
ed5ba2fb YY |
1557 | select CPU_SUPPORTS_32BIT_KERNEL |
1558 | select CPU_SUPPORTS_64BIT_KERNEL | |
970d032f | 1559 | select CPU_SUPPORTS_HUGEPAGES |
1da177e4 LT |
1560 | help |
1561 | MIPS Technologies R4000-series processors other than 4300, including | |
1562 | the R4000, R4400, R4600, and 4700. | |
1563 | ||
1564 | config CPU_TX49XX | |
1565 | bool "R49XX" | |
7cf8053b | 1566 | depends on SYS_HAS_CPU_TX49XX |
de862b48 | 1567 | select CPU_HAS_PREFETCH |
ed5ba2fb YY |
1568 | select CPU_SUPPORTS_32BIT_KERNEL |
1569 | select CPU_SUPPORTS_64BIT_KERNEL | |
970d032f | 1570 | select CPU_SUPPORTS_HUGEPAGES |
1da177e4 LT |
1571 | |
1572 | config CPU_R5000 | |
1573 | bool "R5000" | |
7cf8053b | 1574 | depends on SYS_HAS_CPU_R5000 |
ed5ba2fb YY |
1575 | select CPU_SUPPORTS_32BIT_KERNEL |
1576 | select CPU_SUPPORTS_64BIT_KERNEL | |
970d032f | 1577 | select CPU_SUPPORTS_HUGEPAGES |
1da177e4 LT |
1578 | help |
1579 | MIPS Technologies R5000-series processors other than the Nevada. | |
1580 | ||
542c1020 SK |
1581 | config CPU_R5500 |
1582 | bool "R5500" | |
1583 | depends on SYS_HAS_CPU_R5500 | |
542c1020 SK |
1584 | select CPU_SUPPORTS_32BIT_KERNEL |
1585 | select CPU_SUPPORTS_64BIT_KERNEL | |
9cffd154 | 1586 | select CPU_SUPPORTS_HUGEPAGES |
542c1020 SK |
1587 | help |
1588 | NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV | |
1589 | instruction set. | |
1590 | ||
1da177e4 LT |
1591 | config CPU_NEVADA |
1592 | bool "RM52xx" | |
7cf8053b | 1593 | depends on SYS_HAS_CPU_NEVADA |
ed5ba2fb YY |
1594 | select CPU_SUPPORTS_32BIT_KERNEL |
1595 | select CPU_SUPPORTS_64BIT_KERNEL | |
970d032f | 1596 | select CPU_SUPPORTS_HUGEPAGES |
1da177e4 LT |
1597 | help |
1598 | QED / PMC-Sierra RM52xx-series ("Nevada") processors. | |
1599 | ||
1da177e4 LT |
1600 | config CPU_R10000 |
1601 | bool "R10000" | |
7cf8053b | 1602 | depends on SYS_HAS_CPU_R10000 |
5e83d430 | 1603 | select CPU_HAS_PREFETCH |
ed5ba2fb YY |
1604 | select CPU_SUPPORTS_32BIT_KERNEL |
1605 | select CPU_SUPPORTS_64BIT_KERNEL | |
797798c1 | 1606 | select CPU_SUPPORTS_HIGHMEM |
970d032f | 1607 | select CPU_SUPPORTS_HUGEPAGES |
1da177e4 LT |
1608 | help |
1609 | MIPS Technologies R10000-series processors. | |
1610 | ||
1611 | config CPU_RM7000 | |
1612 | bool "RM7000" | |
7cf8053b | 1613 | depends on SYS_HAS_CPU_RM7000 |
5e83d430 | 1614 | select CPU_HAS_PREFETCH |
ed5ba2fb YY |
1615 | select CPU_SUPPORTS_32BIT_KERNEL |
1616 | select CPU_SUPPORTS_64BIT_KERNEL | |
797798c1 | 1617 | select CPU_SUPPORTS_HIGHMEM |
970d032f | 1618 | select CPU_SUPPORTS_HUGEPAGES |
1da177e4 LT |
1619 | |
1620 | config CPU_SB1 | |
1621 | bool "SB1" | |
7cf8053b | 1622 | depends on SYS_HAS_CPU_SB1 |
ed5ba2fb YY |
1623 | select CPU_SUPPORTS_32BIT_KERNEL |
1624 | select CPU_SUPPORTS_64BIT_KERNEL | |
797798c1 | 1625 | select CPU_SUPPORTS_HIGHMEM |
970d032f | 1626 | select CPU_SUPPORTS_HUGEPAGES |
0004a9df | 1627 | select WEAK_ORDERING |
1da177e4 | 1628 | |
a86c7f72 DD |
1629 | config CPU_CAVIUM_OCTEON |
1630 | bool "Cavium Octeon processor" | |
5e683389 | 1631 | depends on SYS_HAS_CPU_CAVIUM_OCTEON |
a86c7f72 DD |
1632 | select CPU_HAS_PREFETCH |
1633 | select CPU_SUPPORTS_64BIT_KERNEL | |
ba89f9c8 AB |
1634 | select HAVE_PAGE_SIZE_8KB if !MIPS_VA_BITS_48 |
1635 | select HAVE_PAGE_SIZE_32KB if !MIPS_VA_BITS_48 | |
a86c7f72 | 1636 | select WEAK_ORDERING |
a86c7f72 | 1637 | select CPU_SUPPORTS_HIGHMEM |
9cffd154 | 1638 | select CPU_SUPPORTS_HUGEPAGES |
df115f3e BH |
1639 | select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN |
1640 | select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN | |
930beb5a | 1641 | select MIPS_L1_CACHE_SHIFT_7 |
a6d54338 | 1642 | select CPU_SUPPORTS_VZ |
a86c7f72 DD |
1643 | help |
1644 | The Cavium Octeon processor is a highly integrated chip containing | |
1645 | many ethernet hardware widgets for networking tasks. The processor | |
1646 | can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets. | |
1647 | Full details can be found at http://www.caviumnetworks.com. | |
1648 | ||
cd746249 JG |
1649 | config CPU_BMIPS |
1650 | bool "Broadcom BMIPS" | |
1651 | depends on SYS_HAS_CPU_BMIPS | |
1652 | select CPU_MIPS32 | |
fe7f62c0 | 1653 | select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300 |
cd746249 JG |
1654 | select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350 |
1655 | select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380 | |
1656 | select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000 | |
1657 | select CPU_SUPPORTS_32BIT_KERNEL | |
1658 | select DMA_NONCOHERENT | |
67e38cf2 | 1659 | select IRQ_MIPS_CPU |
cd746249 JG |
1660 | select SWAP_IO_SPACE |
1661 | select WEAK_ORDERING | |
c1c0c461 | 1662 | select CPU_SUPPORTS_HIGHMEM |
69aaf9c8 | 1663 | select CPU_HAS_PREFETCH |
a8d709b0 MM |
1664 | select CPU_SUPPORTS_CPUFREQ |
1665 | select MIPS_EXTERNAL_TIMER | |
bf8bde41 | 1666 | select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU |
c1c0c461 | 1667 | help |
fe7f62c0 | 1668 | Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors. |
c1c0c461 | 1669 | |
1da177e4 LT |
1670 | endchoice |
1671 | ||
5033ad56 MY |
1672 | config LOONGSON3_ENHANCEMENT |
1673 | bool "New Loongson-3 CPU Enhancements" | |
1674 | default n | |
1675 | depends on CPU_LOONGSON64 | |
1676 | help | |
1677 | New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A | |
1678 | R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as | |
1679 | FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User | |
1680 | Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer), | |
1681 | Fast TLB refill support, etc. | |
1682 | ||
1683 | This option enable those enhancements which are not probed at run | |
1684 | time. If you want a generic kernel to run on all Loongson 3 machines, | |
1685 | please say 'N' here. If you want a high-performance kernel to run on | |
1686 | new Loongson-3 machines only, please say 'Y' here. | |
1687 | ||
1688 | config CPU_LOONGSON3_WORKAROUNDS | |
1689 | bool "Loongson-3 LLSC Workarounds" | |
1690 | default y if SMP | |
1691 | depends on CPU_LOONGSON64 | |
1692 | help | |
1693 | Loongson-3 processors have the llsc issues which require workarounds. | |
1694 | Without workarounds the system may hang unexpectedly. | |
1695 | ||
1696 | Say Y, unless you know what you are doing. | |
1697 | ||
1698 | config CPU_LOONGSON3_CPUCFG_EMULATION | |
1699 | bool "Emulate the CPUCFG instruction on older Loongson cores" | |
1700 | default y | |
1701 | depends on CPU_LOONGSON64 | |
1702 | help | |
1703 | Loongson-3A R4 and newer have the CPUCFG instruction available for | |
1704 | userland to query CPU capabilities, much like CPUID on x86. This | |
1705 | option provides emulation of the instruction on older Loongson | |
1706 | cores, back to Loongson-3A1000. | |
1707 | ||
1708 | If unsure, please say Y. | |
1709 | ||
a6e18781 LY |
1710 | config CPU_MIPS32_3_5_FEATURES |
1711 | bool "MIPS32 Release 3.5 Features" | |
1712 | depends on SYS_HAS_CPU_MIPS32_R3_5 | |
281e3aea SS |
1713 | depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \ |
1714 | CPU_P5600 | |
a6e18781 LY |
1715 | help |
1716 | Choose this option to build a kernel for release 2 or later of the | |
1717 | MIPS32 architecture including features from the 3.5 release such as | |
1718 | support for Enhanced Virtual Addressing (EVA). | |
1719 | ||
1720 | config CPU_MIPS32_3_5_EVA | |
1721 | bool "Enhanced Virtual Addressing (EVA)" | |
1722 | depends on CPU_MIPS32_3_5_FEATURES | |
1723 | select EVA | |
1724 | default y | |
1725 | help | |
1726 | Choose this option if you want to enable the Enhanced Virtual | |
1727 | Addressing (EVA) on your MIPS32 core (such as proAptiv). | |
1728 | One of its primary benefits is an increase in the maximum size | |
1729 | of lowmem (up to 3GB). If unsure, say 'N' here. | |
1730 | ||
c5b36783 SH |
1731 | config CPU_MIPS32_R5_FEATURES |
1732 | bool "MIPS32 Release 5 Features" | |
1733 | depends on SYS_HAS_CPU_MIPS32_R5 | |
281e3aea | 1734 | depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600 |
c5b36783 SH |
1735 | help |
1736 | Choose this option to build a kernel for release 2 or later of the | |
1737 | MIPS32 architecture including features from release 5 such as | |
1738 | support for Extended Physical Addressing (XPA). | |
1739 | ||
1740 | config CPU_MIPS32_R5_XPA | |
1741 | bool "Extended Physical Addressing (XPA)" | |
1742 | depends on CPU_MIPS32_R5_FEATURES | |
1743 | depends on !EVA | |
1744 | depends on !PAGE_SIZE_4KB | |
1745 | depends on SYS_SUPPORTS_HIGHMEM | |
1746 | select XPA | |
1747 | select HIGHMEM | |
d4a451d5 | 1748 | select PHYS_ADDR_T_64BIT |
c5b36783 SH |
1749 | default n |
1750 | help | |
1751 | Choose this option if you want to enable the Extended Physical | |
1752 | Addressing (XPA) on your MIPS32 core (such as P5600 series). The | |
1753 | benefit is to increase physical addressing equal to or greater | |
1754 | than 40 bits. Note that this has the side effect of turning on | |
1755 | 64-bit addressing which in turn makes the PTEs 64-bit in size. | |
1756 | If unsure, say 'N' here. | |
1757 | ||
622844bf WZ |
1758 | if CPU_LOONGSON2F |
1759 | config CPU_NOP_WORKAROUNDS | |
1760 | bool | |
1761 | ||
1762 | config CPU_JUMP_WORKAROUNDS | |
1763 | bool | |
1764 | ||
1765 | config CPU_LOONGSON2F_WORKAROUNDS | |
1766 | bool "Loongson 2F Workarounds" | |
1767 | default y | |
1768 | select CPU_NOP_WORKAROUNDS | |
1769 | select CPU_JUMP_WORKAROUNDS | |
1770 | help | |
1771 | Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which | |
1772 | require workarounds. Without workarounds the system may hang | |
1773 | unexpectedly. For more information please refer to the gas | |
1774 | -mfix-loongson2f-nop and -mfix-loongson2f-jump options. | |
1775 | ||
1776 | Loongson 2F03 and later have fixed these issues and no workarounds | |
1777 | are needed. The workarounds have no significant side effect on them | |
1778 | but may decrease the performance of the system so this option should | |
1779 | be disabled unless the kernel is intended to be run on 2F01 or 2F02 | |
1780 | systems. | |
1781 | ||
1782 | If unsure, please say Y. | |
1783 | endif # CPU_LOONGSON2F | |
1784 | ||
1b93b3c3 WZ |
1785 | config SYS_SUPPORTS_ZBOOT |
1786 | bool | |
1787 | select HAVE_KERNEL_GZIP | |
1788 | select HAVE_KERNEL_BZIP2 | |
31c4867d | 1789 | select HAVE_KERNEL_LZ4 |
1b93b3c3 | 1790 | select HAVE_KERNEL_LZMA |
fe1d45e0 | 1791 | select HAVE_KERNEL_LZO |
4e23eb63 | 1792 | select HAVE_KERNEL_XZ |
a510b616 | 1793 | select HAVE_KERNEL_ZSTD |
1b93b3c3 WZ |
1794 | |
1795 | config SYS_SUPPORTS_ZBOOT_UART16550 | |
1796 | bool | |
1797 | select SYS_SUPPORTS_ZBOOT | |
1798 | ||
dbb98314 AB |
1799 | config SYS_SUPPORTS_ZBOOT_UART_PROM |
1800 | bool | |
1801 | select SYS_SUPPORTS_ZBOOT | |
1802 | ||
268a2d60 | 1803 | config CPU_LOONGSON2EF |
3702bba5 WZ |
1804 | bool |
1805 | select CPU_SUPPORTS_32BIT_KERNEL | |
1806 | select CPU_SUPPORTS_64BIT_KERNEL | |
1807 | select CPU_SUPPORTS_HIGHMEM | |
970d032f | 1808 | select CPU_SUPPORTS_HUGEPAGES |
3702bba5 | 1809 | |
b2afb64c | 1810 | config CPU_LOONGSON32 |
ca585cf9 KC |
1811 | bool |
1812 | select CPU_MIPS32 | |
7e280f6b | 1813 | select CPU_MIPSR2 |
ca585cf9 KC |
1814 | select CPU_HAS_PREFETCH |
1815 | select CPU_SUPPORTS_32BIT_KERNEL | |
1816 | select CPU_SUPPORTS_HIGHMEM | |
f29ad10d | 1817 | select CPU_SUPPORTS_CPUFREQ |
ca585cf9 | 1818 | |
fe7f62c0 | 1819 | config CPU_BMIPS32_3300 |
04fa8bf7 | 1820 | select SMP_UP if SMP |
1bbb6c1b | 1821 | bool |
cd746249 JG |
1822 | |
1823 | config CPU_BMIPS4350 | |
1824 | bool | |
1825 | select SYS_SUPPORTS_SMP | |
1826 | select SYS_SUPPORTS_HOTPLUG_CPU | |
1827 | ||
1828 | config CPU_BMIPS4380 | |
1829 | bool | |
bbf2ba67 | 1830 | select MIPS_L1_CACHE_SHIFT_6 |
cd746249 JG |
1831 | select SYS_SUPPORTS_SMP |
1832 | select SYS_SUPPORTS_HOTPLUG_CPU | |
b4720809 | 1833 | select CPU_HAS_RIXI |
cd746249 JG |
1834 | |
1835 | config CPU_BMIPS5000 | |
1836 | bool | |
cd746249 | 1837 | select MIPS_CPU_SCACHE |
bbf2ba67 | 1838 | select MIPS_L1_CACHE_SHIFT_7 |
cd746249 JG |
1839 | select SYS_SUPPORTS_SMP |
1840 | select SYS_SUPPORTS_HOTPLUG_CPU | |
b4720809 | 1841 | select CPU_HAS_RIXI |
1bbb6c1b | 1842 | |
268a2d60 | 1843 | config SYS_HAS_CPU_LOONGSON64 |
0e476d91 HC |
1844 | bool |
1845 | select CPU_SUPPORTS_CPUFREQ | |
b2edcfc8 | 1846 | select CPU_HAS_RIXI |
0e476d91 | 1847 | |
3702bba5 | 1848 | config SYS_HAS_CPU_LOONGSON2E |
2a21c730 FZ |
1849 | bool |
1850 | ||
6f7a251a WZ |
1851 | config SYS_HAS_CPU_LOONGSON2F |
1852 | bool | |
55045ff5 WZ |
1853 | select CPU_SUPPORTS_CPUFREQ |
1854 | select CPU_SUPPORTS_ADDRWINCFG if 64BIT | |
6f7a251a | 1855 | |
ca585cf9 KC |
1856 | config SYS_HAS_CPU_LOONGSON1B |
1857 | bool | |
1858 | ||
12e3280b YL |
1859 | config SYS_HAS_CPU_LOONGSON1C |
1860 | bool | |
1861 | ||
7cf8053b RB |
1862 | config SYS_HAS_CPU_MIPS32_R1 |
1863 | bool | |
1864 | ||
1865 | config SYS_HAS_CPU_MIPS32_R2 | |
1866 | bool | |
1867 | ||
a6e18781 LY |
1868 | config SYS_HAS_CPU_MIPS32_R3_5 |
1869 | bool | |
1870 | ||
c5b36783 SH |
1871 | config SYS_HAS_CPU_MIPS32_R5 |
1872 | bool | |
1873 | ||
7fd08ca5 LY |
1874 | config SYS_HAS_CPU_MIPS32_R6 |
1875 | bool | |
1876 | ||
7cf8053b RB |
1877 | config SYS_HAS_CPU_MIPS64_R1 |
1878 | bool | |
1879 | ||
1880 | config SYS_HAS_CPU_MIPS64_R2 | |
1881 | bool | |
1882 | ||
fd4eb90b LB |
1883 | config SYS_HAS_CPU_MIPS64_R5 |
1884 | bool | |
fd4eb90b | 1885 | |
7fd08ca5 LY |
1886 | config SYS_HAS_CPU_MIPS64_R6 |
1887 | bool | |
1888 | ||
281e3aea SS |
1889 | config SYS_HAS_CPU_P5600 |
1890 | bool | |
281e3aea | 1891 | |
7cf8053b RB |
1892 | config SYS_HAS_CPU_R3000 |
1893 | bool | |
1894 | ||
65ce6197 LK |
1895 | config SYS_HAS_CPU_R4300 |
1896 | bool | |
1897 | ||
7cf8053b RB |
1898 | config SYS_HAS_CPU_R4X00 |
1899 | bool | |
1900 | ||
1901 | config SYS_HAS_CPU_TX49XX | |
1902 | bool | |
1903 | ||
1904 | config SYS_HAS_CPU_R5000 | |
1905 | bool | |
1906 | ||
542c1020 SK |
1907 | config SYS_HAS_CPU_R5500 |
1908 | bool | |
1909 | ||
7cf8053b RB |
1910 | config SYS_HAS_CPU_NEVADA |
1911 | bool | |
1912 | ||
7cf8053b RB |
1913 | config SYS_HAS_CPU_R10000 |
1914 | bool | |
1915 | ||
1916 | config SYS_HAS_CPU_RM7000 | |
1917 | bool | |
1918 | ||
7cf8053b RB |
1919 | config SYS_HAS_CPU_SB1 |
1920 | bool | |
1921 | ||
5e683389 DD |
1922 | config SYS_HAS_CPU_CAVIUM_OCTEON |
1923 | bool | |
1924 | ||
cd746249 | 1925 | config SYS_HAS_CPU_BMIPS |
c1c0c461 KC |
1926 | bool |
1927 | ||
fe7f62c0 | 1928 | config SYS_HAS_CPU_BMIPS32_3300 |
c1c0c461 | 1929 | bool |
cd746249 | 1930 | select SYS_HAS_CPU_BMIPS |
c1c0c461 KC |
1931 | |
1932 | config SYS_HAS_CPU_BMIPS4350 | |
1933 | bool | |
cd746249 | 1934 | select SYS_HAS_CPU_BMIPS |
c1c0c461 KC |
1935 | |
1936 | config SYS_HAS_CPU_BMIPS4380 | |
1937 | bool | |
cd746249 | 1938 | select SYS_HAS_CPU_BMIPS |
c1c0c461 KC |
1939 | |
1940 | config SYS_HAS_CPU_BMIPS5000 | |
1941 | bool | |
cd746249 | 1942 | select SYS_HAS_CPU_BMIPS |
c1c0c461 | 1943 | |
17099b11 RB |
1944 | # |
1945 | # CPU may reorder R->R, R->W, W->R, W->W | |
1946 | # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC | |
1947 | # | |
0004a9df RB |
1948 | config WEAK_ORDERING |
1949 | bool | |
17099b11 RB |
1950 | |
1951 | # | |
1952 | # CPU may reorder reads and writes beyond LL/SC | |
1953 | # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC | |
1954 | # | |
1955 | config WEAK_REORDERING_BEYOND_LLSC | |
1956 | bool | |
5e83d430 RB |
1957 | endmenu |
1958 | ||
1959 | # | |
c09b47d8 | 1960 | # These two indicate any level of the MIPS32 and MIPS64 architecture |
5e83d430 RB |
1961 | # |
1962 | config CPU_MIPS32 | |
1963 | bool | |
ab7c01fd | 1964 | default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \ |
281e3aea | 1965 | CPU_MIPS32_R6 || CPU_P5600 |
5e83d430 RB |
1966 | |
1967 | config CPU_MIPS64 | |
1968 | bool | |
ab7c01fd | 1969 | default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \ |
5a4fa44f | 1970 | CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON |
5e83d430 RB |
1971 | |
1972 | # | |
57eeaced | 1973 | # These indicate the revision of the architecture |
5e83d430 RB |
1974 | # |
1975 | config CPU_MIPSR1 | |
1976 | bool | |
1977 | default y if CPU_MIPS32_R1 || CPU_MIPS64_R1 | |
1978 | ||
1979 | config CPU_MIPSR2 | |
1980 | bool | |
a86c7f72 | 1981 | default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON |
8256b17e | 1982 | select CPU_HAS_RIXI |
ba9196d2 | 1983 | select CPU_HAS_DIEI if !CPU_DIEI_BROKEN |
a7e07b1a | 1984 | select MIPS_SPRAM |
5e83d430 | 1985 | |
ab7c01fd SS |
1986 | config CPU_MIPSR5 |
1987 | bool | |
281e3aea | 1988 | default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600 |
ab7c01fd SS |
1989 | select CPU_HAS_RIXI |
1990 | select CPU_HAS_DIEI if !CPU_DIEI_BROKEN | |
1991 | select MIPS_SPRAM | |
1992 | ||
7fd08ca5 LY |
1993 | config CPU_MIPSR6 |
1994 | bool | |
1995 | default y if CPU_MIPS32_R6 || CPU_MIPS64_R6 | |
8256b17e | 1996 | select CPU_HAS_RIXI |
ba9196d2 | 1997 | select CPU_HAS_DIEI if !CPU_DIEI_BROKEN |
87321fdd | 1998 | select HAVE_ARCH_BITREVERSE |
2db003a5 | 1999 | select MIPS_ASID_BITS_VARIABLE |
4a5dc51e | 2000 | select MIPS_CRC_SUPPORT |
a7e07b1a | 2001 | select MIPS_SPRAM |
5e83d430 | 2002 | |
57eeaced PB |
2003 | config TARGET_ISA_REV |
2004 | int | |
2005 | default 1 if CPU_MIPSR1 | |
2006 | default 2 if CPU_MIPSR2 | |
ab7c01fd | 2007 | default 5 if CPU_MIPSR5 |
57eeaced PB |
2008 | default 6 if CPU_MIPSR6 |
2009 | default 0 | |
2010 | help | |
2011 | Reflects the ISA revision being targeted by the kernel build. This | |
2012 | is effectively the Kconfig equivalent of MIPS_ISA_REV. | |
2013 | ||
a6e18781 LY |
2014 | config EVA |
2015 | bool | |
2016 | ||
c5b36783 SH |
2017 | config XPA |
2018 | bool | |
2019 | ||
5e83d430 RB |
2020 | config SYS_SUPPORTS_32BIT_KERNEL |
2021 | bool | |
2022 | config SYS_SUPPORTS_64BIT_KERNEL | |
2023 | bool | |
2024 | config CPU_SUPPORTS_32BIT_KERNEL | |
2025 | bool | |
2026 | config CPU_SUPPORTS_64BIT_KERNEL | |
2027 | bool | |
55045ff5 WZ |
2028 | config CPU_SUPPORTS_CPUFREQ |
2029 | bool | |
2030 | config CPU_SUPPORTS_ADDRWINCFG | |
2031 | bool | |
9cffd154 DD |
2032 | config CPU_SUPPORTS_HUGEPAGES |
2033 | bool | |
a670c82d | 2034 | depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA)) |
a6d54338 PB |
2035 | config CPU_SUPPORTS_VZ |
2036 | bool | |
82622284 DD |
2037 | config MIPS_PGD_C0_CONTEXT |
2038 | bool | |
c6972fb9 | 2039 | depends on 64BIT |
95b8a5e0 | 2040 | default y if (CPU_MIPSR2 || CPU_MIPSR6) |
5e83d430 | 2041 | |
8192c9ea DD |
2042 | # |
2043 | # Set to y for ptrace access to watch registers. | |
2044 | # | |
2045 | config HARDWARE_WATCHPOINTS | |
371a4151 EWI |
2046 | bool |
2047 | default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6 | |
8192c9ea | 2048 | |
5e83d430 RB |
2049 | menu "Kernel type" |
2050 | ||
2051 | choice | |
5e83d430 RB |
2052 | prompt "Kernel code model" |
2053 | help | |
2054 | You should only select this option if you have a workload that | |
2055 | actually benefits from 64-bit processing or if your machine has | |
2056 | large memory. You will only be presented a single option in this | |
2057 | menu if your system does not support both 32-bit and 64-bit kernels. | |
2058 | ||
2059 | config 32BIT | |
2060 | bool "32-bit kernel" | |
2061 | depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL | |
2062 | select TRAD_SIGNALS | |
2063 | help | |
2064 | Select this option if you want to build a 32-bit kernel. | |
f17c4ca3 | 2065 | |
5e83d430 RB |
2066 | config 64BIT |
2067 | bool "64-bit kernel" | |
2068 | depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL | |
2069 | help | |
2070 | Select this option if you want to build a 64-bit kernel. | |
2071 | ||
2072 | endchoice | |
2073 | ||
1e321fa9 LY |
2074 | config MIPS_VA_BITS_48 |
2075 | bool "48 bits virtual memory" | |
2076 | depends on 64BIT | |
2077 | help | |
3377e227 AB |
2078 | Support a maximum at least 48 bits of application virtual |
2079 | memory. Default is 40 bits or less, depending on the CPU. | |
2080 | For page sizes 16k and above, this option results in a small | |
2081 | memory overhead for page tables. For 4k page size, a fourth | |
2082 | level of page tables is added which imposes both a memory | |
2083 | overhead as well as slower TLB fault handling. | |
2084 | ||
1e321fa9 LY |
2085 | If unsure, say N. |
2086 | ||
79876cc1 YS |
2087 | config ZBOOT_LOAD_ADDRESS |
2088 | hex "Compressed kernel load address" | |
2089 | default 0xffffffff80400000 if BCM47XX | |
2090 | default 0x0 | |
2091 | depends on SYS_SUPPORTS_ZBOOT | |
2092 | help | |
2093 | The address to load compressed kernel, aka vmlinuz. | |
2094 | ||
2095 | This is only used if non-zero. | |
2096 | ||
0192445c | 2097 | config ARCH_FORCE_MAX_ORDER |
c9bace7c | 2098 | int "Maximum zone order" |
23baf831 | 2099 | default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB |
23baf831 | 2100 | default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB |
23baf831 | 2101 | default "11" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB |
23baf831 | 2102 | default "10" |
c9bace7c DD |
2103 | help |
2104 | The kernel memory allocator divides physically contiguous memory | |
2105 | blocks into "zones", where each zone is a power of two number of | |
2106 | pages. This option selects the largest power of two that the kernel | |
2107 | keeps in the memory allocator. If you need to allocate very large | |
2108 | blocks of physically contiguous memory, then you may need to | |
2109 | increase this value. | |
2110 | ||
c9bace7c DD |
2111 | The page size is not necessarily 4KB. Keep this in mind |
2112 | when choosing a value for this option. | |
2113 | ||
1da177e4 LT |
2114 | config BOARD_SCACHE |
2115 | bool | |
2116 | ||
2117 | config IP22_CPU_SCACHE | |
2118 | bool | |
2119 | select BOARD_SCACHE | |
2120 | ||
9318c51a CD |
2121 | # |
2122 | # Support for a MIPS32 / MIPS64 style S-caches | |
2123 | # | |
2124 | config MIPS_CPU_SCACHE | |
2125 | bool | |
2126 | select BOARD_SCACHE | |
2127 | ||
1da177e4 LT |
2128 | config R5000_CPU_SCACHE |
2129 | bool | |
2130 | select BOARD_SCACHE | |
2131 | ||
2132 | config RM7000_CPU_SCACHE | |
2133 | bool | |
2134 | select BOARD_SCACHE | |
2135 | ||
2136 | config SIBYTE_DMA_PAGEOPS | |
2137 | bool "Use DMA to clear/copy pages" | |
2138 | depends on CPU_SB1 | |
2139 | help | |
2140 | Instead of using the CPU to zero and copy pages, use a Data Mover | |
2141 | channel. These DMA channels are otherwise unused by the standard | |
2142 | SiByte Linux port. Seems to give a small performance benefit. | |
2143 | ||
2144 | config CPU_HAS_PREFETCH | |
c8094b53 | 2145 | bool |
1da177e4 | 2146 | |
3165c846 FF |
2147 | config CPU_GENERIC_DUMP_TLB |
2148 | bool | |
455481fc | 2149 | default y if !CPU_R3000 |
3165c846 | 2150 | |
c92e47e5 | 2151 | config MIPS_FP_SUPPORT |
183b40f9 PB |
2152 | bool "Floating Point support" if EXPERT |
2153 | default y | |
2154 | help | |
2155 | Select y to include support for floating point in the kernel | |
2156 | including initialization of FPU hardware, FP context save & restore | |
2157 | and emulation of an FPU where necessary. Without this support any | |
2158 | userland program attempting to use floating point instructions will | |
2159 | receive a SIGILL. | |
2160 | ||
2161 | If you know that your userland will not attempt to use floating point | |
2162 | instructions then you can say n here to shrink the kernel a little. | |
2163 | ||
2164 | If unsure, say y. | |
c92e47e5 | 2165 | |
97f7dcbf PB |
2166 | config CPU_R2300_FPU |
2167 | bool | |
c92e47e5 | 2168 | depends on MIPS_FP_SUPPORT |
455481fc | 2169 | default y if CPU_R3000 |
97f7dcbf | 2170 | |
54746829 PB |
2171 | config CPU_R3K_TLB |
2172 | bool | |
2173 | ||
91405eb6 FF |
2174 | config CPU_R4K_FPU |
2175 | bool | |
c92e47e5 | 2176 | depends on MIPS_FP_SUPPORT |
97f7dcbf | 2177 | default y if !CPU_R2300_FPU |
91405eb6 | 2178 | |
62cedc4f FF |
2179 | config CPU_R4K_CACHE_TLB |
2180 | bool | |
54746829 | 2181 | default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON) |
62cedc4f | 2182 | |
59d6ab86 | 2183 | config MIPS_MT_SMP |
a92b7f87 | 2184 | bool "MIPS MT SMP support (1 TC on each available VPE)" |
5cbf9688 | 2185 | default y |
74efddad JY |
2186 | depends on TARGET_ISA_REV > 0 && TARGET_ISA_REV < 6 |
2187 | depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MICROMIPS | |
f7062ddb | 2188 | select CPU_MIPSR2_IRQ_VI |
d725cf38 | 2189 | select CPU_MIPSR2_IRQ_EI |
c080faa5 | 2190 | select SYNC_R4K |
f41ae0b2 | 2191 | select MIPS_MT |
41c594ab | 2192 | select SMP |
87353d8a | 2193 | select SMP_UP |
c080faa5 SH |
2194 | select SYS_SUPPORTS_SMP |
2195 | select SYS_SUPPORTS_SCHED_SMT | |
399aaa25 | 2196 | select MIPS_PERF_SHARED_TC_COUNTERS |
f41ae0b2 | 2197 | help |
c080faa5 SH |
2198 | This is a kernel model which is known as SMVP. This is supported |
2199 | on cores with the MT ASE and uses the available VPEs to implement | |
2200 | virtual processors which supports SMP. This is equivalent to the | |
2201 | Intel Hyperthreading feature. For further information go to | |
2202 | <http://www.imgtec.com/mips/mips-multithreading.asp>. | |
41c594ab | 2203 | |
f41ae0b2 RB |
2204 | config MIPS_MT |
2205 | bool | |
2206 | ||
0ab7aefc RB |
2207 | config SCHED_SMT |
2208 | bool "SMT (multithreading) scheduler support" | |
2209 | depends on SYS_SUPPORTS_SCHED_SMT | |
2210 | default n | |
2211 | help | |
2212 | SMT scheduler support improves the CPU scheduler's decision making | |
2213 | when dealing with MIPS MT enabled cores at a cost of slightly | |
2214 | increased overhead in some places. If unsure say N here. | |
2215 | ||
2216 | config SYS_SUPPORTS_SCHED_SMT | |
2217 | bool | |
2218 | ||
f41ae0b2 RB |
2219 | config SYS_SUPPORTS_MULTITHREADING |
2220 | bool | |
2221 | ||
f088fc84 RB |
2222 | config MIPS_MT_FPAFF |
2223 | bool "Dynamic FPU affinity for FP-intensive threads" | |
f088fc84 | 2224 | default y |
b633648c | 2225 | depends on MIPS_MT_SMP |
07cc0c9e | 2226 | |
b0a668fb LY |
2227 | config MIPSR2_TO_R6_EMULATOR |
2228 | bool "MIPS R2-to-R6 emulator" | |
9eaa9a82 | 2229 | depends on CPU_MIPSR6 |
c92e47e5 | 2230 | depends on MIPS_FP_SUPPORT |
b0a668fb LY |
2231 | default y |
2232 | help | |
2233 | Choose this option if you want to run non-R6 MIPS userland code. | |
2234 | Even if you say 'Y' here, the emulator will still be disabled by | |
07edf0d4 | 2235 | default. You can enable it using the 'mipsr2emu' kernel option. |
b0a668fb LY |
2236 | The only reason this is a build-time option is to save ~14K from the |
2237 | final kernel image. | |
b0a668fb | 2238 | |
f35764e7 JH |
2239 | config SYS_SUPPORTS_VPE_LOADER |
2240 | bool | |
2241 | depends on SYS_SUPPORTS_MULTITHREADING | |
2242 | help | |
2243 | Indicates that the platform supports the VPE loader, and provides | |
2244 | physical_memsize. | |
2245 | ||
07cc0c9e RB |
2246 | config MIPS_VPE_LOADER |
2247 | bool "VPE loader support." | |
f35764e7 | 2248 | depends on SYS_SUPPORTS_VPE_LOADER && MODULES |
07cc0c9e RB |
2249 | select CPU_MIPSR2_IRQ_VI |
2250 | select CPU_MIPSR2_IRQ_EI | |
07cc0c9e RB |
2251 | select MIPS_MT |
2252 | help | |
2253 | Includes a loader for loading an elf relocatable object | |
2254 | onto another VPE and running it. | |
f088fc84 | 2255 | |
1a2a6d7e DCZ |
2256 | config MIPS_VPE_LOADER_MT |
2257 | bool | |
2258 | default "y" | |
7fb6f7b0 | 2259 | depends on MIPS_VPE_LOADER |
1a2a6d7e | 2260 | |
e01402b1 RB |
2261 | config MIPS_VPE_LOADER_TOM |
2262 | bool "Load VPE program into memory hidden from linux" | |
2263 | depends on MIPS_VPE_LOADER | |
2264 | default y | |
2265 | help | |
2266 | The loader can use memory that is present but has been hidden from | |
2267 | Linux using the kernel command line option "mem=xxMB". It's up to | |
2268 | you to ensure the amount you put in the option and the space your | |
2269 | program requires is less or equal to the amount physically present. | |
2270 | ||
e01402b1 | 2271 | config MIPS_VPE_APSP_API |
5e83d430 RB |
2272 | bool "Enable support for AP/SP API (RTLX)" |
2273 | depends on MIPS_VPE_LOADER | |
e01402b1 | 2274 | |
2c973ef0 DCZ |
2275 | config MIPS_VPE_APSP_API_MT |
2276 | bool | |
2277 | default "y" | |
7fb6f7b0 | 2278 | depends on MIPS_VPE_APSP_API |
5cac93b3 | 2279 | |
0ee958e1 PB |
2280 | config MIPS_CPS |
2281 | bool "MIPS Coherent Processing System support" | |
5a3e7c02 | 2282 | depends on SYS_SUPPORTS_MIPS_CPS |
0ee958e1 | 2283 | select MIPS_CM |
1d8f1f5a | 2284 | select MIPS_CPS_PM if HOTPLUG_CPU |
0ee958e1 | 2285 | select SMP |
c8d2bcc4 | 2286 | select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU |
0ee958e1 | 2287 | select SYNC_R4K if (CEVT_R4K || CSRC_R4K) |
1d8f1f5a | 2288 | select SYS_SUPPORTS_HOTPLUG_CPU |
c8b7712c | 2289 | select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6 |
0ee958e1 PB |
2290 | select SYS_SUPPORTS_SMP |
2291 | select WEAK_ORDERING | |
d8d3276b | 2292 | select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU |
0ee958e1 PB |
2293 | help |
2294 | Select this if you wish to run an SMP kernel across multiple cores | |
2295 | within a MIPS Coherent Processing System. When this option is | |
2296 | enabled the kernel will probe for other cores and boot them with | |
2297 | no external assistance. It is safe to enable this when hardware | |
2298 | support is unavailable. | |
2299 | ||
3179d37e | 2300 | config MIPS_CPS_PM |
39a59593 | 2301 | depends on MIPS_CPS |
3179d37e PB |
2302 | bool |
2303 | ||
9f98f3dd PB |
2304 | config MIPS_CM |
2305 | bool | |
3c9b4166 | 2306 | select MIPS_CPC |
9f98f3dd | 2307 | |
9c38cf44 PB |
2308 | config MIPS_CPC |
2309 | bool | |
4a16ff4c | 2310 | |
1da177e4 LT |
2311 | config SB1_PASS_2_WORKAROUNDS |
2312 | bool | |
2313 | depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2) | |
2314 | default y | |
2315 | ||
2316 | config SB1_PASS_2_1_WORKAROUNDS | |
2317 | bool | |
2318 | depends on CPU_SB1 && CPU_SB1_PASS_2 | |
2319 | default y | |
2320 | ||
9e2b5372 MC |
2321 | choice |
2322 | prompt "SmartMIPS or microMIPS ASE support" | |
2323 | ||
2324 | config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS | |
2325 | bool "None" | |
2326 | help | |
2327 | Select this if you want neither microMIPS nor SmartMIPS support | |
2328 | ||
9693a853 FBH |
2329 | config CPU_HAS_SMARTMIPS |
2330 | depends on SYS_SUPPORTS_SMARTMIPS | |
9e2b5372 | 2331 | bool "SmartMIPS" |
9693a853 FBH |
2332 | help |
2333 | SmartMIPS is a extension of the MIPS32 architecture aimed at | |
2334 | increased security at both hardware and software level for | |
2335 | smartcards. Enabling this option will allow proper use of the | |
2336 | SmartMIPS instructions by Linux applications. However a kernel with | |
2337 | this option will not work on a MIPS core without SmartMIPS core. If | |
2338 | you don't know you probably don't have SmartMIPS and should say N | |
2339 | here. | |
2340 | ||
bce86083 | 2341 | config CPU_MICROMIPS |
7fd08ca5 | 2342 | depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6 |
9e2b5372 | 2343 | bool "microMIPS" |
bce86083 SH |
2344 | help |
2345 | When this option is enabled the kernel will be built using the | |
2346 | microMIPS ISA | |
2347 | ||
9e2b5372 MC |
2348 | endchoice |
2349 | ||
a5e9a69e | 2350 | config CPU_HAS_MSA |
0ce3417e | 2351 | bool "Support for the MIPS SIMD Architecture" |
a5e9a69e | 2352 | depends on CPU_SUPPORTS_MSA |
c92e47e5 | 2353 | depends on MIPS_FP_SUPPORT |
2a6cb669 | 2354 | depends on 64BIT || MIPS_O32_FP64_SUPPORT |
a5e9a69e PB |
2355 | help |
2356 | MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers | |
2357 | and a set of SIMD instructions to operate on them. When this option | |
1db1af84 PB |
2358 | is enabled the kernel will support allocating & switching MSA |
2359 | vector register contexts. If you know that your kernel will only be | |
2360 | running on CPUs which do not support MSA or that your userland will | |
2361 | not be making use of it then you may wish to say N here to reduce | |
2362 | the size & complexity of your kernel. | |
a5e9a69e PB |
2363 | |
2364 | If unsure, say Y. | |
2365 | ||
1da177e4 | 2366 | config CPU_HAS_WB |
f7062ddb | 2367 | bool |
e01402b1 | 2368 | |
df0ac8a4 KC |
2369 | config XKS01 |
2370 | bool | |
2371 | ||
ba9196d2 JY |
2372 | config CPU_HAS_DIEI |
2373 | depends on !CPU_DIEI_BROKEN | |
2374 | bool | |
2375 | ||
2376 | config CPU_DIEI_BROKEN | |
2377 | bool | |
2378 | ||
8256b17e FF |
2379 | config CPU_HAS_RIXI |
2380 | bool | |
2381 | ||
18d84e2e | 2382 | config CPU_NO_LOAD_STORE_LR |
932afdee YC |
2383 | bool |
2384 | help | |
18d84e2e | 2385 | CPU lacks support for unaligned load and store instructions: |
932afdee | 2386 | LWL, LWR, SWL, SWR (Load/store word left/right). |
18d84e2e AL |
2387 | LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit |
2388 | systems). | |
932afdee | 2389 | |
f41ae0b2 RB |
2390 | # |
2391 | # Vectored interrupt mode is an R2 feature | |
2392 | # | |
e01402b1 | 2393 | config CPU_MIPSR2_IRQ_VI |
f41ae0b2 | 2394 | bool |
e01402b1 | 2395 | |
f41ae0b2 RB |
2396 | # |
2397 | # Extended interrupt mode is an R2 feature | |
2398 | # | |
e01402b1 | 2399 | config CPU_MIPSR2_IRQ_EI |
f41ae0b2 | 2400 | bool |
e01402b1 | 2401 | |
1da177e4 LT |
2402 | config CPU_HAS_SYNC |
2403 | bool | |
2404 | depends on !CPU_R3000 | |
2405 | default y | |
2406 | ||
20d60d99 MR |
2407 | # |
2408 | # CPU non-features | |
2409 | # | |
b56d1caf TB |
2410 | |
2411 | # Work around the "daddi" and "daddiu" CPU errata: | |
2412 | # | |
2413 | # - The `daddi' instruction fails to trap on overflow. | |
2414 | # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", | |
2415 | # erratum #23 | |
2416 | # | |
2417 | # - The `daddiu' instruction can produce an incorrect result. | |
2418 | # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", | |
2419 | # erratum #41 | |
2420 | # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum | |
2421 | # #15 | |
2422 | # "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7 | |
2423 | # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5 | |
20d60d99 MR |
2424 | config CPU_DADDI_WORKAROUNDS |
2425 | bool | |
2426 | ||
b56d1caf TB |
2427 | # Work around certain R4000 CPU errata (as implemented by GCC): |
2428 | # | |
2429 | # - A double-word or a variable shift may give an incorrect result | |
2430 | # if executed immediately after starting an integer division: | |
2431 | # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", | |
2432 | # erratum #28 | |
2433 | # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum | |
2434 | # #19 | |
2435 | # | |
2436 | # - A double-word or a variable shift may give an incorrect result | |
2437 | # if executed while an integer multiplication is in progress: | |
2438 | # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", | |
2439 | # errata #16 & #28 | |
2440 | # | |
2441 | # - An integer division may give an incorrect result if started in | |
2442 | # a delay slot of a taken branch or a jump: | |
2443 | # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", | |
2444 | # erratum #52 | |
20d60d99 MR |
2445 | config CPU_R4000_WORKAROUNDS |
2446 | bool | |
2447 | select CPU_R4400_WORKAROUNDS | |
2448 | ||
b56d1caf TB |
2449 | # Work around certain R4400 CPU errata (as implemented by GCC): |
2450 | # | |
2451 | # - A double-word or a variable shift may give an incorrect result | |
2452 | # if executed immediately after starting an integer division: | |
2453 | # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10 | |
2454 | # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4 | |
20d60d99 MR |
2455 | config CPU_R4400_WORKAROUNDS |
2456 | bool | |
2457 | ||
071d2f0b PB |
2458 | config CPU_R4X00_BUGS64 |
2459 | bool | |
2460 | default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1) | |
2461 | ||
4edf00a4 PB |
2462 | config MIPS_ASID_SHIFT |
2463 | int | |
455481fc | 2464 | default 6 if CPU_R3000 |
4edf00a4 PB |
2465 | default 0 |
2466 | ||
2467 | config MIPS_ASID_BITS | |
2468 | int | |
2db003a5 | 2469 | default 0 if MIPS_ASID_BITS_VARIABLE |
455481fc | 2470 | default 6 if CPU_R3000 |
4edf00a4 PB |
2471 | default 8 |
2472 | ||
2db003a5 PB |
2473 | config MIPS_ASID_BITS_VARIABLE |
2474 | bool | |
2475 | ||
4a5dc51e MN |
2476 | config MIPS_CRC_SUPPORT |
2477 | bool | |
2478 | ||
802b8362 TB |
2479 | # R4600 erratum. Due to the lack of errata information the exact |
2480 | # technical details aren't known. I've experimentally found that disabling | |
2481 | # interrupts during indexed I-cache flushes seems to be sufficient to deal | |
2482 | # with the issue. | |
2483 | config WAR_R4600_V1_INDEX_ICACHEOP | |
2484 | bool | |
2485 | ||
5e5b6527 TB |
2486 | # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata: |
2487 | # | |
2488 | # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D, | |
2489 | # Hit_Invalidate_D and Create_Dirty_Excl_D should only be | |
2490 | # executed if there is no other dcache activity. If the dcache is | |
18ff14c8 | 2491 | # accessed for another instruction immediately preceding when these |
5e5b6527 TB |
2492 | # cache instructions are executing, it is possible that the dcache |
2493 | # tag match outputs used by these cache instructions will be | |
2494 | # incorrect. These cache instructions should be preceded by at least | |
2495 | # four instructions that are not any kind of load or store | |
2496 | # instruction. | |
2497 | # | |
2498 | # This is not allowed: lw | |
2499 | # nop | |
2500 | # nop | |
2501 | # nop | |
2502 | # cache Hit_Writeback_Invalidate_D | |
2503 | # | |
2504 | # This is allowed: lw | |
2505 | # nop | |
2506 | # nop | |
2507 | # nop | |
2508 | # nop | |
2509 | # cache Hit_Writeback_Invalidate_D | |
2510 | config WAR_R4600_V1_HIT_CACHEOP | |
2511 | bool | |
2512 | ||
44def342 TB |
2513 | # Writeback and invalidate the primary cache dcache before DMA. |
2514 | # | |
2515 | # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D, | |
2516 | # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only | |
2517 | # operate correctly if the internal data cache refill buffer is empty. These | |
2518 | # CACHE instructions should be separated from any potential data cache miss | |
2519 | # by a load instruction to an uncached address to empty the response buffer." | |
2520 | # (Revision 2.0 device errata from IDT available on https://www.idt.com/ | |
2521 | # in .pdf format.) | |
2522 | config WAR_R4600_V2_HIT_CACHEOP | |
2523 | bool | |
2524 | ||
24a1c023 TB |
2525 | # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for |
2526 | # the line which this instruction itself exists, the following | |
2527 | # operation is not guaranteed." | |
2528 | # | |
2529 | # Workaround: do two phase flushing for Index_Invalidate_I | |
2530 | config WAR_TX49XX_ICACHE_INDEX_INV | |
2531 | bool | |
2532 | ||
886ee136 TB |
2533 | # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra |
2534 | # opposes it being called that) where invalid instructions in the same | |
2535 | # I-cache line worth of instructions being fetched may case spurious | |
2536 | # exceptions. | |
2537 | config WAR_ICACHE_REFILLS | |
2538 | bool | |
2539 | ||
256ec489 TB |
2540 | # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that |
2541 | # may cause ll / sc and lld / scd sequences to execute non-atomically. | |
2542 | config WAR_R10000_LLSC | |
2543 | bool | |
2544 | ||
a7fbed98 TB |
2545 | # 34K core erratum: "Problems Executing the TLBR Instruction" |
2546 | config WAR_MIPS34K_MISSED_ITLB | |
2547 | bool | |
2548 | ||
1da177e4 LT |
2549 | # |
2550 | # - Highmem only makes sense for the 32-bit kernel. | |
2551 | # - The current highmem code will only work properly on physically indexed | |
2552 | # caches such as R3000, SB1, R7000 or those that look like they're virtually | |
2553 | # indexed such as R4000/R4400 SC and MC versions or R10000. So for the | |
2554 | # moment we protect the user and offer the highmem option only on machines | |
2555 | # where it's known to be safe. This will not offer highmem on a few systems | |
2556 | # such as MIPS32 and MIPS64 CPUs which may have virtual and physically | |
2557 | # indexed CPUs but we're playing safe. | |
797798c1 RB |
2558 | # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we |
2559 | # know they might have memory configurations that could make use of highmem | |
2560 | # support. | |
1da177e4 LT |
2561 | # |
2562 | config HIGHMEM | |
2563 | bool "High Memory Support" | |
a6e18781 | 2564 | depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA |
a4c33e83 | 2565 | select KMAP_LOCAL |
797798c1 RB |
2566 | |
2567 | config CPU_SUPPORTS_HIGHMEM | |
2568 | bool | |
2569 | ||
2570 | config SYS_SUPPORTS_HIGHMEM | |
2571 | bool | |
1da177e4 | 2572 | |
9693a853 FBH |
2573 | config SYS_SUPPORTS_SMARTMIPS |
2574 | bool | |
2575 | ||
a6a4834c SH |
2576 | config SYS_SUPPORTS_MICROMIPS |
2577 | bool | |
2578 | ||
377cb1b6 RB |
2579 | config SYS_SUPPORTS_MIPS16 |
2580 | bool | |
2581 | help | |
2582 | This option must be set if a kernel might be executed on a MIPS16- | |
2583 | enabled CPU even if MIPS16 is not actually being used. In other | |
2584 | words, it makes the kernel MIPS16-tolerant. | |
2585 | ||
a5e9a69e PB |
2586 | config CPU_SUPPORTS_MSA |
2587 | bool | |
2588 | ||
b4819b59 YY |
2589 | config ARCH_FLATMEM_ENABLE |
2590 | def_bool y | |
268a2d60 | 2591 | depends on !NUMA && !CPU_LOONGSON2EF |
b4819b59 | 2592 | |
31473747 AN |
2593 | config ARCH_SPARSEMEM_ENABLE |
2594 | bool | |
2595 | ||
d8cb4e11 RB |
2596 | config NUMA |
2597 | bool "NUMA Support" | |
2598 | depends on SYS_SUPPORTS_NUMA | |
cf8194e4 | 2599 | select SMP |
7ecd19cf KW |
2600 | select HAVE_SETUP_PER_CPU_AREA |
2601 | select NEED_PER_CPU_EMBED_FIRST_CHUNK | |
d8cb4e11 RB |
2602 | help |
2603 | Say Y to compile the kernel to support NUMA (Non-Uniform Memory | |
2604 | Access). This option improves performance on systems with more | |
2605 | than two nodes; on two node systems it is generally better to | |
172a37e9 | 2606 | leave it disabled; on single node systems leave this option |
d8cb4e11 RB |
2607 | disabled. |
2608 | ||
2609 | config SYS_SUPPORTS_NUMA | |
2610 | bool | |
2611 | ||
f8f9f21c FC |
2612 | config HAVE_ARCH_NODEDATA_EXTENSION |
2613 | bool | |
2614 | ||
8c530ea3 MR |
2615 | config RELOCATABLE |
2616 | bool "Relocatable kernel" | |
ab7c01fd SS |
2617 | depends on SYS_SUPPORTS_RELOCATABLE |
2618 | depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \ | |
2619 | CPU_MIPS32_R5 || CPU_MIPS64_R5 || \ | |
2620 | CPU_MIPS32_R6 || CPU_MIPS64_R6 || \ | |
a307a4ce JH |
2621 | CPU_P5600 || CAVIUM_OCTEON_SOC || \ |
2622 | CPU_LOONGSON64 | |
8c530ea3 MR |
2623 | help |
2624 | This builds a kernel image that retains relocation information | |
2625 | so it can be loaded someplace besides the default 1MB. | |
2626 | The relocations make the kernel binary about 15% larger, | |
2627 | but are discarded at runtime | |
2628 | ||
069fd766 MR |
2629 | config RELOCATION_TABLE_SIZE |
2630 | hex "Relocation table size" | |
2631 | depends on RELOCATABLE | |
2632 | range 0x0 0x01000000 | |
a307a4ce | 2633 | default "0x00200000" if CPU_LOONGSON64 |
069fd766 | 2634 | default "0x00100000" |
a7f7f624 | 2635 | help |
069fd766 MR |
2636 | A table of relocation data will be appended to the kernel binary |
2637 | and parsed at boot to fix up the relocated kernel. | |
2638 | ||
2639 | This option allows the amount of space reserved for the table to be | |
2640 | adjusted, although the default of 1Mb should be ok in most cases. | |
2641 | ||
2642 | The build will fail and a valid size suggested if this is too small. | |
2643 | ||
2644 | If unsure, leave at the default value. | |
2645 | ||
405bc8fd MR |
2646 | config RANDOMIZE_BASE |
2647 | bool "Randomize the address of the kernel image" | |
2648 | depends on RELOCATABLE | |
a7f7f624 | 2649 | help |
371a4151 EWI |
2650 | Randomizes the physical and virtual address at which the |
2651 | kernel image is loaded, as a security feature that | |
2652 | deters exploit attempts relying on knowledge of the location | |
2653 | of kernel internals. | |
405bc8fd | 2654 | |
371a4151 | 2655 | Entropy is generated using any coprocessor 0 registers available. |
405bc8fd | 2656 | |
371a4151 | 2657 | The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET. |
405bc8fd | 2658 | |
371a4151 | 2659 | If unsure, say N. |
405bc8fd MR |
2660 | |
2661 | config RANDOMIZE_BASE_MAX_OFFSET | |
2662 | hex "Maximum kASLR offset" if EXPERT | |
2663 | depends on RANDOMIZE_BASE | |
2664 | range 0x0 0x40000000 if EVA || 64BIT | |
2665 | range 0x0 0x08000000 | |
2666 | default "0x01000000" | |
a7f7f624 | 2667 | help |
405bc8fd MR |
2668 | When kASLR is active, this provides the maximum offset that will |
2669 | be applied to the kernel image. It should be set according to the | |
2670 | amount of physical RAM available in the target system minus | |
2671 | PHYSICAL_START and must be a power of 2. | |
2672 | ||
2673 | This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with | |
2674 | EVA or 64-bit. The default is 16Mb. | |
2675 | ||
c80d79d7 YG |
2676 | config NODES_SHIFT |
2677 | int | |
2678 | default "6" | |
a9ee6cf5 | 2679 | depends on NUMA |
c80d79d7 | 2680 | |
14f70012 DCZ |
2681 | config HW_PERF_EVENTS |
2682 | bool "Enable hardware performance counter support for perf events" | |
95b8a5e0 | 2683 | depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64) |
14f70012 DCZ |
2684 | default y |
2685 | help | |
2686 | Enable hardware performance counter support for perf events. If | |
2687 | disabled, perf events will use software events only. | |
2688 | ||
be8fa1cb TY |
2689 | config DMI |
2690 | bool "Enable DMI scanning" | |
2691 | depends on MACH_LOONGSON64 | |
2692 | select DMI_SCAN_MACHINE_NON_EFI_FALLBACK | |
2693 | default y | |
2694 | help | |
2695 | Enabled scanning of DMI to identify machine quirks. Say Y | |
2696 | here unless you have verified that your setup is not | |
2697 | affected by entries in the DMI blacklist. Required by PNP | |
2698 | BIOS code. | |
2699 | ||
1da177e4 LT |
2700 | config SMP |
2701 | bool "Multi-Processing support" | |
e73ea273 RB |
2702 | depends on SYS_SUPPORTS_SMP |
2703 | help | |
1da177e4 | 2704 | This enables support for systems with more than one CPU. If you have |
4a474157 RG |
2705 | a system with only one CPU, say N. If you have a system with more |
2706 | than one CPU, say Y. | |
1da177e4 | 2707 | |
4a474157 | 2708 | If you say N here, the kernel will run on uni- and multiprocessor |
1da177e4 LT |
2709 | machines, but will use only one CPU of a multiprocessor machine. If |
2710 | you say Y here, the kernel will run on many, but not all, | |
4a474157 | 2711 | uniprocessor machines. On a uniprocessor machine, the kernel |
1da177e4 LT |
2712 | will run faster if you say N here. |
2713 | ||
2714 | People using multiprocessor machines who say Y here should also say | |
2715 | Y to "Enhanced Real Time Clock Support", below. | |
2716 | ||
03502faa | 2717 | See also the SMP-HOWTO available at |
ef054ad3 | 2718 | <https://www.tldp.org/docs.html#howto>. |
1da177e4 LT |
2719 | |
2720 | If you don't know what to do here, say N. | |
2721 | ||
7840d618 MR |
2722 | config HOTPLUG_CPU |
2723 | bool "Support for hot-pluggable CPUs" | |
2724 | depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU | |
2725 | help | |
2726 | Say Y here to allow turning CPUs off and on. CPUs can be | |
2727 | controlled through /sys/devices/system/cpu. | |
2728 | (Note: power management support will enable this option | |
2729 | automatically on SMP systems. ) | |
2730 | Say N if you want to disable CPU hotplug. | |
2731 | ||
87353d8a RB |
2732 | config SMP_UP |
2733 | bool | |
2734 | ||
0ee958e1 PB |
2735 | config SYS_SUPPORTS_MIPS_CPS |
2736 | bool | |
2737 | ||
e73ea273 RB |
2738 | config SYS_SUPPORTS_SMP |
2739 | bool | |
2740 | ||
130e2fb7 RB |
2741 | config NR_CPUS_DEFAULT_4 |
2742 | bool | |
2743 | ||
2744 | config NR_CPUS_DEFAULT_8 | |
2745 | bool | |
2746 | ||
2747 | config NR_CPUS_DEFAULT_16 | |
2748 | bool | |
2749 | ||
2750 | config NR_CPUS_DEFAULT_32 | |
2751 | bool | |
2752 | ||
2753 | config NR_CPUS_DEFAULT_64 | |
2754 | bool | |
2755 | ||
1da177e4 | 2756 | config NR_CPUS |
a91796a9 J |
2757 | int "Maximum number of CPUs (2-256)" |
2758 | range 2 256 | |
1da177e4 | 2759 | depends on SMP |
130e2fb7 RB |
2760 | default "4" if NR_CPUS_DEFAULT_4 |
2761 | default "8" if NR_CPUS_DEFAULT_8 | |
2762 | default "16" if NR_CPUS_DEFAULT_16 | |
2763 | default "32" if NR_CPUS_DEFAULT_32 | |
2764 | default "64" if NR_CPUS_DEFAULT_64 | |
1da177e4 LT |
2765 | help |
2766 | This allows you to specify the maximum number of CPUs which this | |
2767 | kernel will support. The maximum supported value is 32 for 32-bit | |
2768 | kernel and 64 for 64-bit kernels; the minimum value which makes | |
72ede9b1 AN |
2769 | sense is 1 for Qemu (useful only for kernel debugging purposes) |
2770 | and 2 for all others. | |
1da177e4 LT |
2771 | |
2772 | This is purely to save memory - each supported CPU adds | |
72ede9b1 AN |
2773 | approximately eight kilobytes to the kernel image. For best |
2774 | performance should round up your number of processors to the next | |
2775 | power of two. | |
1da177e4 | 2776 | |
399aaa25 AC |
2777 | config MIPS_PERF_SHARED_TC_COUNTERS |
2778 | bool | |
7820b84b DD |
2779 | |
2780 | config MIPS_NR_CPU_NR_MAP_1024 | |
2781 | bool | |
2782 | ||
2783 | config MIPS_NR_CPU_NR_MAP | |
2784 | int | |
2785 | depends on SMP | |
2786 | default 1024 if MIPS_NR_CPU_NR_MAP_1024 | |
2787 | default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024 | |
399aaa25 | 2788 | |
1723b4a3 AN |
2789 | # |
2790 | # Timer Interrupt Frequency Configuration | |
2791 | # | |
2792 | ||
2793 | choice | |
2794 | prompt "Timer frequency" | |
2795 | default HZ_250 | |
2796 | help | |
371a4151 | 2797 | Allows the configuration of the timer frequency. |
1723b4a3 | 2798 | |
67596573 PB |
2799 | config HZ_24 |
2800 | bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ | |
2801 | ||
1723b4a3 | 2802 | config HZ_48 |
0f873585 | 2803 | bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ |
1723b4a3 AN |
2804 | |
2805 | config HZ_100 | |
2806 | bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ | |
2807 | ||
2808 | config HZ_128 | |
2809 | bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ | |
2810 | ||
2811 | config HZ_250 | |
2812 | bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ | |
2813 | ||
2814 | config HZ_256 | |
2815 | bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ | |
2816 | ||
2817 | config HZ_1000 | |
2818 | bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ | |
2819 | ||
2820 | config HZ_1024 | |
2821 | bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ | |
2822 | ||
2823 | endchoice | |
2824 | ||
67596573 PB |
2825 | config SYS_SUPPORTS_24HZ |
2826 | bool | |
2827 | ||
1723b4a3 AN |
2828 | config SYS_SUPPORTS_48HZ |
2829 | bool | |
2830 | ||
2831 | config SYS_SUPPORTS_100HZ | |
2832 | bool | |
2833 | ||
2834 | config SYS_SUPPORTS_128HZ | |
2835 | bool | |
2836 | ||
2837 | config SYS_SUPPORTS_250HZ | |
2838 | bool | |
2839 | ||
2840 | config SYS_SUPPORTS_256HZ | |
2841 | bool | |
2842 | ||
2843 | config SYS_SUPPORTS_1000HZ | |
2844 | bool | |
2845 | ||
2846 | config SYS_SUPPORTS_1024HZ | |
2847 | bool | |
2848 | ||
2849 | config SYS_SUPPORTS_ARBIT_HZ | |
2850 | bool | |
67596573 PB |
2851 | default y if !SYS_SUPPORTS_24HZ && \ |
2852 | !SYS_SUPPORTS_48HZ && \ | |
2853 | !SYS_SUPPORTS_100HZ && \ | |
2854 | !SYS_SUPPORTS_128HZ && \ | |
2855 | !SYS_SUPPORTS_250HZ && \ | |
2856 | !SYS_SUPPORTS_256HZ && \ | |
2857 | !SYS_SUPPORTS_1000HZ && \ | |
1723b4a3 AN |
2858 | !SYS_SUPPORTS_1024HZ |
2859 | ||
2860 | config HZ | |
2861 | int | |
67596573 | 2862 | default 24 if HZ_24 |
1723b4a3 AN |
2863 | default 48 if HZ_48 |
2864 | default 100 if HZ_100 | |
2865 | default 128 if HZ_128 | |
2866 | default 250 if HZ_250 | |
2867 | default 256 if HZ_256 | |
2868 | default 1000 if HZ_1000 | |
2869 | default 1024 if HZ_1024 | |
2870 | ||
96685b17 DCZ |
2871 | config SCHED_HRTICK |
2872 | def_bool HIGH_RES_TIMERS | |
2873 | ||
571feed5 ED |
2874 | config ARCH_SUPPORTS_KEXEC |
2875 | def_bool y | |
2876 | ||
2877 | config ARCH_SUPPORTS_CRASH_DUMP | |
2878 | def_bool y | |
7aa1c8f4 RB |
2879 | |
2880 | config PHYSICAL_START | |
bff323d5 | 2881 | hex "Physical address where the kernel is loaded" |
8bda3e26 | 2882 | default "0xffffffff84000000" |
bff323d5 MN |
2883 | depends on CRASH_DUMP |
2884 | help | |
7aa1c8f4 RB |
2885 | This gives the CKSEG0 or KSEG0 address where the kernel is loaded. |
2886 | If you plan to use kernel for capturing the crash dump change | |
2887 | this value to start of the reserved region (the "X" value as | |
2888 | specified in the "crashkernel=YM@XM" command line boot parameter | |
2889 | passed to the panic-ed kernel). | |
2890 | ||
597ce172 | 2891 | config MIPS_O32_FP64_SUPPORT |
b7f1e273 | 2892 | bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6 |
597ce172 | 2893 | depends on 32BIT || MIPS32_O32 |
597ce172 PB |
2894 | help |
2895 | When this is enabled, the kernel will support use of 64-bit floating | |
2896 | point registers with binaries using the O32 ABI along with the | |
2897 | EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On | |
2898 | 32-bit MIPS systems this support is at the cost of increasing the | |
2899 | size and complexity of the compiled FPU emulator. Thus if you are | |
2900 | running a MIPS32 system and know that none of your userland binaries | |
2901 | will require 64-bit floating point, you may wish to reduce the size | |
2902 | of your kernel & potentially improve FP emulation performance by | |
2903 | saying N here. | |
2904 | ||
06e2e882 PB |
2905 | Although binutils currently supports use of this flag the details |
2906 | concerning its effect upon the O32 ABI in userland are still being | |
18ff14c8 | 2907 | worked on. In order to avoid userland becoming dependent upon current |
06e2e882 PB |
2908 | behaviour before the details have been finalised, this option should |
2909 | be considered experimental and only enabled by those working upon | |
2910 | said details. | |
2911 | ||
2912 | If unsure, say N. | |
597ce172 | 2913 | |
f2ffa5ab | 2914 | config USE_OF |
0b3e06fd | 2915 | bool |
f2ffa5ab | 2916 | select OF |
e6ce1324 | 2917 | select OF_EARLY_FLATTREE |
abd2363f | 2918 | select IRQ_DOMAIN |
f2ffa5ab | 2919 | |
2fe8ea39 DZ |
2920 | config UHI_BOOT |
2921 | bool | |
2922 | ||
7fafb068 AB |
2923 | config BUILTIN_DTB |
2924 | bool | |
2925 | ||
1da8f179 | 2926 | choice |
5b24d52c | 2927 | prompt "Kernel appended dtb support" if USE_OF |
1da8f179 JG |
2928 | default MIPS_NO_APPENDED_DTB |
2929 | ||
2930 | config MIPS_NO_APPENDED_DTB | |
2931 | bool "None" | |
2932 | help | |
2933 | Do not enable appended dtb support. | |
2934 | ||
87db537d AK |
2935 | config MIPS_ELF_APPENDED_DTB |
2936 | bool "vmlinux" | |
2937 | help | |
2938 | With this option, the boot code will look for a device tree binary | |
2939 | DTB) included in the vmlinux ELF section .appended_dtb. By default | |
2940 | it is empty and the DTB can be appended using binutils command | |
2941 | objcopy: | |
2942 | ||
2943 | objcopy --update-section .appended_dtb=<filename>.dtb vmlinux | |
2944 | ||
18ff14c8 | 2945 | This is meant as a backward compatibility convenience for those |
87db537d AK |
2946 | systems with a bootloader that can't be upgraded to accommodate |
2947 | the documented boot protocol using a device tree. | |
2948 | ||
1da8f179 | 2949 | config MIPS_RAW_APPENDED_DTB |
b8f54f2c | 2950 | bool "vmlinux.bin or vmlinuz.bin" |
1da8f179 JG |
2951 | help |
2952 | With this option, the boot code will look for a device tree binary | |
b8f54f2c | 2953 | DTB) appended to raw vmlinux.bin or vmlinuz.bin. |
1da8f179 JG |
2954 | (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb). |
2955 | ||
2956 | This is meant as a backward compatibility convenience for those | |
2957 | systems with a bootloader that can't be upgraded to accommodate | |
2958 | the documented boot protocol using a device tree. | |
2959 | ||
2960 | Beware that there is very little in terms of protection against | |
2961 | this option being confused by leftover garbage in memory that might | |
2962 | look like a DTB header after a reboot if no actual DTB is appended | |
2963 | to vmlinux.bin. Do not leave this option active in a production kernel | |
2964 | if you don't intend to always append a DTB. | |
2965 | endchoice | |
2966 | ||
2024972e JG |
2967 | choice |
2968 | prompt "Kernel command line type" if !CMDLINE_OVERRIDE | |
2bcef9b4 | 2969 | default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \ |
87fcfa7b | 2970 | !MACH_LOONGSON64 && !MIPS_MALTA && \ |
2bcef9b4 | 2971 | !CAVIUM_OCTEON_SOC |
2024972e JG |
2972 | default MIPS_CMDLINE_FROM_BOOTLOADER |
2973 | ||
2974 | config MIPS_CMDLINE_FROM_DTB | |
2975 | depends on USE_OF | |
2976 | bool "Dtb kernel arguments if available" | |
2977 | ||
2978 | config MIPS_CMDLINE_DTB_EXTEND | |
2979 | depends on USE_OF | |
2980 | bool "Extend dtb kernel arguments with bootloader arguments" | |
2981 | ||
2982 | config MIPS_CMDLINE_FROM_BOOTLOADER | |
2983 | bool "Bootloader kernel arguments if available" | |
ed47e153 RV |
2984 | |
2985 | config MIPS_CMDLINE_BUILTIN_EXTEND | |
2986 | depends on CMDLINE_BOOL | |
2987 | bool "Extend builtin kernel arguments with bootloader arguments" | |
2024972e JG |
2988 | endchoice |
2989 | ||
5e83d430 RB |
2990 | endmenu |
2991 | ||
1df0f0ff AN |
2992 | config LOCKDEP_SUPPORT |
2993 | bool | |
2994 | default y | |
2995 | ||
2996 | config STACKTRACE_SUPPORT | |
2997 | bool | |
2998 | default y | |
2999 | ||
a728ab52 KS |
3000 | config PGTABLE_LEVELS |
3001 | int | |
3377e227 | 3002 | default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48 |
41ce097f | 3003 | default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48) |
a728ab52 KS |
3004 | default 2 |
3005 | ||
6c359eb1 PB |
3006 | config MIPS_AUTO_PFN_OFFSET |
3007 | bool | |
3008 | ||
1da177e4 LT |
3009 | menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)" |
3010 | ||
c5611df9 | 3011 | config PCI_DRIVERS_GENERIC |
2eac9c2d | 3012 | select PCI_DOMAINS_GENERIC if PCI |
c5611df9 PB |
3013 | bool |
3014 | ||
3015 | config PCI_DRIVERS_LEGACY | |
3016 | def_bool !PCI_DRIVERS_GENERIC | |
3017 | select NO_GENERIC_PCI_IOPORT_MAP | |
2eac9c2d | 3018 | select PCI_DOMAINS if PCI |
1da177e4 LT |
3019 | |
3020 | # | |
3021 | # ISA support is now enabled via select. Too many systems still have the one | |
3022 | # or other ISA chip on the board that users don't know about so don't expect | |
3023 | # users to choose the right thing ... | |
3024 | # | |
3025 | config ISA | |
3026 | bool | |
3027 | ||
1da177e4 LT |
3028 | config TC |
3029 | bool "TURBOchannel support" | |
3030 | depends on MACH_DECSTATION | |
3031 | help | |
50a23e6e JM |
3032 | TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS |
3033 | processors. TURBOchannel programming specifications are available | |
3034 | at: | |
3035 | <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/> | |
3036 | and: | |
3037 | <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/> | |
3038 | Linux driver support status is documented at: | |
3039 | <http://www.linux-mips.org/wiki/DECstation> | |
1da177e4 | 3040 | |
1da177e4 LT |
3041 | config MMU |
3042 | bool | |
3043 | default y | |
3044 | ||
109c32ff MR |
3045 | config ARCH_MMAP_RND_BITS_MIN |
3046 | default 12 if 64BIT | |
3047 | default 8 | |
3048 | ||
3049 | config ARCH_MMAP_RND_BITS_MAX | |
3050 | default 18 if 64BIT | |
3051 | default 15 | |
3052 | ||
3053 | config ARCH_MMAP_RND_COMPAT_BITS_MIN | |
371a4151 | 3054 | default 8 |
109c32ff MR |
3055 | |
3056 | config ARCH_MMAP_RND_COMPAT_BITS_MAX | |
371a4151 | 3057 | default 15 |
109c32ff | 3058 | |
d865bea4 RB |
3059 | config I8253 |
3060 | bool | |
798778b8 | 3061 | select CLKSRC_I8253 |
2d02612f | 3062 | select CLKEVT_I8253 |
9726b43a | 3063 | select MIPS_EXTERNAL_TIMER |
1da177e4 LT |
3064 | endmenu |
3065 | ||
1da177e4 LT |
3066 | config TRAD_SIGNALS |
3067 | bool | |
1da177e4 | 3068 | |
1da177e4 | 3069 | config MIPS32_COMPAT |
78aaf956 | 3070 | bool |
1da177e4 LT |
3071 | |
3072 | config COMPAT | |
3073 | bool | |
1da177e4 LT |
3074 | |
3075 | config MIPS32_O32 | |
3076 | bool "Kernel support for o32 binaries" | |
78aaf956 RB |
3077 | depends on 64BIT |
3078 | select ARCH_WANT_OLD_COMPAT_IPC | |
3079 | select COMPAT | |
3080 | select MIPS32_COMPAT | |
1da177e4 LT |
3081 | help |
3082 | Select this option if you want to run o32 binaries. These are pure | |
3083 | 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of | |
3084 | existing binaries are in this format. | |
3085 | ||
3086 | If unsure, say Y. | |
3087 | ||
3088 | config MIPS32_N32 | |
3089 | bool "Kernel support for n32 binaries" | |
c22eacfe | 3090 | depends on 64BIT |
5a9372f7 | 3091 | select ARCH_WANT_COMPAT_IPC_PARSE_VERSION |
78aaf956 RB |
3092 | select COMPAT |
3093 | select MIPS32_COMPAT | |
1da177e4 LT |
3094 | help |
3095 | Select this option if you want to run n32 binaries. These are | |
3096 | 64-bit binaries using 32-bit quantities for addressing and certain | |
3097 | data that would normally be 64-bit. They are used in special | |
3098 | cases. | |
3099 | ||
3100 | If unsure, say N. | |
3101 | ||
d49fc692 NC |
3102 | config CC_HAS_MNO_BRANCH_LIKELY |
3103 | def_bool y | |
3104 | depends on $(cc-option,-mno-branch-likely) | |
3105 | ||
1a2c73f4 JY |
3106 | # https://github.com/llvm/llvm-project/issues/61045 |
3107 | config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH | |
3108 | def_bool y if CC_IS_CLANG | |
3109 | ||
2116245e RB |
3110 | menu "Power management options" |
3111 | ||
363c55ca WZ |
3112 | config ARCH_HIBERNATION_POSSIBLE |
3113 | def_bool y | |
3f5b3e17 | 3114 | depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP |
363c55ca | 3115 | |
f4cb5700 JB |
3116 | config ARCH_SUSPEND_POSSIBLE |
3117 | def_bool y | |
3f5b3e17 | 3118 | depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP |
f4cb5700 | 3119 | |
2116245e | 3120 | source "kernel/power/Kconfig" |
952fa954 | 3121 | |
1da177e4 LT |
3122 | endmenu |
3123 | ||
7a998935 VK |
3124 | config MIPS_EXTERNAL_TIMER |
3125 | bool | |
3126 | ||
7a998935 | 3127 | menu "CPU Power Management" |
c095ebaf PB |
3128 | |
3129 | if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER | |
7a998935 | 3130 | source "drivers/cpufreq/Kconfig" |
31f12fdc | 3131 | endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER |
9726b43a | 3132 | |
c095ebaf PB |
3133 | source "drivers/cpuidle/Kconfig" |
3134 | ||
3135 | endmenu | |
3136 | ||
2235a54d | 3137 | source "arch/mips/kvm/Kconfig" |
e91946d6 NC |
3138 | |
3139 | source "arch/mips/vdso/Kconfig" |