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[linux-2.6-block.git] / arch / metag / include / asm / metag_regs.h
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af8a1049
JH		 1/*
2 * asm/metag_regs.h
3 *
4 * Copyright (C) 2000-2007, 2012 Imagination Technologies.
5 *
6 * This program is free software; you can redistribute it and/or modify it under
7 * the terms of the GNU General Public License version 2 as published by the
8 * Free Software Foundation.
9 *
10 * Various defines for Meta core (non memory-mapped) registers.
11 */
12
13#ifndef _ASM_METAG_REGS_H_
14#define _ASM_METAG_REGS_H_
15
16/*
17 * CHIP Unit Identifiers and Valid/Global register number masks
18 * ------------------------------------------------------------
19 */
20#define TXUCT_ID 0x0 /* Control unit regs */
21#ifdef METAC_1_2
22#define TXUCT_MASK 0xFF0FFFFF /* Valid regs 0..31 */
23#else
24#define TXUCT_MASK 0xFF1FFFFF /* Valid regs 0..31 */
25#endif
26#define TGUCT_MASK 0x00000000 /* No global regs */
27#define TXUD0_ID 0x1 /* Data unit regs */
28#define TXUD1_ID 0x2
29#define TXUDX_MASK 0xFFFFFFFF /* Valid regs 0..31 */
30#define TGUDX_MASK 0xFFFF0000 /* Global regs for base inst */
31#define TXUDXDSP_MASK 0x0F0FFFFF /* Valid DSP regs */
32#define TGUDXDSP_MASK 0x0E0E0000 /* Global DSP ACC regs */
33#define TXUA0_ID 0x3 /* Address unit regs */
34#define TXUA1_ID 0x4
35#define TXUAX_MASK 0x0000FFFF /* Valid regs 0-15 */
36#define TGUAX_MASK 0x0000FF00 /* Global regs 8-15 */
37#define TXUPC_ID 0x5 /* PC registers */
38#define TXUPC_MASK 0x00000003 /* Valid regs 0- 1 */
39#define TGUPC_MASK 0x00000000 /* No global regs */
40#define TXUPORT_ID 0x6 /* Ports are not registers */
41#define TXUTR_ID 0x7
42#define TXUTR_MASK 0x0000005F /* Valid regs 0-3,4,6 */
43#define TGUTR_MASK 0x00000000 /* No global regs */
44#ifdef METAC_2_1
45#define TXUTT_ID 0x8
46#define TXUTT_MASK 0x0000000F /* Valid regs 0-3 */
47#define TGUTT_MASK 0x00000010 /* Global reg 4 */
48#define TXUFP_ID 0x9 /* FPU regs */
49#define TXUFP_MASK 0x0000FFFF /* Valid regs 0-15 */
50#define TGUFP_MASK 0x00000000 /* No global regs */
51#endif /* METAC_2_1 */
52
53#ifdef METAC_1_2
54#define TXUXX_MASKS { TXUCT_MASK, TXUDX_MASK, TXUDX_MASK, TXUAX_MASK, \
55 TXUAX_MASK, TXUPC_MASK, 0, TXUTR_MASK, \
56 0, 0, 0, 0, 0, 0, 0, 0 }
57#define TGUXX_MASKS { TGUCT_MASK, TGUDX_MASK, TGUDX_MASK, TGUAX_MASK, \
58 TGUAX_MASK, TGUPC_MASK, 0, TGUTR_MASK, \
59 0, 0, 0, 0, 0, 0, 0, 0 }
60#else /* METAC_1_2 */
61#define TXUXX_MASKS { TXUCT_MASK, TXUDX_MASK, TXUDX_MASK, TXUAX_MASK, \
62 TXUAX_MASK, TXUPC_MASK, 0, TXUTR_MASK, \
63 TXUTT_MASK, TXUFP_MASK, 0, 0, \
64 0, 0, 0, 0 }
65#define TGUXX_MASKS { TGUCT_MASK, TGUDX_MASK, TGUDX_MASK, TGUAX_MASK, \
66 TGUAX_MASK, TGUPC_MASK, 0, TGUTR_MASK, \
67 TGUTT_MASK, TGUFP_MASK, 0, 0, \
68 0, 0, 0, 0 }
69#endif /* !METAC_1_2 */
70
71#define TXUXXDSP_MASKS { 0, TXUDXDSP_MASK, TXUDXDSP_MASK, 0, 0, 0, 0, 0, \
72 0, 0, 0, 0, 0, 0, 0, 0 }
73#define TGUXXDSP_MASKS { 0, TGUDXDSP_MASK, TGUDXDSP_MASK, 0, 0, 0, 0, 0, \
74 0, 0, 0, 0, 0, 0, 0, 0 }
75
76/* -------------------------------------------------------------------------
77; DATA AND ADDRESS UNIT REGISTERS
78; -----------------------------------------------------------------------*/
79/*
80 Thread local D0 registers
81 */
82/* D0.0 ; Holds 32-bit result, can be used as scratch */
83#define D0Re0 D0.0
84/* D0.1 ; Used to pass Arg6_32 */
85#define D0Ar6 D0.1
86/* D0.2 ; Used to pass Arg4_32 */
87#define D0Ar4 D0.2
88/* D0.3 ; Used to pass Arg2_32 to a called routine (see D1.3 below) */
89#define D0Ar2 D0.3
90/* D0.4 ; Can be used as scratch; used to save A0FrP in entry sequences */
91#define D0FrT D0.4
92/* D0.5 ; C compiler assumes preservation, save with D1.5 if used */
93/* D0.6 ; C compiler assumes preservation, save with D1.6 if used */
94/* D0.7 ; C compiler assumes preservation, save with D1.7 if used */
95/* D0.8 ; Use of D0.8 and above is not encouraged */
96/* D0.9 */
97/* D0.10 */
98/* D0.11 */
99/* D0.12 */
100/* D0.13 */
101/* D0.14 */
102/* D0.15 */
103/*
104 Thread local D1 registers
105 */
106/* D1.0 ; Holds top 32-bits of 64-bit result, can be used as scratch */
107#define D1Re0 D1.0
108/* D1.1 ; Used to pass Arg5_32 */
109#define D1Ar5 D1.1
110/* D1.2 ; Used to pass Arg3_32 */
111#define D1Ar3 D1.2
112/* D1.3 ; Used to pass Arg1_32 (first 32-bit argument) to a called routine */
113#define D1Ar1 D1.3
114/* D1.4 ; Used for Return Pointer, save during entry with A0FrP (via D0.4) */
115#define D1RtP D1.4
116/* D1.5 ; C compiler assumes preservation, save if used */
117/* D1.6 ; C compiler assumes preservation, save if used */
118/* D1.7 ; C compiler assumes preservation, save if used */
119/* D1.8 ; Use of D1.8 and above is not encouraged */
120/* D1.9 */
121/* D1.10 */
122/* D1.11 */
123/* D1.12 */
124/* D1.13 */
125/* D1.14 */
126/* D1.15 */
127/*
128 Thread local A0 registers
129 */
130/* A0.0 ; Primary stack pointer */
131#define A0StP A0.0
132/* A0.1 ; Used as local frame pointer in C, save if used (via D0.4) */
133#define A0FrP A0.1
134/* A0.2 */
135/* A0.3 */
136/* A0.4 ; Use of A0.4 and above is not encouraged */
137/* A0.5 */
138/* A0.6 */
139/* A0.7 */
140/*
141 Thread local A1 registers
142 */
143/* A1.0 ; Global static chain pointer - do not modify */
144#define A1GbP A1.0
145/* A1.1 ; Local static chain pointer in C, can be used as scratch */
146#define A1LbP A1.1
147/* A1.2 */
148/* A1.3 */
149/* A1.4 ; Use of A1.4 and above is not encouraged */
150/* A1.5 */
151/* A1.6 */
152/* A1.7 */
153#ifdef METAC_2_1
154/* Renameable registers for use with Fast Interrupts */
155/* The interrupt stack pointer (usually a global register) */
156#define A0IStP A0IReg
157/* The interrupt global pointer (usually a global register) */
158#define A1IGbP A1IReg
159#endif
160/*
161 Further registers may be globally allocated via linkage/loading tools,
162 normally they are not used.
163 */
164/*-------------------------------------------------------------------------
165; STACK STRUCTURE and CALLING CONVENTION
166; -----------------------------------------------------------------------*/
167/*
168; Calling convention indicates that the following is the state of the
169; stack frame at the start of a routine-
170;
171; Arg9_32 [A0StP+#-12]
172; Arg8_32 [A0StP+#- 8]
173; Arg7_32 [A0StP+#- 4]
174; A0StP->
175;
176; Registers D1.3, D0.3, ..., to D0.1 are used to pass Arg1_32 to Arg6_32
177; respectively. If a routine needs to store them on the stack in order
178; to make sub-calls or because of the general complexity of the routine it
179; is best to dump these registers immediately at the start of a routine
180; using a MSETL or SETL instruction-
181;
986724dd 182; MSETL [A0StP],D0Ar6,D0Ar4,D0Ar2; Only dump arguments expected
af8a1049
JH		 183;or SETL [A0StP+#8++],D0Ar2 ; Up to two 32-bit args expected
184;
185; For non-leaf routines it is always necessary to save and restore at least
186; the return address value D1RtP on the stack. Also by convention if the
187; frame is saved then a new A0FrP value must be set-up. So for non-leaf
188; routines at this point both these registers must be saved onto the stack
189; using a SETL instruction and the new A0FrP value is then set-up-
190;
191; MOV D0FrT,A0FrP
192; ADD A0FrP,A0StP,#0
193; SETL [A0StP+#8++],D0FrT,D1RtP
194;
195; Registers D0.5, D1.5, to D1.7 are assumed to be preserved across calls so
196; a SETL or MSETL instruction can be used to save the current state
197; of these registers if they are modified by the current routine-
198;
199; MSETL [A0StP],D0.5,D0.6,D0.7 ; Only save registers modified
200;or SETL [A0StP+#8++],D0.5 ; Only D0.5 and/or D1.5 modified
201;
202; All of the above sequences can be combined into one maximal case-
203;
204; MOV D0FrT,A0FrP ; Save and calculate new frame pointer
205; ADD A0FrP,A0StP,#(ARS)
206; MSETL [A0StP],D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7
207;
208; Having completed the above sequence the only remaining task on routine
209; entry is to reserve any local and outgoing argment storage space on the
210; stack. This instruction may be omitted if the size of this region is zero-
211;
212; ADD A0StP,A0StP,#(LCS)
213;
214; LCS is the first example use of one of a number of standard local defined
215; values that can be created to make assembler code more readable and
216; potentially more robust-
217;
218; #define ARS 0x18 ; Register arg bytes saved on stack
219; #define FRS 0x20 ; Frame save area size in bytes
220; #define LCS 0x00 ; Locals and Outgoing arg size
221; #define ARO (LCS+FRS) ; Stack offset to access args
222;
223; All of the above defines should be undefined (#undef) at the end of each
224; routine to avoid accidental use in the next routine.
225;
226; Given all of the above the following stack structure is expected during
227; the body of a routine if all args passed in registers are saved during
228; entry-
229;
230; ; 'Incoming args area'
231; Arg10_32 [A0StP+#-((10*4)+ARO)] Arg9_32 [A0StP+#-(( 9*4)+ARO)]
232; Arg8_32 [A0StP+#-(( 8*4)+ARO)] Arg7_32 [A0StP+#-(( 7*4)+ARO)]
233;--- Call point
234; D0Ar6= Arg6_32 [A0StP+#-(( 6*4)+ARO)] D1Ar5=Arg5_32 [A0StP+#-(( 5*4)+ARO)]
235; D0Ar4= Arg4_32 [A0StP+#-(( 4*4)+ARO)] D1Ar3=Arg3_32 [A0StP+#-(( 3*4)+ARO)]
236; D0Ar2= Arg2_32 [A0StP+#-(( 2*4)+ARO)] D1Ar2=Arg1_32 [A0StP+#-(( 1*4)+ARO)]
237; ; 'Frame area'
238; A0FrP-> D0FrT, D1RtP,
239; D0.5, D1.5,
240; D0.6, D1.6,
241; D0.7, D1.7,
242; ; 'Locals area'
243; Loc0_32 [A0StP+# (( 0*4)-LCS)], Loc1_32 [A0StP+# (( 1*4)-LCS)]
244; .... other locals
245; Locn_32 [A0StP+# (( n*4)-LCS)]
246; ; 'Outgoing args area'
247; Outm_32 [A0StP+#- ( m*4)] .... other outgoing args
248; Out8_32 [A0StP+#- ( 1*4)] Out7_32 [A0StP+#- ( 1*4)]
249; A0StP-> (Out1_32-Out6_32 in regs D1Ar1-D0Ar6)
250;
251; The exit sequence for a non-leaf routine can use the frame pointer created
252; in the entry sequence to optimise the recovery of the full state-
253;
254; MGETL D0FrT,D0.5,D0.6,D0.7,[A0FrP]
255; SUB A0StP,A0FrP,#(ARS+FRS)
256; MOV A0FrP,D0FrT
257; MOV PC,D1RtP
258;
259; Having described the most complex non-leaf case above, it is worth noting
260; that if a routine is a leaf and does not use any of the caller-preserved
261; state. The routine can be implemented as-
262;
263; ADD A0StP,A0StP,#LCS
264; .... body of routine
265; SUB A0StP,A0StP,#LCS
266; MOV PC,D1RtP
267;
268; The stack adjustments can also be omitted if no local storage is required.
269;
270; Another exit sequence structure is more applicable if for a leaf routine
271; with no local frame pointer saved/generated in which the call saved
272; registers need to be saved and restored-
273;
274; MSETL [A0StP],D0.5,D0.6,D0.7 ; Hence FRS is 0x18, ARS is 0x00
275; ADD A0StP,A0StP,#LCS
276; .... body of routine
277; GETL D0.5,D1.5,[A0StP+#((0*8)-(FRS+LCS))]
278; GETL D0.6,D1.6,[A0StP+#((1*8)-(FRS+LCS))]
279; GETL D0.7,D1.7,[A0StP+#((2*8)-(FRS+LCS))]
280; SUB A0StP,A0StP,#(ARS+FRS+LCS)
281; MOV PC,D1RtP
282;
283; Lastly, to support profiling assembler code should use a fixed entry/exit
284; sequence if the trigger define _GMON_ASM is defined-
285;
286; #ifndef _GMON_ASM
287; ... optimised entry code
288; #else
289; ; Profiling entry case
290; MOV D0FrT,A0FrP ; Save and calculate new frame pointer
291; ADD A0FrP,A0StP,#(ARS)
292; MSETL [A0StP],...,D0FrT,... or SETL [A0FrP],D0FrT,D1RtP
293; CALLR D0FrT,_mcount_wrapper
294; #endif
295; ... body of routine
296; #ifndef _GMON_ASM
297; ... optimised exit code
298; #else
299; ; Profiling exit case
300; MGETL D0FrT,...,[A0FrP] or GETL D0FrT,D1RtP,[A0FrP++]
301; SUB A0StP,A0FrP,#(ARS+FRS)
302; MOV A0FrP,D0FrT
303; MOV PC,D1RtP
304; #endif
305
306
307; -------------------------------------------------------------------------
308; CONTROL UNIT REGISTERS
309; -------------------------------------------------------------------------
310;
311; See the assembler guide, hardware documentation, or the field values
312; defined below for some details of the use of these registers.
313*/
314#define TXENABLE CT.0 /* Need to define bit-field values in these */
315#define TXMODE CT.1
316#define TXSTATUS CT.2 /* DEFAULT 0x00020000 */
317#define TXRPT CT.3
318#define TXTIMER CT.4
319#define TXL1START CT.5
320#define TXL1END CT.6
321#define TXL1COUNT CT.7
322#define TXL2START CT.8
323#define TXL2END CT.9
324#define TXL2COUNT CT.10
325#define TXBPOBITS CT.11
326#define TXMRSIZE CT.12
327#define TXTIMERI CT.13
328#define TXDRCTRL CT.14 /* DEFAULT 0x0XXXF0F0 */
329#define TXDRSIZE CT.15
330#define TXCATCH0 CT.16
331#define TXCATCH1 CT.17
332#define TXCATCH2 CT.18
333#define TXCATCH3 CT.19
334
335#ifdef METAC_2_1
336#define TXDEFR CT.20
337#define TXCPRS CT.21
338#endif
339
340#define TXINTERN0 CT.23
341#define TXAMAREG0 CT.24
342#define TXAMAREG1 CT.25
343#define TXAMAREG2 CT.26
344#define TXAMAREG3 CT.27
345#define TXDIVTIME CT.28 /* DEFAULT 0x00000001 */
346#define TXPRIVEXT CT.29 /* DEFAULT 0x003B0000 */
347#define TXTACTCYC CT.30
348#define TXIDLECYC CT.31
349
350/*****************************************************************************
351 * CONTROL UNIT REGISTER BITS
352 ****************************************************************************/
353/*
354 * The following registers and where appropriate the sub-fields of those
355 * registers are defined for pervasive use in controlling program flow.
356 */
357
358/*
359 * TXENABLE register fields - only the thread id is routinely useful
360 */
361#define TXENABLE_REGNUM 0
362#define TXENABLE_THREAD_BITS 0x00000700
363#define TXENABLE_THREAD_S 8
364#define TXENABLE_REV_STEP_BITS 0x000000F0
365#define TXENABLE_REV_STEP_S 4
366
367/*
368 * TXMODE register - controls extensions of the instruction set
369 */
370#define TXMODE_REGNUM 1
371#define TXMODE_DEFAULT 0 /* All fields default to zero */
372
373/*
374 * TXSTATUS register - contains a couple of stable bits that can be used
375 * to determine the privilege processing level and interrupt
376 * processing level of the current thread.
377 */
378#define TXSTATUS_REGNUM 2
379#define TXSTATUS_PSTAT_BIT 0x00020000 /* -> Privilege active */
380#define TXSTATUS_PSTAT_S 17
381#define TXSTATUS_ISTAT_BIT 0x00010000 /* -> In interrupt state */
382#define TXSTATUS_ISTAT_S 16
383
384/*
385 * These are all relatively boring registers, mostly full 32-bit
386 */
387#define TXRPT_REGNUM 3 /* Repeat counter for XFR... instructions */
388#define TXTIMER_REGNUM 4 /* Timer-- causes timer trigger on overflow */
389#define TXL1START_REGNUM 5 /* Hardware Loop 1 Start-PC/End-PC/Count */
390#define TXL1END_REGNUM 6
391#define TXL1COUNT_REGNUM 7
392#define TXL2START_REGNUM 8 /* Hardware Loop 2 Start-PC/End-PC/Count */
393#define TXL2END_REGNUM 9
394#define TXL2COUNT_REGNUM 10
395#define TXBPOBITS_REGNUM 11 /* Branch predict override bits - tune perf */
396#define TXTIMERI_REGNUM 13 /* Timer-- time based interrupt trigger */
397
398/*
399 * TXDIVTIME register is routinely read to calculate the time-base for
400 * the TXTIMER register.
401 */
402#define TXDIVTIME_REGNUM 28
403#define TXDIVTIME_DIV_BITS 0x000000FF
404#define TXDIVTIME_DIV_S 0
405#define TXDIVTIME_DIV_MIN 0x00000001 /* Maximum resolution */
406#define TXDIVTIME_DIV_MAX 0x00000100 /* 1/1 -> 1/256 resolution */
407#define TXDIVTIME_BASE_HZ 1000000 /* Timers run at 1Mhz @1/1 */
408
409/*
410 * TXPRIVEXT register can be consulted to decide if write access to a
411 * part of the threads register set is not permitted when in
412 * unprivileged mode (PSTAT == 0).
413 */
414#define TXPRIVEXT_REGNUM 29
415#define TXPRIVEXT_COPRO_BITS 0xFF000000 /* Co-processor 0-7 */
416#define TXPRIVEXT_COPRO_S 24
c787c2d6
JH		 417#ifndef METAC_1_2
418#define TXPRIVEXT_TXTIMER_BIT 0x00080000 /* TXTIMER priv */
419#define TXPRIVEXT_TRACE_BIT 0x00040000 /* TTEXEC|TTCTRL|GTEXEC */
420#endif
af8a1049
JH		 421#define TXPRIVEXT_TXTRIGGER_BIT 0x00020000 /* TXSTAT|TXMASK|TXPOLL */
422#define TXPRIVEXT_TXGBLCREG_BIT 0x00010000 /* Global common regs */
423#define TXPRIVEXT_CBPRIV_BIT 0x00008000 /* Mem i/f dump priv */
424#define TXPRIVEXT_ILOCK_BIT 0x00004000 /* LOCK inst priv */
425#define TXPRIVEXT_TXITACCYC_BIT 0x00002000 /* TXIDLECYC|TXTACTCYC */
426#define TXPRIVEXT_TXDIVTIME_BIT 0x00001000 /* TXDIVTIME priv */
427#define TXPRIVEXT_TXAMAREGX_BIT 0x00000800 /* TXAMAREGX priv */
428#define TXPRIVEXT_TXTIMERI_BIT 0x00000400 /* TXTIMERI priv */
429#define TXPRIVEXT_TXSTATUS_BIT 0x00000200 /* TXSTATUS priv */
430#define TXPRIVEXT_TXDISABLE_BIT 0x00000100 /* TXENABLE priv */
431#ifndef METAC_1_2
432#define TXPRIVEXT_MINIMON_BIT 0x00000080 /* Enable Minim features */
433#define TXPRIVEXT_OLDBCCON_BIT 0x00000020 /* Restore Static predictions */
434#define TXPRIVEXT_ALIGNREW_BIT 0x00000010 /* Align & precise checks */
435#endif
436#define TXPRIVEXT_KEEPPRI_BIT 0x00000008 /* Use AMA_Priority if ISTAT=1*/
437#define TXPRIVEXT_TXTOGGLEI_BIT 0x00000001 /* TX.....I priv */
438
439/*
440 * TXTACTCYC register - counts instructions issued for this thread
441 */
442#define TXTACTCYC_REGNUM 30
443#define TXTACTCYC_COUNT_MASK 0x00FFFFFF
444
445/*
446 * TXIDLECYC register - counts idle cycles
447 */
448#define TXIDLECYC_REGNUM 31
449#define TXIDLECYC_COUNT_MASK 0x00FFFFFF
450
451/*****************************************************************************
452 * DSP EXTENSIONS
453 ****************************************************************************/
454/*
455 * The following values relate to fields and controls that only a program
456 * using the DSP extensions of the META instruction set need to know.
457 */
458
459
460#ifndef METAC_1_2
461/*
462 * Allow co-processor hardware to replace the read pipeline data source in
463 * appropriate cases.
464 */
465#define TXMODE_RDCPEN_BIT 0x00800000
466#endif
467
468/*
469 * Address unit addressing modes
470 */
471#define TXMODE_A1ADDR_BITS 0x00007000
472#define TXMODE_A1ADDR_S 12
473#define TXMODE_A0ADDR_BITS 0x00000700
474#define TXMODE_A0ADDR_S 8
475#define TXMODE_AXADDR_MODULO 3
476#define TXMODE_AXADDR_REVB 4
477#define TXMODE_AXADDR_REVW 5
478#define TXMODE_AXADDR_REVD 6
479#define TXMODE_AXADDR_REVL 7
480
481/*
482 * Data unit OverScale select (default 0 -> normal, 1 -> top 16 bits)
483 */
484#define TXMODE_DXOVERSCALE_BIT 0x00000080
485
486/*
487 * Data unit MX mode select (default 0 -> MX16, 1 -> MX8)
488 */
489#define TXMODE_M8_BIT 0x00000040
490
491/*
492 * Data unit accumulator saturation point (default -> 40 bit accumulator)
493 */
494#define TXMODE_DXACCSAT_BIT 0x00000020 /* Set for 32-bit accumulator */
495
496/*
497 * Data unit accumulator saturation enable (default 0 -> no saturation)
498 */
499#define TXMODE_DXSAT_BIT 0x00000010
500
501/*
502 * Data unit master rounding control (default 0 -> normal, 1 -> convergent)
503 */
504#define TXMODE_DXROUNDING_BIT 0x00000008
505
506/*
507 * Data unit product shift for fractional arithmetic (default off)
508 */
509#define TXMODE_DXPRODSHIFT_BIT 0x00000004
510
511/*
512 * Select the arithmetic mode (multiply mostly) for both data units
513 */
514#define TXMODE_DXARITH_BITS 0x00000003
515#define TXMODE_DXARITH_32 3
516#define TXMODE_DXARITH_32H 2
517#define TXMODE_DXARITH_S16 1
518#define TXMODE_DXARITH_16 0
519
520/*
521 * TXMRSIZE register value only relevant when DSP modulo addressing active
522 */
523#define TXMRSIZE_REGNUM 12
524#define TXMRSIZE_MIN 0x0002 /* 0, 1 -> normal addressing logic */
525#define TXMRSIZE_MAX 0xFFFF
526
527/*
528 * TXDRCTRL register can be used to detect the actaul size of the DSP RAM
529 * partitions allocated to this thread.
530 */
531#define TXDRCTRL_REGNUM 14
532#define TXDRCTRL_SINESIZE_BITS 0x0F000000
533#define TXDRCTRL_SINESIZE_S 24
534#define TXDRCTRL_RAMSZPOW_BITS 0x001F0000 /* Limit = (1<<RAMSZPOW)-1 */
535#define TXDRCTRL_RAMSZPOW_S 16
536#define TXDRCTRL_D1RSZAND_BITS 0x0000F000 /* Mask top 4 bits - D1 */
537#define TXDRCTRL_D1RSZAND_S 12
538#define TXDRCTRL_D0RSZAND_BITS 0x000000F0 /* Mask top 4 bits - D0 */
539#define TXDRCTRL_D0RSZAND_S 4
540/* Given extracted RAMSZPOW and DnRSZAND fields this returns the size */
541#define TXDRCTRL_DXSIZE(Pow, AndBits) \
542 ((((~(AndBits)) & 0x0f) + 1) << ((Pow)-4))
543
544/*
545 * TXDRSIZE register provides modulo addressing options for each DSP RAM
546 */
547#define TXDRSIZE_REGNUM 15
548#define TXDRSIZE_R1MOD_BITS 0xFFFF0000
549#define TXDRSIZE_R1MOD_S 16
550#define TXDRSIZE_R0MOD_BITS 0x0000FFFF
551#define TXDRSIZE_R0MOD_S 0
552
553#define TXDRSIZE_RBRAD_SCALE_BITS 0x70000000
554#define TXDRSIZE_RBRAD_SCALE_S 28
555#define TXDRSIZE_RBMODSIZE_BITS 0x0FFF0000
556#define TXDRSIZE_RBMODSIZE_S 16
557#define TXDRSIZE_RARAD_SCALE_BITS 0x00007000
558#define TXDRSIZE_RARAD_SCALE_S 12
559#define TXDRSIZE_RAMODSIZE_BITS 0x00000FFF
560#define TXDRSIZE_RAMODSIZE_S 0
561
562/*****************************************************************************
563 * DEFERRED and BUS ERROR EXTENSION
564 ****************************************************************************/
565
566/*
567 * TXDEFR register - Deferred exception control
568 */
569#define TXDEFR_REGNUM 20
570#define TXDEFR_DEFAULT 0 /* All fields default to zero */
571
572/*
573 * Bus error state is a multi-bit positive/negative event notification from
574 * the bus infrastructure.
575 */
576#define TXDEFR_BUS_ERR_BIT 0x80000000 /* Set if error (LSB STATE) */
577#define TXDEFR_BUS_ERRI_BIT 0x40000000 /* Fetch returned error */
578#define TXDEFR_BUS_STATE_BITS 0x3F000000 /* Bus event/state data */
579#define TXDEFR_BUS_STATE_S 24
580#define TXDEFR_BUS_TRIG_BIT 0x00800000 /* Set when bus error seen */
581
582/*
583 * Bus events are collected by background code in a deferred manner unless
584 * selected to trigger an extended interrupt HALT trigger when they occur.
585 */
586#define TXDEFR_BUS_ICTRL_BIT 0x00000080 /* Enable interrupt trigger */
587
588/*
589 * CHIP Automatic Mips Allocation control registers
590 * ------------------------------------------------
591 */
592
593/* CT Bank AMA Registers */
594#define TXAMAREG0_REGNUM 24
595#ifdef METAC_1_2
596#define TXAMAREG0_CTRL_BITS 0x07000000
597#else /* METAC_1_2 */
598#define TXAMAREG0_RCOFF_BIT 0x08000000
599#define TXAMAREG0_DLINEHLT_BIT 0x04000000
600#define TXAMAREG0_DLINEDIS_BIT 0x02000000
601#define TXAMAREG0_CYCSTRICT_BIT 0x01000000
602#define TXAMAREG0_CTRL_BITS (TXAMAREG0_RCOFF_BIT | \
603 TXAMAREG0_DLINEHLT_BIT | \
604 TXAMAREG0_DLINEDIS_BIT | \
605 TXAMAREG0_CYCSTRICT_BIT)
606#endif /* !METAC_1_2 */
607#define TXAMAREG0_CTRL_S 24
608#define TXAMAREG0_MDM_BIT 0x00400000
609#define TXAMAREG0_MPF_BIT 0x00200000
610#define TXAMAREG0_MPE_BIT 0x00100000
611#define TXAMAREG0_MASK_BITS (TXAMAREG0_MDM_BIT | \
612 TXAMAREG0_MPF_BIT | \
613 TXAMAREG0_MPE_BIT)
614#define TXAMAREG0_MASK_S 20
615#define TXAMAREG0_SDM_BIT 0x00040000
616#define TXAMAREG0_SPF_BIT 0x00020000
617#define TXAMAREG0_SPE_BIT 0x00010000
618#define TXAMAREG0_STATUS_BITS (TXAMAREG0_SDM_BIT | \
619 TXAMAREG0_SPF_BIT | \
620 TXAMAREG0_SPE_BIT)
621#define TXAMAREG0_STATUS_S 16
622#define TXAMAREG0_PRIORITY_BITS 0x0000FF00
623#define TXAMAREG0_PRIORITY_S 8
624#define TXAMAREG0_BVALUE_BITS 0x000000FF
625#define TXAMAREG0_BVALUE_S 0
626
627#define TXAMAREG1_REGNUM 25
628#define TXAMAREG1_DELAYC_BITS 0x07FFFFFF
629#define TXAMAREG1_DELAYC_S 0
630
631#define TXAMAREG2_REGNUM 26
632#ifdef METAC_1_2
633#define TXAMAREG2_DLINEC_BITS 0x00FFFFFF
634#define TXAMAREG2_DLINEC_S 0
635#else /* METAC_1_2 */
636#define TXAMAREG2_IRQPRIORITY_BIT 0xFF000000
637#define TXAMAREG2_IRQPRIORITY_S 24
638#define TXAMAREG2_DLINEC_BITS 0x00FFFFF0
639#define TXAMAREG2_DLINEC_S 4
640#endif /* !METAC_1_2 */
641
642#define TXAMAREG3_REGNUM 27
643#define TXAMAREG2_AMABLOCK_BIT 0x00080000
644#define TXAMAREG2_AMAC_BITS 0x0000FFFF
645#define TXAMAREG2_AMAC_S 0
646
647/*****************************************************************************
648 * FPU EXTENSIONS
649 ****************************************************************************/
650/*
651 * The following registers only exist in FPU enabled cores.
652 */
653
654/*
655 * TXMODE register - FPU rounding mode control/status fields
656 */
657#define TXMODE_FPURMODE_BITS 0x00030000
658#define TXMODE_FPURMODE_S 16
659#define TXMODE_FPURMODEWRITE_BIT 0x00040000 /* Set to change FPURMODE */
660
661/*
662 * TXDEFR register - FPU exception handling/state is a significant source
663 * of deferrable errors. Run-time S/W can move handling to interrupt level
664 * using DEFR instruction to collect state.
665 */
666#define TXDEFR_FPE_FE_BITS 0x003F0000 /* Set by FPU_FE events */
667#define TXDEFR_FPE_FE_S 16
668
669#define TXDEFR_FPE_INEXACT_FE_BIT 0x010000
670#define TXDEFR_FPE_UNDERFLOW_FE_BIT 0x020000
671#define TXDEFR_FPE_OVERFLOW_FE_BIT 0x040000
672#define TXDEFR_FPE_DIVBYZERO_FE_BIT 0x080000
673#define TXDEFR_FPE_INVALID_FE_BIT 0x100000
674#define TXDEFR_FPE_DENORMAL_FE_BIT 0x200000
675
676#define TXDEFR_FPE_ICTRL_BITS 0x000003F /* Route to interrupts */
677#define TXDEFR_FPE_ICTRL_S 0
678
679#define TXDEFR_FPE_INEXACT_ICTRL_BIT 0x01
680#define TXDEFR_FPE_UNDERFLOW_ICTRL_BIT 0x02
681#define TXDEFR_FPE_OVERFLOW_ICTRL_BIT 0x04
682#define TXDEFR_FPE_DIVBYZERO_ICTRL_BIT 0x08
683#define TXDEFR_FPE_INVALID_ICTRL_BIT 0x10
684#define TXDEFR_FPE_DENORMAL_ICTRL_BIT 0x20
685
686/*
687 * DETAILED FPU RELATED VALUES
688 * ---------------------------
689 */
690
691/*
692 * Rounding mode field in TXMODE can hold a number of logical values
693 */
694#define METAG_FPURMODE_TONEAREST 0x0 /* Default */
695#define METAG_FPURMODE_TOWARDZERO 0x1
696#define METAG_FPURMODE_UPWARD 0x2
697#define METAG_FPURMODE_DOWNWARD 0x3
698
699/*
700 * In order to set the TXMODE register field that controls the rounding mode
701 * an extra bit must be set in the value written versus that read in order
702 * to gate writes to the rounding mode field. This allows other non-FPU code
703 * to modify TXMODE without knowledge of the FPU units presence and not
704 * influence the FPU rounding mode. This macro adds the required bit so new
705 * rounding modes are accepted.
706 */
707#define TXMODE_FPURMODE_SET(FPURMode) \
708 (TXMODE_FPURMODEWRITE_BIT + ((FPURMode)<<TXMODE_FPURMODE_S))
709
710/*
711 * To successfully restore TXMODE to zero at the end of the function the
712 * following value (rather than zero) must be used.
713 */
714#define TXMODE_FPURMODE_RESET (TXMODE_FPURMODEWRITE_BIT)
715
716/*
717 * In TXSTATUS a special bit exists to indicate if FPU H/W has been accessed
718 * since it was last reset.
719 */
720#define TXSTATUS_FPACTIVE_BIT 0x01000000
721
722/*
723 * Exception state (see TXDEFR_FPU_FE_*) and enabling (for interrupt
724 * level processing (see TXDEFR_FPU_ICTRL_*) are controlled by similar
725 * bit mask locations within each field.
726 */
727#define METAG_FPU_FE_INEXACT 0x01
728#define METAG_FPU_FE_UNDERFLOW 0x02
729#define METAG_FPU_FE_OVERFLOW 0x04
730#define METAG_FPU_FE_DIVBYZERO 0x08
731#define METAG_FPU_FE_INVALID 0x10
732#define METAG_FPU_FE_DENORMAL 0x20
733#define METAG_FPU_FE_ALL_EXCEPT (METAG_FPU_FE_INEXACT | \
734 METAG_FPU_FE_UNDERFLOW | \
735 METAG_FPU_FE_OVERFLOW | \
736 METAG_FPU_FE_DIVBYZERO | \
737 METAG_FPU_FE_INVALID | \
738 METAG_FPU_FE_DENORMAL)
739
740/*****************************************************************************
741 * THREAD CONTROL, ERROR, OR INTERRUPT STATE EXTENSIONS
742 ****************************************************************************/
743/*
744 * The following values are only relevant to code that externally controls
745 * threads, handles errors/interrupts, and/or set-up interrupt/error handlers
746 * for subsequent use.
747 */
748
749/*
750 * TXENABLE register fields - only ENABLE_BIT is potentially read/write
751 */
752#define TXENABLE_MAJOR_REV_BITS 0xFF000000
753#define TXENABLE_MAJOR_REV_S 24
754#define TXENABLE_MINOR_REV_BITS 0x00FF0000
755#define TXENABLE_MINOR_REV_S 16
756#define TXENABLE_CLASS_BITS 0x0000F000
757#define TXENABLE_CLASS_S 12
758#define TXENABLE_CLASS_DSP 0x0 /* -> DSP Thread */
759#define TXENABLE_CLASS_LDSP 0x8 /* -> DSP LITE Thread */
760#define TXENABLE_CLASS_GP 0xC /* -> General Purpose Thread */
761#define TXENABLE_CLASSALT_LFPU 0x2 /* Set to indicate LITE FPU */
762#define TXENABLE_CLASSALT_FPUR8 0x1 /* Set to indicate 8xFPU regs */
763#define TXENABLE_MTXARCH_BIT 0x00000800
764#define TXENABLE_STEP_REV_BITS 0x000000F0
765#define TXENABLE_STEP_REV_S 4
766#define TXENABLE_STOPPED_BIT 0x00000004 /* TXOFF due to ENABLE->0 */
767#define TXENABLE_OFF_BIT 0x00000002 /* Thread is in off state */
768#define TXENABLE_ENABLE_BIT 0x00000001 /* Set if running */
769
770/*
771 * TXSTATUS register - used by external/internal interrupt/error handler
772 */
773#define TXSTATUS_CB1MARKER_BIT 0x00800000 /* -> int level mem state */
774#define TXSTATUS_CBMARKER_BIT 0x00400000 /* -> mem i/f state dumped */
775#define TXSTATUS_MEM_FAULT_BITS 0x00300000
776#define TXSTATUS_MEM_FAULT_S 20
777#define TXSTATUS_MEMFAULT_NONE 0x0 /* -> No memory fault */
778#define TXSTATUS_MEMFAULT_GEN 0x1 /* -> General fault */
779#define TXSTATUS_MEMFAULT_PF 0x2 /* -> Page fault */
780#define TXSTATUS_MEMFAULT_RO 0x3 /* -> Read only fault */
781#define TXSTATUS_MAJOR_HALT_BITS 0x000C0000
782#define TXSTATUS_MAJOR_HALT_S 18
783#define TXSTATUS_MAJHALT_TRAP 0x0 /* -> SWITCH inst used */
784#define TXSTATUS_MAJHALT_INST 0x1 /* -> Unknown inst or fetch */
785#define TXSTATUS_MAJHALT_PRIV 0x2 /* -> Internal privilege */
786#define TXSTATUS_MAJHALT_MEM 0x3 /* -> Memory i/f fault */
787#define TXSTATUS_L_STEP_BITS 0x00000800 /* -> Progress of L oper */
788#define TXSTATUS_LSM_STEP_BITS 0x00000700 /* -> Progress of L/S mult */
789#define TXSTATUS_LSM_STEP_S 8
790#define TXSTATUS_FLAG_BITS 0x0000001F /* -> All the flags */
791#define TXSTATUS_SCC_BIT 0x00000010 /* -> Split-16 flags ... */
792#define TXSTATUS_SCF_LZ_BIT 0x00000008 /* -> Split-16 Low Z flag */
793#define TXSTATUS_SCF_HZ_BIT 0x00000004 /* -> Split-16 High Z flag */
794#define TXSTATUS_SCF_HC_BIT 0x00000002 /* -> Split-16 High C flag */
795#define TXSTATUS_SCF_LC_BIT 0x00000001 /* -> Split-16 Low C flag */
796#define TXSTATUS_CF_Z_BIT 0x00000008 /* -> Condition Z flag */
797#define TXSTATUS_CF_N_BIT 0x00000004 /* -> Condition N flag */
798#define TXSTATUS_CF_O_BIT 0x00000002 /* -> Condition O flag */
799#define TXSTATUS_CF_C_BIT 0x00000001 /* -> Condition C flag */
800
801/*
802 * TXCATCH0-3 register contents may store information on a memory operation
803 * that has failed if the bit TXSTATUS_CBMARKER_BIT is set.
804 */
805#define TXCATCH0_REGNUM 16
806#define TXCATCH1_REGNUM 17
807#define TXCATCH1_ADDR_BITS 0xFFFFFFFF /* TXCATCH1 is Addr 0-31 */
808#define TXCATCH1_ADDR_S 0
809#define TXCATCH2_REGNUM 18
810#define TXCATCH2_DATA0_BITS 0xFFFFFFFF /* TXCATCH2 is Data 0-31 */
811#define TXCATCH2_DATA0_S 0
812#define TXCATCH3_REGNUM 19
813#define TXCATCH3_DATA1_BITS 0xFFFFFFFF /* TXCATCH3 is Data 32-63 */
814#define TXCATCH3_DATA1_S 0
815
816/*
817 * Detailed catch state information
818 * --------------------------------
819 */
820
821/* Contents of TXCATCH0 register */
822#define TXCATCH0_LDRXX_BITS 0xF8000000 /* Load destination reg 0-31 */
823#define TXCATCH0_LDRXX_S 27
824#define TXCATCH0_LDDST_BITS 0x07FF0000 /* Load destination bits */
825#define TXCATCH0_LDDST_S 16
826#define TXCATCH0_LDDST_D1DSP 0x400 /* One bit set if it's a LOAD */
827#define TXCATCH0_LDDST_D0DSP 0x200
828#define TXCATCH0_LDDST_TMPLT 0x100
829#define TXCATCH0_LDDST_TR 0x080
830#ifdef METAC_2_1
831#define TXCATCH0_LDDST_FPU 0x040
832#endif
833#define TXCATCH0_LDDST_PC 0x020
834#define TXCATCH0_LDDST_A1 0x010
835#define TXCATCH0_LDDST_A0 0x008
836#define TXCATCH0_LDDST_D1 0x004
837#define TXCATCH0_LDDST_D0 0x002
838#define TXCATCH0_LDDST_CT 0x001
839#ifdef METAC_2_1
840#define TXCATCH0_WATCHSTOP_BIT 0x00004000 /* Set if Data Watch set fault */
841#endif
842#define TXCATCH0_WATCHS_BIT 0x00004000 /* Set if Data Watch set fault */
843#define TXCATCH0_WATCH1_BIT 0x00002000 /* Set if Data Watch 1 matches */
844#define TXCATCH0_WATCH0_BIT 0x00001000 /* Set if Data Watch 0 matches */
845#define TXCATCH0_FAULT_BITS 0x00000C00 /* See TXSTATUS_MEMFAULT_* */
846#define TXCATCH0_FAULT_S 10
847#define TXCATCH0_PRIV_BIT 0x00000200 /* Privilege of transaction */
848#define TXCATCH0_READ_BIT 0x00000100 /* Set for Read or Load cases */
849
850#ifdef METAC_2_1
851/* LNKGET Marker bit in TXCATCH0 */
852#define TXCATCH0_LNKGET_MARKER_BIT 0x00000008
853#define TXCATCH0_PREPROC_BIT 0x00000004
854#endif
855
856/* Loads are indicated by one of the LDDST bits being set */
857#define TXCATCH0_LDM16_BIT 0x00000004 /* Load M16 flag */
858#define TXCATCH0_LDL2L1_BITS 0x00000003 /* Load data size L2,L1 */
859#define TXCATCH0_LDL2L1_S 0
860
861/* Reads are indicated by the READ bit being set without LDDST bits */
862#define TXCATCH0_RAXX_BITS 0x0000001F /* RAXX issue port for read */
863#define TXCATCH0_RAXX_S 0
864
865/* Write operations are all that remain if READ bit is not set */
866#define TXCATCH0_WMASK_BITS 0x000000FF /* Write byte lane mask */
867#define TXCATCH0_WMASK_S 0
868
869#ifdef METAC_2_1
870
871/* When a FPU exception is signalled then FPUSPEC == FPUSPEC_TAG */
872#define TXCATCH0_FPURDREG_BITS 0xF8000000
873#define TXCATCH0_FPURDREG_S 27
874#define TXCATCH0_FPUR1REG_BITS 0x07C00000
875#define TXCATCH0_FPUR1REG_S 22
876#define TXCATCH0_FPUSPEC_BITS 0x000F0000
877#define TXCATCH0_FPUSPEC_S 16
878#define TXCATCH0_FPUSPEC_TAG 0xF
879#define TXCATCH0_FPUINSTA_BIT 0x00001000
880#define TXCATCH0_FPUINSTQ_BIT 0x00000800
881#define TXCATCH0_FPUINSTZ_BIT 0x00000400
882#define TXCATCH0_FPUINSTN_BIT 0x00000200
883#define TXCATCH0_FPUINSTO3O_BIT 0x00000100
884#define TXCATCH0_FPUWIDTH_BITS 0x000000C0
885#define TXCATCH0_FPUWIDTH_S 6
886#define TXCATCH0_FPUWIDTH_FLOAT 0
887#define TXCATCH0_FPUWIDTH_DOUBLE 1
888#define TXCATCH0_FPUWIDTH_PAIRED 2
889#define TXCATCH0_FPUOPENC_BITS 0x0000003F
890#define TXCATCH0_FPUOPENC_S 0
891#define TXCATCH0_FPUOPENC_ADD 0 /* rop1=Rs1, rop3=Rs2 */
892#define TXCATCH0_FPUOPENC_SUB 1 /* rop1=Rs1, rop3=Rs2 */
893#define TXCATCH0_FPUOPENC_MUL 2 /* rop1=Rs1, rop2=Rs2 */
894#define TXCATCH0_FPUOPENC_ATOI 3 /* rop3=Rs */
895#define TXCATCH0_FPUOPENC_ATOX 4 /* rop3=Rs, uses #Imm */
896#define TXCATCH0_FPUOPENC_ITOA 5 /* rop3=Rs */
897#define TXCATCH0_FPUOPENC_XTOA 6 /* rop3=Rs, uses #Imm */
898#define TXCATCH0_FPUOPENC_ATOH 7 /* rop2=Rs */
899#define TXCATCH0_FPUOPENC_HTOA 8 /* rop2=Rs */
900#define TXCATCH0_FPUOPENC_DTOF 9 /* rop3=Rs */
901#define TXCATCH0_FPUOPENC_FTOD 10 /* rop3=Rs */
902#define TXCATCH0_FPUOPENC_DTOL 11 /* rop3=Rs */
903#define TXCATCH0_FPUOPENC_LTOD 12 /* rop3=Rs */
904#define TXCATCH0_FPUOPENC_DTOXL 13 /* rop3=Rs, uses #imm */
905#define TXCATCH0_FPUOPENC_XLTOD 14 /* rop3=Rs, uses #imm */
906#define TXCATCH0_FPUOPENC_CMP 15 /* rop1=Rs1, rop2=Rs2 */
907#define TXCATCH0_FPUOPENC_MIN 16 /* rop1=Rs1, rop2=Rs2 */
908#define TXCATCH0_FPUOPENC_MAX 17 /* rop1=Rs1, rop2=Rs2 */
909#define TXCATCH0_FPUOPENC_ADDRE 18 /* rop1=Rs1, rop3=Rs2 */
910#define TXCATCH0_FPUOPENC_SUBRE 19 /* rop1=Rs1, rop3=Rs2 */
911#define TXCATCH0_FPUOPENC_MULRE 20 /* rop1=Rs1, rop2=Rs2 */
912#define TXCATCH0_FPUOPENC_MXA 21 /* rop1=Rs1, rop2=Rs2, rop3=Rs3*/
913#define TXCATCH0_FPUOPENC_MXAS 22 /* rop1=Rs1, rop2=Rs2, rop3=Rs3*/
914#define TXCATCH0_FPUOPENC_MAR 23 /* rop1=Rs1, rop2=Rs2 */
915#define TXCATCH0_FPUOPENC_MARS 24 /* rop1=Rs1, rop2=Rs2 */
916#define TXCATCH0_FPUOPENC_MUZ 25 /* rop1=Rs1, rop2=Rs2, rop3=Rs3*/
917#define TXCATCH0_FPUOPENC_MUZS 26 /* rop1=Rs1, rop2=Rs2, rop3=Rs3*/
918#define TXCATCH0_FPUOPENC_RCP 27 /* rop2=Rs */
919#define TXCATCH0_FPUOPENC_RSQ 28 /* rop2=Rs */
920
921/* For floating point exceptions TXCATCH1 is used to carry extra data */
922#define TXCATCH1_FPUR2REG_BITS 0xF8000000
923#define TXCATCH1_FPUR2REG_S 27
924#define TXCATCH1_FPUR3REG_BITS 0x07C00000 /* Undefined if O3O set */
925#define TXCATCH1_FPUR3REG_S 22
926#define TXCATCH1_FPUIMM16_BITS 0x0000FFFF
927#define TXCATCH1_FPUIMM16_S 0
928
929#endif /* METAC_2_1 */
930
931/*
932 * TXDIVTIME register used to hold the partial base address of memory i/f
933 * state dump area. Now deprecated.
934 */
935#define TXDIVTIME_CBBASE_MASK 0x03FFFE00
936#define TXDIVTIME_CBBASE_LINBASE 0x80000000
937#define TXDIVTIME_CBBASE_LINBOFF 0x00000000 /* BGnd state */
938#define TXDIVTIME_CBBASE_LINIOFF 0x00000100 /* Int state */
939
940/*
941 * TXDIVTIME register used to indicate if the read pipeline was dirty when a
942 * thread was interrupted, halted, or generated an exception. It is invalid
943 * to attempt to issue a further pipeline read address while the read
944 * pipeline is in the dirty state.
945 */
946#define TXDIVTIME_RPDIRTY_BIT 0x80000000
947
948/*
949 * Further bits in the TXDIVTIME register allow interrupt handling code to
950 * short-cut the discovery the most significant bit last read from TXSTATI.
951 *
952 * This is the bit number of the trigger line that a low level interrupt
953 * handler should acknowledge and then perhaps the index of a corresponding
954 * handler function.
955 */
956#define TXDIVTIME_IRQENC_BITS 0x0F000000
957#define TXDIVTIME_IRQENC_S 24
958
959/*
960 * If TXDIVTIME_RPVALID_BIT is set the read pipeline contained significant
961 * information when the thread was interrupted|halted|exceptioned. Each slot
962 * containing data is indicated by a one bit in the corresponding
963 * TXDIVTIME_RPMASK_BITS bit (least significance bit relates to first
964 * location in read pipeline - most likely to have the 1 state). Empty slots
965 * contain zeroes with no interlock applied on reads if RPDIRTY is currently
966 * set with RPMASK itself being read-only state.
967 */
968#define TXDIVTIME_RPMASK_BITS 0x003F0000 /* -> Full (1) Empty (0) */
969#define TXDIVTIME_RPMASK_S 16
970
971/*
972 * TXPRIVEXT register can be used to single step thread execution and
973 * enforce synchronous memory i/f address checking for debugging purposes.
974 */
975#define TXPRIVEXT_TXSTEP_BIT 0x00000004
976#define TXPRIVEXT_MEMCHECK_BIT 0x00000002
977
978/*
979 * TXINTERNx registers holds internal state information for H/W debugging only
980 */
981#define TXINTERN0_REGNUM 23
982#define TXINTERN0_LOCK2_BITS 0xF0000000
983#define TXINTERN0_LOCK2_S 28
984#define TXINTERN0_LOCK1_BITS 0x0F000000
985#define TXINTERN0_LOCK1_S 24
986#define TXINTERN0_TIFDF_BITS 0x0000F000
987#define TXINTERN0_TIFDF_S 12
988#define TXINTERN0_TIFIB_BITS 0x00000F00
989#define TXINTERN0_TIFIB_S 8
990#define TXINTERN0_TIFAF_BITS 0x000000F0
991#define TXINTERN0_TIFAF_S 4
992#define TXINTERN0_MSTATE_BITS 0x0000000F
993#define TXINTERN0_MSTATE_S 0
994
995/*
996 * TXSTAT, TXMASK, TXPOLL, TXSTATI, TXMASKI, TXPOLLI registers from trigger
997 * bank all have similar contents (upper kick count bits not in MASK regs)
998 */
999#define TXSTAT_REGNUM 0
1000#define TXSTAT_TIMER_BIT 0x00000001
1001#define TXSTAT_TIMER_S 0
1002#define TXSTAT_KICK_BIT 0x00000002
1003#define TXSTAT_KICK_S 1
1004#define TXSTAT_DEFER_BIT 0x00000008
1005#define TXSTAT_DEFER_S 3
1006#define TXSTAT_EXTTRIG_BITS 0x0000FFF0
1007#define TXSTAT_EXTTRIG_S 4
1008#define TXSTAT_FPE_BITS 0x003F0000
1009#define TXSTAT_FPE_S 16
1010#define TXSTAT_FPE_DENORMAL_BIT 0x00200000
1011#define TXSTAT_FPE_DENORMAL_S 21
1012#define TXSTAT_FPE_INVALID_BIT 0x00100000
1013#define TXSTAT_FPE_INVALID_S 20
1014#define TXSTAT_FPE_DIVBYZERO_BIT 0x00080000
1015#define TXSTAT_FPE_DIVBYZERO_S 19
1016#define TXSTAT_FPE_OVERFLOW_BIT 0x00040000
1017#define TXSTAT_FPE_OVERFLOW_S 18
1018#define TXSTAT_FPE_UNDERFLOW_BIT 0x00020000
1019#define TXSTAT_FPE_UNDERFLOW_S 17
1020#define TXSTAT_FPE_INEXACT_BIT 0x00010000
1021#define TXSTAT_FPE_INEXACT_S 16
1022#define TXSTAT_BUSERR_BIT 0x00800000 /* Set if bus error/ack state */
1023#define TXSTAT_BUSERR_S 23
1024#define TXSTAT_BUSSTATE_BITS 0xFF000000 /* Read only */
1025#define TXSTAT_BUSSTATE_S 24
1026#define TXSTAT_KICKCNT_BITS 0xFFFF0000
1027#define TXSTAT_KICKCNT_S 16
1028#define TXMASK_REGNUM 1
1029#define TXSTATI_REGNUM 2
1030#define TXSTATI_BGNDHALT_BIT 0x00000004
1031#define TXMASKI_REGNUM 3
1032#define TXPOLL_REGNUM 4
1033#define TXPOLLI_REGNUM 6
1034
1035/*
1036 * TXDRCTRL register can be used to partition the DSP RAM space available to
1037 * this thread at startup. This is achieved by offsetting the region allocated
1038 * to each thread.
1039 */
1040#define TXDRCTRL_D1PARTOR_BITS 0x00000F00 /* OR's into top 4 bits */
1041#define TXDRCTRL_D1PARTOR_S 8
1042#define TXDRCTRL_D0PARTOR_BITS 0x0000000F /* OR's into top 4 bits */
1043#define TXDRCTRL_D0PARTOR_S 0
1044/* Given extracted Pow and Or fields this is threads base within DSP RAM */
1045#define TXDRCTRL_DXBASE(Pow, Or) ((Or)<<((Pow)-4))
1046
1047/*****************************************************************************
1048 * RUN TIME TRACE CONTROL REGISTERS
1049 ****************************************************************************/
1050/*
1051 * The following values are only relevant to code that implements run-time
1052 * trace features within the META Core
1053 */
1054#define TTEXEC TT.0
1055#define TTCTRL TT.1
1056#define TTMARK TT.2
1057#define TTREC TT.3
1058#define GTEXEC TT.4
1059
1060#define TTEXEC_REGNUM 0
1061#define TTEXEC_EXTTRIGAND_BITS 0x7F000000
1062#define TTEXEC_EXTTRIGAND_S 24
1063#define TTEXEC_EXTTRIGEN_BIT 0x00008000
1064#define TTEXEC_EXTTRIGMATCH_BITS 0x00007F00
1065#define TTEXEC_EXTTRIGMATCH_S 8
1066#define TTEXEC_TCMODE_BITS 0x00000003
1067#define TTEXEC_TCMODE_S 0
1068
1069#define TTCTRL_REGNUM 1
1070#define TTCTRL_TRACETT_BITS 0x00008000
1071#define TTCTRL_TRACETT_S 15
1072#define TTCTRL_TRACEALL_BITS 0x00002000
1073#define TTCTRL_TRACEALL_S 13
1074#ifdef METAC_2_1
1075#define TTCTRL_TRACEALLTAG_BITS 0x00000400
1076#define TTCTRL_TRACEALLTAG_S 10
1077#endif /* METAC_2_1 */
1078#define TTCTRL_TRACETAG_BITS 0x00000200
1079#define TTCTRL_TRACETAG_S 9
1080#define TTCTRL_TRACETTPC_BITS 0x00000080
1081#define TTCTRL_TRACETTPC_S 7
1082#define TTCTRL_TRACEMPC_BITS 0x00000020
1083#define TTCTRL_TRACEMPC_S 5
1084#define TTCTRL_TRACEEN_BITS 0x00000008
1085#define TTCTRL_TRACEEN_S 3
1086#define TTCTRL_TRACEEN1_BITS 0x00000004
1087#define TTCTRL_TRACEEN1_S 2
1088#define TTCTRL_TRACEPC_BITS 0x00000002
1089#define TTCTRL_TRACEPC_S 1
1090
1091#ifdef METAC_2_1
1092#define TTMARK_REGNUM 2
1093#define TTMARK_BITS 0xFFFFFFFF
1094#define TTMARK_S 0x0
1095
1096#define TTREC_REGNUM 3
1097#define TTREC_BITS 0xFFFFFFFFFFFFFFFF
1098#define TTREC_S 0x0
1099#endif /* METAC_2_1 */
1100
1101#define GTEXEC_REGNUM 4
1102#define GTEXEC_DCRUN_BITS 0x80000000
1103#define GTEXEC_DCRUN_S 31
1104#define GTEXEC_ICMODE_BITS 0x0C000000
1105#define GTEXEC_ICMODE_S 26
1106#define GTEXEC_TCMODE_BITS 0x03000000
1107#define GTEXEC_TCMODE_S 24
1108#define GTEXEC_PERF1CMODE_BITS 0x00040000
1109#define GTEXEC_PERF1CMODE_S 18
1110#define GTEXEC_PERF0CMODE_BITS 0x00010000
1111#define GTEXEC_PERF0CMODE_S 16
1112#define GTEXEC_REFMSEL_BITS 0x0000F000
1113#define GTEXEC_REFMSEL_S 12
1114#define GTEXEC_METRICTH_BITS 0x000003FF
1115#define GTEXEC_METRICTH_S 0
1116
1117#ifdef METAC_2_1
1118/*
1119 * Clock Control registers
1120 * -----------------------
1121 */
1122#define TXCLKCTRL_REGNUM 22
1123
1124/*
1125 * Default setting is with clocks always on (DEFON), turning all clocks off
1126 * can only be done from external devices (OFF), enabling automatic clock
1127 * gating will allow clocks to stop as units fall idle.
1128 */
1129#define TXCLKCTRL_ALL_OFF 0x02222222
1130#define TXCLKCTRL_ALL_DEFON 0x01111111
1131#define TXCLKCTRL_ALL_AUTO 0x02222222
1132
1133/*
1134 * Individual fields control caches, floating point and main data/addr units
1135 */
1136#define TXCLKCTRL_CLOCKIC_BITS 0x03000000
1137#define TXCLKCTRL_CLOCKIC_S 24
1138#define TXCLKCTRL_CLOCKDC_BITS 0x00300000
1139#define TXCLKCTRL_CLOCKDC_S 20
1140#define TXCLKCTRL_CLOCKFP_BITS 0x00030000
1141#define TXCLKCTRL_CLOCKFP_S 16
1142#define TXCLKCTRL_CLOCKD1_BITS 0x00003000
1143#define TXCLKCTRL_CLOCKD1_S 12
1144#define TXCLKCTRL_CLOCKD0_BITS 0x00000300
1145#define TXCLKCTRL_CLOCKD0_S 8
1146#define TXCLKCTRL_CLOCKA1_BITS 0x00000030
1147#define TXCLKCTRL_CLOCKA1_S 4
1148#define TXCLKCTRL_CLOCKA0_BITS 0x00000003
1149#define TXCLKCTRL_CLOCKA0_S 0
1150
1151/*
1152 * Individual settings for each field are common
1153 */
1154#define TXCLKCTRL_CLOCKxx_OFF 0
1155#define TXCLKCTRL_CLOCKxx_DEFON 1
1156#define TXCLKCTRL_CLOCKxx_AUTO 2
1157
1158#endif /* METAC_2_1 */
1159
1160#ifdef METAC_2_1
1161/*
1162 * Fast interrupt new bits
1163 * ------------------------------------
1164 */
1165#define TXSTATUS_IPTOGGLE_BIT 0x80000000 /* Prev PToggle of TXPRIVEXT */
1166#define TXSTATUS_ISTATE_BIT 0x40000000 /* IState bit */
1167#define TXSTATUS_IWAIT_BIT 0x20000000 /* wait indefinitely in decision step*/
cacd2c41 1168#define TXSTATUS_IEXCEPT_BIT 0x10000000 /* Indicate an exception occurred */
af8a1049
JH		 1169#define TXSTATUS_IRPCOUNT_BITS 0x0E000000 /* Number of 'dirty' date entries*/
1170#define TXSTATUS_IRPCOUNT_S 25
1171#define TXSTATUS_IRQSTAT_BITS 0x0000F000 /* IRQEnc bits, trigger or interrupts */
1172#define TXSTATUS_IRQSTAT_S 12
1173#define TXSTATUS_LNKSETOK_BIT 0x00000020 /* LNKSetOK bit, successful LNKSET */
1174
1175/* New fields in TXDE for fast interrupt system */
1176#define TXDIVTIME_IACTIVE_BIT 0x00008000 /* Enable new interrupt system */
1177#define TXDIVTIME_INONEST_BIT 0x00004000 /* Gate nested interrupt */
1178#define TXDIVTIME_IREGIDXGATE_BIT 0x00002000 /* gate of the IRegIdex field */
1179#define TXDIVTIME_IREGIDX_BITS 0x00001E00 /* Index of A0.0/1 replaces */
1180#define TXDIVTIME_IREGIDX_S 9
1181#define TXDIVTIME_NOST_BIT 0x00000100 /* disable superthreading bit */
1182#endif
1183
1184#endif /* _ASM_METAG_REGS_H_ */
Linux 6.x block layer and io_uring tree(s)