[linux-2.6-block.git] / arch / m68k / include / asm / mac_iop.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * I/O Processor (IOP) defines and structures, mostly snagged from A/UX
 * header files.
 *
 * The original header from which this was taken is copyrighted. I've done some
 * rewriting (in fact my changes make this a bit more readable, IMHO) but some
 * more should be done.
 */

/*
 * This is the base address of the IOPs. Use this as the address of
 * a "struct iop" (see below) to see where the actual registers fall.
 */

#define SCC_IOP_BASE_IIFX	(0x50F04000)
#define ISM_IOP_BASE_IIFX	(0x50F12000)

#define SCC_IOP_BASE_QUADRA	(0x50F0C000)
#define ISM_IOP_BASE_QUADRA	(0x50F1E000)

/* IOP status/control register bits: */

#define	IOP_BYPASS	0x01	/* bypass-mode hardware access */
#define	IOP_AUTOINC	0x02	/* allow autoincrement of ramhi/lo */
#define	IOP_RUN		0x04	/* set to 0 to reset IOP chip */
#define	IOP_IRQ		0x08	/* generate IRQ to IOP if 1 */
#define	IOP_INT0	0x10	/* intr priority from IOP to host */
#define	IOP_INT1	0x20	/* intr priority from IOP to host */
#define	IOP_HWINT	0x40	/* IRQ from hardware; bypass mode only */
#define	IOP_DMAINACTIVE	0x80	/* no DMA request active; bypass mode only */

#define NUM_IOPS	2
#define NUM_IOP_CHAN	7
#define NUM_IOP_MSGS	NUM_IOP_CHAN*8
#define IOP_MSG_LEN	32

/* IOP reference numbers, used by the globally-visible iop_xxx functions */

#define IOP_NUM_SCC	0
#define IOP_NUM_ISM	1

/* IOP channel states */

#define IOP_MSG_IDLE		0       /* idle                         */
#define IOP_MSG_NEW		1       /* new message sent             */
#define IOP_MSG_RCVD		2       /* message received; processing */
#define IOP_MSG_COMPLETE	3       /* message processing complete  */

/* IOP message status codes */

#define IOP_MSGSTATUS_UNUSED	0	/* Unused message structure        */
#define IOP_MSGSTATUS_WAITING	1	/* waiting for channel             */
#define IOP_MSGSTATUS_SENT	2	/* message sent, awaiting reply    */
#define IOP_MSGSTATUS_COMPLETE	3	/* message complete and reply rcvd */
#define IOP_MSGSTATUS_UNSOL	6	/* message is unsolicited          */

/* IOP memory addresses of the members of the mac_iop_kernel structure. */

#define IOP_ADDR_MAX_SEND_CHAN	0x0200
#define IOP_ADDR_SEND_STATE	0x0201
#define IOP_ADDR_PATCH_CTRL	0x021F
#define IOP_ADDR_SEND_MSG	0x0220
#define IOP_ADDR_MAX_RECV_CHAN	0x0300
#define IOP_ADDR_RECV_STATE	0x0301
#define IOP_ADDR_ALIVE		0x031F
#define IOP_ADDR_RECV_MSG	0x0320

#ifndef __ASSEMBLY__

/*
 * IOP Control registers, staggered because in usual Apple style they were
 * too lazy to decode the A0 bit. This structure is assumed to begin at
 * one of the xxx_IOP_BASE addresses given above.
 */

struct mac_iop {
    __u8	ram_addr_hi;	/* shared RAM address hi byte */
    __u8	pad0;
    __u8	ram_addr_lo;	/* shared RAM address lo byte */
    __u8	pad1;
    __u8	status_ctrl;	/* status/control register */
    __u8	pad2[3];
    __u8	ram_data;	/* RAM data byte at ramhi/lo */

    __u8	pad3[23];

    /* Bypass-mode hardware access registers */

    union {
	struct {		/* SCC registers */
	    __u8 sccb_cmd;	/* SCC B command reg */
	    __u8 pad4;
	    __u8 scca_cmd;	/* SCC A command reg */
	    __u8 pad5;
	    __u8 sccb_data;	/* SCC B data */
	    __u8 pad6;
	    __u8 scca_data;	/* SCC A data */
	} scc_regs;

	struct {		/* ISM registers */
	    __u8 wdata;		/* write a data byte */
	    __u8 pad7;
	    __u8 wmark;		/* write a mark byte */
	    __u8 pad8;
	    __u8 wcrc;		/* write 2-byte crc to disk */
	    __u8 pad9;
	    __u8 wparams;	/* write the param regs */
	    __u8 pad10;
	    __u8 wphase;	/* write the phase states & dirs */
	    __u8 pad11;
	    __u8 wsetup;	/* write the setup register */
	    __u8 pad12;
	    __u8 wzeroes;	/* mode reg: 1's clr bits, 0's are x */
	    __u8 pad13;
	    __u8 wones;		/* mode reg: 1's set bits, 0's are x */
	    __u8 pad14;
	    __u8 rdata;		/* read a data byte */
	    __u8 pad15;
	    __u8 rmark;		/* read a mark byte */
	    __u8 pad16;
	    __u8 rerror;	/* read the error register */
	    __u8 pad17;
	    __u8 rparams;	/* read the param regs */
	    __u8 pad18;
	    __u8 rphase;	/* read the phase states & dirs */
	    __u8 pad19;
	    __u8 rsetup;	/* read the setup register */
	    __u8 pad20;
	    __u8 rmode;		/* read the mode register */
	    __u8 pad21;
	    __u8 rhandshake;	/* read the handshake register */
	} ism_regs;
    } b;
};

/* This structure is used to track IOP messages in the Linux kernel */

struct iop_msg {
	struct iop_msg	*next;		/* next message in queue or NULL     */
	uint	iop_num;		/* IOP number                        */
	uint	channel;		/* channel number                    */
	void	*caller_priv;		/* caller private data               */
	int	status;			/* status of this message            */
	__u8	message[IOP_MSG_LEN];	/* the message being sent/received   */
	__u8	reply[IOP_MSG_LEN];	/* the reply to the message          */
	void	(*handler)(struct iop_msg *);
					/* function to call when reply recvd */
};

extern int iop_scc_present,iop_ism_present;

extern int iop_listen(uint, uint,
			void (*handler)(struct iop_msg *),
			const char *);
extern int iop_send_message(uint, uint, void *, uint, __u8 *,
			    void (*)(struct iop_msg *));
extern void iop_complete_message(struct iop_msg *);
extern void iop_upload_code(uint, __u8 *, uint, __u16);
extern void iop_download_code(uint, __u8 *, uint, __u16);
extern __u8 *iop_compare_code(uint, __u8 *, uint, __u16);

extern void iop_register_interrupts(void);

#endif /* __ASSEMBLY__ */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
1da177e4 LT	2	/*
	3	* I/O Processor (IOP) defines and structures, mostly snagged from A/UX
	4	* header files.
	5	*
	6	* The original header from which this was taken is copyrighted. I've done some
	7	* rewriting (in fact my changes make this a bit more readable, IMHO) but some
	8	* more should be done.
	9	*/
	10
	11	/*
	12	* This is the base address of the IOPs. Use this as the address of
	13	* a "struct iop" (see below) to see where the actual registers fall.
	14	*/
	15
	16	#define SCC_IOP_BASE_IIFX (0x50F04000)
	17	#define ISM_IOP_BASE_IIFX (0x50F12000)
	18
	19	#define SCC_IOP_BASE_QUADRA (0x50F0C000)
	20	#define ISM_IOP_BASE_QUADRA (0x50F1E000)
	21
	22	/* IOP status/control register bits: */
	23
	24	#define IOP_BYPASS 0x01 /* bypass-mode hardware access */
	25	#define IOP_AUTOINC 0x02 /* allow autoincrement of ramhi/lo */
	26	#define IOP_RUN 0x04 /* set to 0 to reset IOP chip */
	27	#define IOP_IRQ 0x08 /* generate IRQ to IOP if 1 */
	28	#define IOP_INT0 0x10 /* intr priority from IOP to host */
	29	#define IOP_INT1 0x20 /* intr priority from IOP to host */
	30	#define IOP_HWINT 0x40 /* IRQ from hardware; bypass mode only */
	31	#define IOP_DMAINACTIVE 0x80 /* no DMA request active; bypass mode only */
	32
	33	#define NUM_IOPS 2
	34	#define NUM_IOP_CHAN 7
	35	#define NUM_IOP_MSGS NUM_IOP_CHAN*8
	36	#define IOP_MSG_LEN 32
	37
	38	/* IOP reference numbers, used by the globally-visible iop_xxx functions */
	39
	40	#define IOP_NUM_SCC 0
	41	#define IOP_NUM_ISM 1
	42
	43	/* IOP channel states */
	44
	45	#define IOP_MSG_IDLE 0 /* idle */
	46	#define IOP_MSG_NEW 1 /* new message sent */
	47	#define IOP_MSG_RCVD 2 /* message received; processing */
	48	#define IOP_MSG_COMPLETE 3 /* message processing complete */
	49
	50	/* IOP message status codes */
	51
efbec135	52	#define IOP_MSGSTATUS_UNUSED 0 /* Unused message structure */
1da177e4 LT	53	#define IOP_MSGSTATUS_WAITING 1 /* waiting for channel */
	54	#define IOP_MSGSTATUS_SENT 2 /* message sent, awaiting reply */
	55	#define IOP_MSGSTATUS_COMPLETE 3 /* message complete and reply rcvd */
	56	#define IOP_MSGSTATUS_UNSOL 6 /* message is unsolicited */
	57
	58	/* IOP memory addresses of the members of the mac_iop_kernel structure. */
	59
	60	#define IOP_ADDR_MAX_SEND_CHAN 0x0200
	61	#define IOP_ADDR_SEND_STATE 0x0201
	62	#define IOP_ADDR_PATCH_CTRL 0x021F
	63	#define IOP_ADDR_SEND_MSG 0x0220
	64	#define IOP_ADDR_MAX_RECV_CHAN 0x0300
	65	#define IOP_ADDR_RECV_STATE 0x0301
	66	#define IOP_ADDR_ALIVE 0x031F
	67	#define IOP_ADDR_RECV_MSG 0x0320
	68
	69	#ifndef __ASSEMBLY__
	70
	71	/*
	72	* IOP Control registers, staggered because in usual Apple style they were
	73	* too lazy to decode the A0 bit. This structure is assumed to begin at
	74	* one of the xxx_IOP_BASE addresses given above.
	75	*/
	76
	77	struct mac_iop {
	78	__u8 ram_addr_hi; /* shared RAM address hi byte */
	79	__u8 pad0;
	80	__u8 ram_addr_lo; /* shared RAM address lo byte */
	81	__u8 pad1;
	82	__u8 status_ctrl; /* status/control register */
	83	__u8 pad2[3];
	84	__u8 ram_data; /* RAM data byte at ramhi/lo */
	85
	86	__u8 pad3[23];
	87
	88	/* Bypass-mode hardware access registers */
	89
	90	union {
	91	struct { /* SCC registers */
	92	__u8 sccb_cmd; /* SCC B command reg */
	93	__u8 pad4;
	94	__u8 scca_cmd; /* SCC A command reg */
	95	__u8 pad5;
	96	__u8 sccb_data; /* SCC B data */
	97	__u8 pad6;
	98	__u8 scca_data; /* SCC A data */
	99	} scc_regs;
	100
	101	struct { /* ISM registers */
	102	__u8 wdata; /* write a data byte */
	103	__u8 pad7;
	104	__u8 wmark; /* write a mark byte */
	105	__u8 pad8;
	106	__u8 wcrc; /* write 2-byte crc to disk */
	107	__u8 pad9;
	108	__u8 wparams; /* write the param regs */
	109	__u8 pad10;
	110	__u8 wphase; /* write the phase states & dirs */
	111	__u8 pad11;
	112	__u8 wsetup; /* write the setup register */
	113	__u8 pad12;
	114	__u8 wzeroes; /* mode reg: 1's clr bits, 0's are x */
	115	__u8 pad13;
	116	__u8 wones; /* mode reg: 1's set bits, 0's are x */
117	__u8 pad14;
118	__u8 rdata; /* read a data byte */
119	__u8 pad15;
120	__u8 rmark; /* read a mark byte */
121	__u8 pad16;
122	__u8 rerror; /* read the error register */
123	__u8 pad17;
124	__u8 rparams; /* read the param regs */
125	__u8 pad18;
126	__u8 rphase; /* read the phase states & dirs */
127	__u8 pad19;
128	__u8 rsetup; /* read the setup register */
129	__u8 pad20;
130	__u8 rmode; /* read the mode register */
131	__u8 pad21;
132	__u8 rhandshake; /* read the handshake register */
133	} ism_regs;
134	} b;
135	};
136
137	/* This structure is used to track IOP messages in the Linux kernel */
138
139	struct iop_msg {
140	struct iop_msg next; / next message in queue or NULL */
141	uint iop_num; /* IOP number */
142	uint channel; /* channel number */
143	void caller_priv; / caller private data */
144	int status; /* status of this message */
145	__u8 message[IOP_MSG_LEN]; /* the message being sent/received */
146	__u8 reply[IOP_MSG_LEN]; /* the reply to the message */
2850bc27	147	void (handler)(struct iop_msg );
1da177e4 LT	148	/* function to call when reply recvd */
	149	};
	150
	151	extern int iop_scc_present,iop_ism_present;
	152
	153	extern int iop_listen(uint, uint,
2850bc27	154	void (handler)(struct iop_msg ),
1da177e4 LT	155	const char *);
1da177e4 LT	156	extern int iop_send_message(uint, uint, void , uint, __u8 ,
2850bc27	157	void ()(struct iop_msg ));
1da177e4 LT	158	extern void iop_complete_message(struct iop_msg *);
	159	extern void iop_upload_code(uint, __u8 *, uint, __u16);
	160	extern void iop_download_code(uint, __u8 *, uint, __u16);
	161	extern __u8 iop_compare_code(uint, __u8 , uint, __u16);
	162
ed04c97d FT	163	extern void iop_register_interrupts(void);
ed04c97d FT	164
1da177e4	165	#endif /* __ASSEMBLY__ */