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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1da177e4 LT |
2 | #ifndef _ASM_M32R_SMP_H |
3 | #define _ASM_M32R_SMP_H | |
4 | ||
1da177e4 LT |
5 | #ifdef CONFIG_SMP |
6 | #ifndef __ASSEMBLY__ | |
7 | ||
8 | #include <linux/cpumask.h> | |
9 | #include <linux/spinlock.h> | |
10 | #include <linux/threads.h> | |
11 | #include <asm/m32r.h> | |
12 | ||
13 | #define PHYSID_ARRAY_SIZE 1 | |
14 | ||
15 | struct physid_mask | |
16 | { | |
17 | unsigned long mask[PHYSID_ARRAY_SIZE]; | |
18 | }; | |
19 | ||
20 | typedef struct physid_mask physid_mask_t; | |
21 | ||
22 | #define physid_set(physid, map) set_bit(physid, (map).mask) | |
23 | #define physid_clear(physid, map) clear_bit(physid, (map).mask) | |
24 | #define physid_isset(physid, map) test_bit(physid, (map).mask) | |
25 | #define physid_test_and_set(physid, map) test_and_set_bit(physid, (map).mask) | |
26 | ||
27 | #define physids_and(dst, src1, src2) bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS) | |
28 | #define physids_or(dst, src1, src2) bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS) | |
29 | #define physids_clear(map) bitmap_zero((map).mask, MAX_APICS) | |
30 | #define physids_complement(dst, src) bitmap_complement((dst).mask,(src).mask, MAX_APICS) | |
31 | #define physids_empty(map) bitmap_empty((map).mask, MAX_APICS) | |
32 | #define physids_equal(map1, map2) bitmap_equal((map1).mask, (map2).mask, MAX_APICS) | |
33 | #define physids_weight(map) bitmap_weight((map).mask, MAX_APICS) | |
34 | #define physids_shift_right(d, s, n) bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS) | |
35 | #define physids_shift_left(d, s, n) bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS) | |
36 | #define physids_coerce(map) ((map).mask[0]) | |
37 | ||
38 | #define physids_promote(physids) \ | |
39 | ({ \ | |
40 | physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ | |
41 | __physid_mask.mask[0] = physids; \ | |
42 | __physid_mask; \ | |
43 | }) | |
44 | ||
45 | #define physid_mask_of_physid(physid) \ | |
46 | ({ \ | |
47 | physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ | |
48 | physid_set(physid, __physid_mask); \ | |
49 | __physid_mask; \ | |
50 | }) | |
51 | ||
52 | #define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} } | |
53 | #define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} } | |
54 | ||
55 | extern physid_mask_t phys_cpu_present_map; | |
56 | ||
57 | /* | |
58 | * Some lowlevel functions might want to know about | |
59 | * the real CPU ID <-> CPU # mapping. | |
60 | */ | |
1da177e4 | 61 | extern volatile int cpu_2_physid[NR_CPUS]; |
1da177e4 LT |
62 | #define cpu_to_physid(cpu_id) cpu_2_physid[cpu_id] |
63 | ||
39c715b7 | 64 | #define raw_smp_processor_id() (current_thread_info()->cpu) |
1da177e4 LT |
65 | |
66 | extern cpumask_t cpu_callout_map; | |
1da177e4 LT |
67 | |
68 | static __inline__ int hard_smp_processor_id(void) | |
69 | { | |
70 | return (int)*(volatile long *)M32R_CPUID_PORTL; | |
71 | } | |
72 | ||
73 | static __inline__ int cpu_logical_map(int cpu) | |
74 | { | |
75 | return cpu; | |
76 | } | |
77 | ||
78 | static __inline__ int cpu_number_map(int cpu) | |
79 | { | |
80 | return cpu; | |
81 | } | |
82 | ||
1da177e4 | 83 | extern void smp_send_timer(void); |
937e26c0 | 84 | extern unsigned long send_IPI_mask_phys(const cpumask_t*, int, int); |
1da177e4 | 85 | |
7b7426c8 | 86 | extern void arch_send_call_function_single_ipi(int cpu); |
c2a3a488 | 87 | extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); |
7b7426c8 | 88 | |
1da177e4 LT |
89 | #endif /* not __ASSEMBLY__ */ |
90 | ||
91 | #define NO_PROC_ID (0xff) /* No processor magic marker */ | |
92 | ||
1da177e4 LT |
93 | /* |
94 | * M32R-mp IPI | |
95 | */ | |
96 | #define RESCHEDULE_IPI (M32R_IRQ_IPI0-M32R_IRQ_IPI0) | |
97 | #define INVALIDATE_TLB_IPI (M32R_IRQ_IPI1-M32R_IRQ_IPI0) | |
98 | #define CALL_FUNCTION_IPI (M32R_IRQ_IPI2-M32R_IRQ_IPI0) | |
99 | #define LOCAL_TIMER_IPI (M32R_IRQ_IPI3-M32R_IRQ_IPI0) | |
100 | #define INVALIDATE_CACHE_IPI (M32R_IRQ_IPI4-M32R_IRQ_IPI0) | |
101 | #define CPU_BOOT_IPI (M32R_IRQ_IPI5-M32R_IRQ_IPI0) | |
7b7426c8 | 102 | #define CALL_FUNC_SINGLE_IPI (M32R_IRQ_IPI6-M32R_IRQ_IPI0) |
1da177e4 LT |
103 | |
104 | #define IPI_SHIFT (0) | |
105 | #define NR_IPIS (8) | |
106 | ||
2f4dfe20 FLVC |
107 | #else /* CONFIG_SMP */ |
108 | ||
109 | #define hard_smp_processor_id() 0 | |
110 | ||
111 | #endif /* CONFIG_SMP */ | |
1da177e4 LT |
112 | |
113 | #endif /* _ASM_M32R_SMP_H */ |