[linux-2.6-block.git] / arch / ia64 / kernel / irq_ia64.c

/*
 * linux/arch/ia64/kernel/irq_ia64.c
 *
 * Copyright (C) 1998-2001 Hewlett-Packard Co
 *	Stephane Eranian <eranian@hpl.hp.com>
 *	David Mosberger-Tang <davidm@hpl.hp.com>
 *
 *  6/10/99: Updated to bring in sync with x86 version to facilitate
 *	     support for SMP and different interrupt controllers.
 *
 * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
 *                      PCI to vector allocation routine.
 * 04/14/2004 Ashok Raj <ashok.raj@intel.com>
 *						Added CPU Hotplug handling for IPF.
 */

#include <linux/module.h>

#include <linux/jiffies.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/kernel_stat.h>
#include <linux/slab.h>
#include <linux/ptrace.h>
#include <linux/random.h>	/* for rand_initialize_irq() */
#include <linux/signal.h>
#include <linux/smp.h>
#include <linux/threads.h>
#include <linux/bitops.h>
#include <linux/irq.h>

#include <asm/delay.h>
#include <asm/intrinsics.h>
#include <asm/io.h>
#include <asm/hw_irq.h>
#include <asm/machvec.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/tlbflush.h>

#ifdef CONFIG_PERFMON
# include <asm/perfmon.h>
#endif

#define IRQ_DEBUG	0

#define IRQ_VECTOR_UNASSIGNED	(0)

#define IRQ_UNUSED		(0)
#define IRQ_USED		(1)
#define IRQ_RSVD		(2)

/* These can be overridden in platform_irq_init */
int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;

/* default base addr of IPI table */
void __iomem *ipi_base_addr = ((void __iomem *)
			       (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR));

static cpumask_t vector_allocation_domain(int cpu);

/*
 * Legacy IRQ to IA-64 vector translation table.
 */
__u8 isa_irq_to_vector_map[16] = {
	/* 8259 IRQ translation, first 16 entries */
	0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
	0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
};
EXPORT_SYMBOL(isa_irq_to_vector_map);

DEFINE_SPINLOCK(vector_lock);

struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
	[0 ... NR_IRQS - 1] = {
		.vector = IRQ_VECTOR_UNASSIGNED,
		.domain = CPU_MASK_NONE
	}
};

DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
	[0 ... IA64_NUM_VECTORS - 1] = IA64_SPURIOUS_INT_VECTOR
};

static cpumask_t vector_table[IA64_NUM_VECTORS] = {
	[0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
};

static int irq_status[NR_IRQS] = {
	[0 ... NR_IRQS -1] = IRQ_UNUSED
};

int check_irq_used(int irq)
{
	if (irq_status[irq] == IRQ_USED)
		return 1;

	return -1;
}

static void reserve_irq(unsigned int irq)
{
	unsigned long flags;

	spin_lock_irqsave(&vector_lock, flags);
	irq_status[irq] = IRQ_RSVD;
	spin_unlock_irqrestore(&vector_lock, flags);
}

static inline int find_unassigned_irq(void)
{
	int irq;

	for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
		if (irq_status[irq] == IRQ_UNUSED)
			return irq;
	return -ENOSPC;
}

static inline int find_unassigned_vector(cpumask_t domain)
{
	cpumask_t mask;
	int pos, vector;

	cpus_and(mask, domain, cpu_online_map);
	if (cpus_empty(mask))
		return -EINVAL;

	for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
		vector = IA64_FIRST_DEVICE_VECTOR + pos;
		cpus_and(mask, domain, vector_table[vector]);
		if (!cpus_empty(mask))
			continue;
		return vector;
	}
	return -ENOSPC;
}

static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
{
	cpumask_t mask;
	int cpu;
	struct irq_cfg *cfg = &irq_cfg[irq];

	BUG_ON((unsigned)irq >= NR_IRQS);
	BUG_ON((unsigned)vector >= IA64_NUM_VECTORS);

	cpus_and(mask, domain, cpu_online_map);
	if (cpus_empty(mask))
		return -EINVAL;
	if ((cfg->vector == vector) && cpus_equal(cfg->domain, domain))
		return 0;
	if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
		return -EBUSY;
	for_each_cpu_mask(cpu, mask)
		per_cpu(vector_irq, cpu)[vector] = irq;
	cfg->vector = vector;
	cfg->domain = domain;
	irq_status[irq] = IRQ_USED;
	cpus_or(vector_table[vector], vector_table[vector], domain);
	return 0;
}

int bind_irq_vector(int irq, int vector, cpumask_t domain)
{
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&vector_lock, flags);
	ret = __bind_irq_vector(irq, vector, domain);
	spin_unlock_irqrestore(&vector_lock, flags);
	return ret;
}

static void __clear_irq_vector(int irq)
{
	int vector, cpu;
	cpumask_t mask;
	cpumask_t domain;
	struct irq_cfg *cfg = &irq_cfg[irq];

	BUG_ON((unsigned)irq >= NR_IRQS);
	BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
	vector = cfg->vector;
	domain = cfg->domain;
	cpus_and(mask, cfg->domain, cpu_online_map);
	for_each_cpu_mask(cpu, mask)
		per_cpu(vector_irq, cpu)[vector] = IA64_SPURIOUS_INT_VECTOR;
	cfg->vector = IRQ_VECTOR_UNASSIGNED;
	cfg->domain = CPU_MASK_NONE;
	irq_status[irq] = IRQ_UNUSED;
	cpus_andnot(vector_table[vector], vector_table[vector], domain);
}

static void clear_irq_vector(int irq)
{
	unsigned long flags;

	spin_lock_irqsave(&vector_lock, flags);
	__clear_irq_vector(irq);
	spin_unlock_irqrestore(&vector_lock, flags);
}

int
assign_irq_vector (int irq)
{
	unsigned long flags;
	int vector, cpu;
	cpumask_t domain;

	vector = -ENOSPC;

	spin_lock_irqsave(&vector_lock, flags);
	for_each_online_cpu(cpu) {
		domain = vector_allocation_domain(cpu);
		vector = find_unassigned_vector(domain);
		if (vector >= 0)
			break;
	}
	if (vector < 0)
		goto out;
	if (irq == AUTO_ASSIGN)
		irq = vector;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
 out:
	spin_unlock_irqrestore(&vector_lock, flags);
	return vector;
}

void
free_irq_vector (int vector)
{
	if (vector < IA64_FIRST_DEVICE_VECTOR ||
	    vector > IA64_LAST_DEVICE_VECTOR)
		return;
	clear_irq_vector(vector);
}

int
reserve_irq_vector (int vector)
{
	if (vector < IA64_FIRST_DEVICE_VECTOR ||
	    vector > IA64_LAST_DEVICE_VECTOR)
		return -EINVAL;
	return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
}

/*
 * Initialize vector_irq on a new cpu. This function must be called
 * with vector_lock held.
 */
void __setup_vector_irq(int cpu)
{
	int irq, vector;

	/* Clear vector_irq */
	for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
		per_cpu(vector_irq, cpu)[vector] = IA64_SPURIOUS_INT_VECTOR;
	/* Mark the inuse vectors */
	for (irq = 0; irq < NR_IRQS; ++irq) {
		if (!cpu_isset(cpu, irq_cfg[irq].domain))
			continue;
		vector = irq_to_vector(irq);
		per_cpu(vector_irq, cpu)[vector] = irq;
	}
}

#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG))
static enum vector_domain_type {
	VECTOR_DOMAIN_NONE,
	VECTOR_DOMAIN_PERCPU
} vector_domain_type = VECTOR_DOMAIN_NONE;

static cpumask_t vector_allocation_domain(int cpu)
{
	if (vector_domain_type == VECTOR_DOMAIN_PERCPU)
		return cpumask_of_cpu(cpu);
	return CPU_MASK_ALL;
}

static int __init parse_vector_domain(char *arg)
{
	if (!arg)
		return -EINVAL;
	if (!strcmp(arg, "percpu")) {
		vector_domain_type = VECTOR_DOMAIN_PERCPU;
		no_int_routing = 1;
	}
	return 0;
}
early_param("vector", parse_vector_domain);
#else
static cpumask_t vector_allocation_domain(int cpu)
{
	return CPU_MASK_ALL;
}
#endif


void destroy_and_reserve_irq(unsigned int irq)
{
	dynamic_irq_cleanup(irq);

	clear_irq_vector(irq);
	reserve_irq(irq);
}

static int __reassign_irq_vector(int irq, int cpu)
{
	struct irq_cfg *cfg = &irq_cfg[irq];
	int vector;
	cpumask_t domain;

	if (cfg->vector == IRQ_VECTOR_UNASSIGNED || !cpu_online(cpu))
		return -EINVAL;
	if (cpu_isset(cpu, cfg->domain))
		return 0;
	domain = vector_allocation_domain(cpu);
	vector = find_unassigned_vector(domain);
	if (vector < 0)
		return -ENOSPC;
	__clear_irq_vector(irq);
	BUG_ON(__bind_irq_vector(irq, vector, domain));
	return 0;
}

int reassign_irq_vector(int irq, int cpu)
{
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&vector_lock, flags);
	ret = __reassign_irq_vector(irq, cpu);
	spin_unlock_irqrestore(&vector_lock, flags);
	return ret;
}

/*
 * Dynamic irq allocate and deallocation for MSI
 */
int create_irq(void)
{
	unsigned long flags;
	int irq, vector, cpu;
	cpumask_t domain;

	irq = vector = -ENOSPC;
	spin_lock_irqsave(&vector_lock, flags);
	for_each_online_cpu(cpu) {
		domain = vector_allocation_domain(cpu);
		vector = find_unassigned_vector(domain);
		if (vector >= 0)
			break;
	}
	if (vector < 0)
		goto out;
	irq = find_unassigned_irq();
	if (irq < 0)
		goto out;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
 out:
	spin_unlock_irqrestore(&vector_lock, flags);
	if (irq >= 0)
		dynamic_irq_init(irq);
	return irq;
}

void destroy_irq(unsigned int irq)
{
	dynamic_irq_cleanup(irq);
	clear_irq_vector(irq);
}

#ifdef CONFIG_SMP
#	define IS_RESCHEDULE(vec)	(vec == IA64_IPI_RESCHEDULE)
#	define IS_LOCAL_TLB_FLUSH(vec)	(vec == IA64_IPI_LOCAL_TLB_FLUSH)
#else
#	define IS_RESCHEDULE(vec)	(0)
#	define IS_LOCAL_TLB_FLUSH(vec)	(0)
#endif
/*
 * That's where the IVT branches when we get an external
 * interrupt. This branches to the correct hardware IRQ handler via
 * function ptr.
 */
void
ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
{
	struct pt_regs *old_regs = set_irq_regs(regs);
	unsigned long saved_tpr;

#if IRQ_DEBUG
	{
		unsigned long bsp, sp;

		/*
		 * Note: if the interrupt happened while executing in
		 * the context switch routine (ia64_switch_to), we may
		 * get a spurious stack overflow here.  This is
		 * because the register and the memory stack are not
		 * switched atomically.
		 */
		bsp = ia64_getreg(_IA64_REG_AR_BSP);
		sp = ia64_getreg(_IA64_REG_SP);

		if ((sp - bsp) < 1024) {
			static unsigned char count;
			static long last_time;

			if (jiffies - last_time > 5*HZ)
				count = 0;
			if (++count < 5) {
				last_time = jiffies;
				printk("ia64_handle_irq: DANGER: less than "
				       "1KB of free stack space!!\n"
				       "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
			}
		}
	}
#endif /* IRQ_DEBUG */

	/*
	 * Always set TPR to limit maximum interrupt nesting depth to
	 * 16 (without this, it would be ~240, which could easily lead
	 * to kernel stack overflows).
	 */
	irq_enter();
	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	ia64_srlz_d();
	while (vector != IA64_SPURIOUS_INT_VECTOR) {
		if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
			smp_local_flush_tlb();
			kstat_this_cpu.irqs[vector]++;
		} else if (unlikely(IS_RESCHEDULE(vector)))
			kstat_this_cpu.irqs[vector]++;
		else {
			ia64_setreg(_IA64_REG_CR_TPR, vector);
			ia64_srlz_d();

			generic_handle_irq(local_vector_to_irq(vector));

			/*
			 * Disable interrupts and send EOI:
			 */
			local_irq_disable();
			ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
		}
		ia64_eoi();
		vector = ia64_get_ivr();
	}
	/*
	 * This must be done *after* the ia64_eoi().  For example, the keyboard softirq
	 * handler needs to be able to wait for further keyboard interrupts, which can't
	 * come through until ia64_eoi() has been done.
	 */
	irq_exit();
	set_irq_regs(old_regs);
}

#ifdef CONFIG_HOTPLUG_CPU
/*
 * This function emulates a interrupt processing when a cpu is about to be
 * brought down.
 */
void ia64_process_pending_intr(void)
{
	ia64_vector vector;
	unsigned long saved_tpr;
	extern unsigned int vectors_in_migration[NR_IRQS];

	vector = ia64_get_ivr();

	 irq_enter();
	 saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	 ia64_srlz_d();

	 /*
	  * Perform normal interrupt style processing
	  */
	while (vector != IA64_SPURIOUS_INT_VECTOR) {
		if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
			smp_local_flush_tlb();
			kstat_this_cpu.irqs[vector]++;
		} else if (unlikely(IS_RESCHEDULE(vector)))
			kstat_this_cpu.irqs[vector]++;
		else {
			struct pt_regs *old_regs = set_irq_regs(NULL);

			ia64_setreg(_IA64_REG_CR_TPR, vector);
			ia64_srlz_d();

			/*
			 * Now try calling normal ia64_handle_irq as it would have got called
			 * from a real intr handler. Try passing null for pt_regs, hopefully
			 * it will work. I hope it works!.
			 * Probably could shared code.
			 */
			vectors_in_migration[local_vector_to_irq(vector)]=0;
			generic_handle_irq(local_vector_to_irq(vector));
			set_irq_regs(old_regs);

			/*
			 * Disable interrupts and send EOI
			 */
			local_irq_disable();
			ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
		}
		ia64_eoi();
		vector = ia64_get_ivr();
	}
	irq_exit();
}
#endif


#ifdef CONFIG_SMP

static irqreturn_t dummy_handler (int irq, void *dev_id)
{
	BUG();
}
extern irqreturn_t handle_IPI (int irq, void *dev_id);

static struct irqaction ipi_irqaction = {
	.handler =	handle_IPI,
	.flags =	IRQF_DISABLED,
	.name =		"IPI"
};

static struct irqaction resched_irqaction = {
	.handler =	dummy_handler,
	.flags =	IRQF_DISABLED,
	.name =		"resched"
};

static struct irqaction tlb_irqaction = {
	.handler =	dummy_handler,
	.flags =	IRQF_DISABLED,
	.name =		"tlb_flush"
};

#endif

void
register_percpu_irq (ia64_vector vec, struct irqaction *action)
{
	irq_desc_t *desc;
	unsigned int irq;

	irq = vec;
	BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
	desc = irq_desc + irq;
	desc->status |= IRQ_PER_CPU;
	desc->chip = &irq_type_ia64_lsapic;
	if (action)
		setup_irq(irq, action);
}

void __init
init_IRQ (void)
{
	register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
#ifdef CONFIG_SMP
	register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
	register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
	register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
#endif
#ifdef CONFIG_PERFMON
	pfm_init_percpu();
#endif
	platform_irq_init();
}

void
ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
{
	void __iomem *ipi_addr;
	unsigned long ipi_data;
	unsigned long phys_cpu_id;

#ifdef CONFIG_SMP
	phys_cpu_id = cpu_physical_id(cpu);
#else
	phys_cpu_id = (ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff;
#endif

	/*
	 * cpu number is in 8bit ID and 8bit EID
	 */

	ipi_data = (delivery_mode << 8) | (vector & 0xff);
	ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) | ((redirect & 1) << 3));

	writeq(ipi_data, ipi_addr);
}
Commit	Line	Data
1da177e4	1	/*
f30c2269	2	* linux/arch/ia64/kernel/irq_ia64.c
1da177e4 LT	3	*
	4	* Copyright (C) 1998-2001 Hewlett-Packard Co
	5	* Stephane Eranian <eranian@hpl.hp.com>
	6	* David Mosberger-Tang <davidm@hpl.hp.com>
	7	*
	8	* 6/10/99: Updated to bring in sync with x86 version to facilitate
	9	* support for SMP and different interrupt controllers.
	10	*
	11	* 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
	12	* PCI to vector allocation routine.
	13	* 04/14/2004 Ashok Raj <ashok.raj@intel.com>
	14	* Added CPU Hotplug handling for IPF.
	15	*/
	16
1da177e4 LT	17	#include <linux/module.h>
	18
	19	#include <linux/jiffies.h>
	20	#include <linux/errno.h>
	21	#include <linux/init.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/ioport.h>
	24	#include <linux/kernel_stat.h>
	25	#include <linux/slab.h>
	26	#include <linux/ptrace.h>
	27	#include <linux/random.h> /* for rand_initialize_irq() */
	28	#include <linux/signal.h>
	29	#include <linux/smp.h>
1da177e4 LT	30	#include <linux/threads.h>
1da177e4 LT	31	#include <linux/bitops.h>
b6cf2583	32	#include <linux/irq.h>
1da177e4 LT	33
	34	#include <asm/delay.h>
	35	#include <asm/intrinsics.h>
	36	#include <asm/io.h>
	37	#include <asm/hw_irq.h>
	38	#include <asm/machvec.h>
	39	#include <asm/pgtable.h>
	40	#include <asm/system.h>
3be44b9c	41	#include <asm/tlbflush.h>
1da177e4 LT	42
	43	#ifdef CONFIG_PERFMON
	44	# include <asm/perfmon.h>
	45	#endif
	46
	47	#define IRQ_DEBUG 0
	48
e1b30a39 YI	49	#define IRQ_VECTOR_UNASSIGNED (0)
	50
	51	#define IRQ_UNUSED (0)
	52	#define IRQ_USED (1)
	53	#define IRQ_RSVD (2)
	54
10083072 MM	55	/* These can be overridden in platform_irq_init */
	56	int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
	57	int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;
	58
1da177e4 LT	59	/* default base addr of IPI table */
	60	void __iomem ipi_base_addr = ((void __iomem )
	61	(__IA64_UNCACHED_OFFSET \| IA64_IPI_DEFAULT_BASE_ADDR));
	62
4994be1b YI	63	static cpumask_t vector_allocation_domain(int cpu);
4994be1b YI	64
1da177e4 LT	65	/*
	66	* Legacy IRQ to IA-64 vector translation table.
	67	*/
	68	__u8 isa_irq_to_vector_map[16] = {
	69	/* 8259 IRQ translation, first 16 entries */
	70	0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
	71	0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
	72	};
	73	EXPORT_SYMBOL(isa_irq_to_vector_map);
	74
e1b30a39 YI	75	DEFINE_SPINLOCK(vector_lock);
	76
	77	struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
4994be1b YI	78	[0 ... NR_IRQS - 1] = {
	79	.vector = IRQ_VECTOR_UNASSIGNED,
	80	.domain = CPU_MASK_NONE
	81	}
e1b30a39 YI	82	};
	83
	84	DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
	85	[0 ... IA64_NUM_VECTORS - 1] = IA64_SPURIOUS_INT_VECTOR
	86	};
	87
6ffbc823 KK	88	static cpumask_t vector_table[IA64_NUM_VECTORS] = {
6ffbc823 KK	89	[0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
4994be1b YI	90	};
4994be1b YI	91
e1b30a39 YI	92	static int irq_status[NR_IRQS] = {
	93	[0 ... NR_IRQS -1] = IRQ_UNUSED
	94	};
	95
	96	int check_irq_used(int irq)
	97	{
	98	if (irq_status[irq] == IRQ_USED)
	99	return 1;
	100
	101	return -1;
	102	}
	103
	104	static void reserve_irq(unsigned int irq)
	105	{
	106	unsigned long flags;
	107
	108	spin_lock_irqsave(&vector_lock, flags);
	109	irq_status[irq] = IRQ_RSVD;
	110	spin_unlock_irqrestore(&vector_lock, flags);
	111	}
	112
	113	static inline int find_unassigned_irq(void)
	114	{
	115	int irq;
	116
	117	for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
	118	if (irq_status[irq] == IRQ_UNUSED)
	119	return irq;
	120	return -ENOSPC;
	121	}
	122
4994be1b	123	static inline int find_unassigned_vector(cpumask_t domain)
e1b30a39	124	{
4994be1b	125	cpumask_t mask;
6ffbc823	126	int pos, vector;
4994be1b YI	127
	128	cpus_and(mask, domain, cpu_online_map);
	129	if (cpus_empty(mask))
	130	return -EINVAL;
e1b30a39	131
4994be1b	132	for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
6ffbc823 KK	133	vector = IA64_FIRST_DEVICE_VECTOR + pos;
6ffbc823 KK	134	cpus_and(mask, domain, vector_table[vector]);
4994be1b YI	135	if (!cpus_empty(mask))
4994be1b YI	136	continue;
6ffbc823	137	return vector;
4994be1b	138	}
e1b30a39 YI	139	return -ENOSPC;
	140	}
	141
4994be1b	142	static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
e1b30a39	143	{
4994be1b	144	cpumask_t mask;
6ffbc823	145	int cpu;
4994be1b	146	struct irq_cfg *cfg = &irq_cfg[irq];
e1b30a39	147
6bde71ec KK	148	BUG_ON((unsigned)irq >= NR_IRQS);
	149	BUG_ON((unsigned)vector >= IA64_NUM_VECTORS);
	150
4994be1b YI	151	cpus_and(mask, domain, cpu_online_map);
	152	if (cpus_empty(mask))
	153	return -EINVAL;
	154	if ((cfg->vector == vector) && cpus_equal(cfg->domain, domain))
e1b30a39	155	return 0;
4994be1b	156	if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
e1b30a39	157	return -EBUSY;
4994be1b	158	for_each_cpu_mask(cpu, mask)
e1b30a39	159	per_cpu(vector_irq, cpu)[vector] = irq;
4994be1b YI	160	cfg->vector = vector;
4994be1b YI	161	cfg->domain = domain;
e1b30a39	162	irq_status[irq] = IRQ_USED;
6ffbc823	163	cpus_or(vector_table[vector], vector_table[vector], domain);
e1b30a39 YI	164	return 0;
	165	}
	166
4994be1b	167	int bind_irq_vector(int irq, int vector, cpumask_t domain)
e1b30a39 YI	168	{
	169	unsigned long flags;
	170	int ret;
	171
	172	spin_lock_irqsave(&vector_lock, flags);
4994be1b	173	ret = __bind_irq_vector(irq, vector, domain);
e1b30a39 YI	174	spin_unlock_irqrestore(&vector_lock, flags);
	175	return ret;
	176	}
	177
cd378f18	178	static void __clear_irq_vector(int irq)
e1b30a39	179	{
6ffbc823	180	int vector, cpu;
4994be1b YI	181	cpumask_t mask;
	182	cpumask_t domain;
	183	struct irq_cfg *cfg = &irq_cfg[irq];
e1b30a39	184
e1b30a39	185	BUG_ON((unsigned)irq >= NR_IRQS);
4994be1b YI	186	BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
	187	vector = cfg->vector;
	188	domain = cfg->domain;
	189	cpus_and(mask, cfg->domain, cpu_online_map);
	190	for_each_cpu_mask(cpu, mask)
e1b30a39	191	per_cpu(vector_irq, cpu)[vector] = IA64_SPURIOUS_INT_VECTOR;
4994be1b YI	192	cfg->vector = IRQ_VECTOR_UNASSIGNED;
4994be1b YI	193	cfg->domain = CPU_MASK_NONE;
e1b30a39	194	irq_status[irq] = IRQ_UNUSED;
6ffbc823	195	cpus_andnot(vector_table[vector], vector_table[vector], domain);
cd378f18 YI	196	}
	197
	198	static void clear_irq_vector(int irq)
	199	{
	200	unsigned long flags;
	201
	202	spin_lock_irqsave(&vector_lock, flags);
	203	__clear_irq_vector(irq);
e1b30a39 YI	204	spin_unlock_irqrestore(&vector_lock, flags);
e1b30a39 YI	205	}
1da177e4 LT	206
1da177e4 LT	207	int
3b5cc090	208	assign_irq_vector (int irq)
1da177e4	209	{
e1b30a39	210	unsigned long flags;
4994be1b YI	211	int vector, cpu;
	212	cpumask_t domain;
	213
	214	vector = -ENOSPC;
e1b30a39	215
4994be1b	216	spin_lock_irqsave(&vector_lock, flags);
4994be1b YI	217	for_each_online_cpu(cpu) {
	218	domain = vector_allocation_domain(cpu);
	219	vector = find_unassigned_vector(domain);
	220	if (vector >= 0)
	221	break;
	222	}
e1b30a39 YI	223	if (vector < 0)
e1b30a39 YI	224	goto out;
8f5ad1a8 YI	225	if (irq == AUTO_ASSIGN)
8f5ad1a8 YI	226	irq = vector;
4994be1b	227	BUG_ON(__bind_irq_vector(irq, vector, domain));
e1b30a39	228	out:
4994be1b	229	spin_unlock_irqrestore(&vector_lock, flags);
1da177e4 LT	230	return vector;
	231	}
	232
	233	void
	234	free_irq_vector (int vector)
	235	{
e1b30a39 YI	236	if (vector < IA64_FIRST_DEVICE_VECTOR \|\|
e1b30a39 YI	237	vector > IA64_LAST_DEVICE_VECTOR)
1da177e4	238	return;
e1b30a39	239	clear_irq_vector(vector);
1da177e4 LT	240	}
1da177e4 LT	241
10083072 MM	242	int
	243	reserve_irq_vector (int vector)
	244	{
10083072 MM	245	if (vector < IA64_FIRST_DEVICE_VECTOR \|\|
	246	vector > IA64_LAST_DEVICE_VECTOR)
	247	return -EINVAL;
4994be1b	248	return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
e1b30a39	249	}
10083072	250
e1b30a39 YI	251	/*
	252	* Initialize vector_irq on a new cpu. This function must be called
	253	* with vector_lock held.
	254	*/
	255	void __setup_vector_irq(int cpu)
	256	{
	257	int irq, vector;
	258
	259	/* Clear vector_irq */
	260	for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
	261	per_cpu(vector_irq, cpu)[vector] = IA64_SPURIOUS_INT_VECTOR;
	262	/* Mark the inuse vectors */
	263	for (irq = 0; irq < NR_IRQS; ++irq) {
4994be1b YI	264	if (!cpu_isset(cpu, irq_cfg[irq].domain))
	265	continue;
	266	vector = irq_to_vector(irq);
	267	per_cpu(vector_irq, cpu)[vector] = irq;
e1b30a39 YI	268	}
	269	}
	270
e5bd762b	271	#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) \|\| defined(CONFIG_IA64_DIG))
d080d397 YI	272	static enum vector_domain_type {
	273	VECTOR_DOMAIN_NONE,
	274	VECTOR_DOMAIN_PERCPU
	275	} vector_domain_type = VECTOR_DOMAIN_NONE;
	276
4994be1b YI	277	static cpumask_t vector_allocation_domain(int cpu)
4994be1b YI	278	{
d080d397 YI	279	if (vector_domain_type == VECTOR_DOMAIN_PERCPU)
d080d397 YI	280	return cpumask_of_cpu(cpu);
4994be1b YI	281	return CPU_MASK_ALL;
	282	}
	283
d080d397 YI	284	static int __init parse_vector_domain(char *arg)
	285	{
	286	if (!arg)
	287	return -EINVAL;
	288	if (!strcmp(arg, "percpu")) {
	289	vector_domain_type = VECTOR_DOMAIN_PERCPU;
	290	no_int_routing = 1;
	291	}
074ff856	292	return 0;
d080d397 YI	293	}
	294	early_param("vector", parse_vector_domain);
	295	#else
	296	static cpumask_t vector_allocation_domain(int cpu)
	297	{
	298	return CPU_MASK_ALL;
	299	}
	300	#endif
	301
4994be1b	302
e1b30a39 YI	303	void destroy_and_reserve_irq(unsigned int irq)
	304	{
	305	dynamic_irq_cleanup(irq);
	306
	307	clear_irq_vector(irq);
	308	reserve_irq(irq);
10083072 MM	309	}
10083072 MM	310
cd378f18 YI	311	static int __reassign_irq_vector(int irq, int cpu)
	312	{
	313	struct irq_cfg *cfg = &irq_cfg[irq];
	314	int vector;
	315	cpumask_t domain;
	316
	317	if (cfg->vector == IRQ_VECTOR_UNASSIGNED \|\| !cpu_online(cpu))
	318	return -EINVAL;
	319	if (cpu_isset(cpu, cfg->domain))
	320	return 0;
	321	domain = vector_allocation_domain(cpu);
	322	vector = find_unassigned_vector(domain);
	323	if (vector < 0)
	324	return -ENOSPC;
	325	__clear_irq_vector(irq);
	326	BUG_ON(__bind_irq_vector(irq, vector, domain));
	327	return 0;
	328	}
	329
	330	int reassign_irq_vector(int irq, int cpu)
	331	{
	332	unsigned long flags;
	333	int ret;
	334
	335	spin_lock_irqsave(&vector_lock, flags);
	336	ret = __reassign_irq_vector(irq, cpu);
	337	spin_unlock_irqrestore(&vector_lock, flags);
	338	return ret;
	339	}
	340
b6cf2583 EB	341	/*
	342	* Dynamic irq allocate and deallocation for MSI
	343	*/
	344	int create_irq(void)
	345	{
e1b30a39	346	unsigned long flags;
4994be1b YI	347	int irq, vector, cpu;
4994be1b YI	348	cpumask_t domain;
e1b30a39	349
4994be1b	350	irq = vector = -ENOSPC;
e1b30a39	351	spin_lock_irqsave(&vector_lock, flags);
4994be1b YI	352	for_each_online_cpu(cpu) {
	353	domain = vector_allocation_domain(cpu);
	354	vector = find_unassigned_vector(domain);
	355	if (vector >= 0)
	356	break;
	357	}
e1b30a39 YI	358	if (vector < 0)
	359	goto out;
	360	irq = find_unassigned_irq();
	361	if (irq < 0)
	362	goto out;
4994be1b	363	BUG_ON(__bind_irq_vector(irq, vector, domain));
e1b30a39 YI	364	out:
	365	spin_unlock_irqrestore(&vector_lock, flags);
	366	if (irq >= 0)
	367	dynamic_irq_init(irq);
	368	return irq;
b6cf2583 EB	369	}
	370
	371	void destroy_irq(unsigned int irq)
	372	{
	373	dynamic_irq_cleanup(irq);
e1b30a39	374	clear_irq_vector(irq);
b6cf2583 EB	375	}
b6cf2583 EB	376
1da177e4 LT	377	#ifdef CONFIG_SMP
1da177e4 LT	378	# define IS_RESCHEDULE(vec) (vec == IA64_IPI_RESCHEDULE)
3be44b9c	379	# define IS_LOCAL_TLB_FLUSH(vec) (vec == IA64_IPI_LOCAL_TLB_FLUSH)
1da177e4 LT	380	#else
1da177e4 LT	381	# define IS_RESCHEDULE(vec) (0)
3be44b9c	382	# define IS_LOCAL_TLB_FLUSH(vec) (0)
1da177e4 LT	383	#endif
	384	/*
	385	* That's where the IVT branches when we get an external
	386	* interrupt. This branches to the correct hardware IRQ handler via
	387	* function ptr.
	388	*/
	389	void
	390	ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
	391	{
7d12e780	392	struct pt_regs *old_regs = set_irq_regs(regs);
1da177e4 LT	393	unsigned long saved_tpr;
	394
	395	#if IRQ_DEBUG
	396	{
	397	unsigned long bsp, sp;
	398
	399	/*
	400	* Note: if the interrupt happened while executing in
	401	* the context switch routine (ia64_switch_to), we may
	402	* get a spurious stack overflow here. This is
	403	* because the register and the memory stack are not
	404	* switched atomically.
	405	*/
	406	bsp = ia64_getreg(_IA64_REG_AR_BSP);
	407	sp = ia64_getreg(_IA64_REG_SP);
	408
	409	if ((sp - bsp) < 1024) {
	410	static unsigned char count;
	411	static long last_time;
	412
	413	if (jiffies - last_time > 5*HZ)
	414	count = 0;
	415	if (++count < 5) {
	416	last_time = jiffies;
	417	printk("ia64_handle_irq: DANGER: less than "
	418	"1KB of free stack space!!\n"
	419	"(bsp=0x%lx, sp=%lx)\n", bsp, sp);
	420	}
	421	}
	422	}
	423	#endif /* IRQ_DEBUG */
	424
	425	/*
	426	* Always set TPR to limit maximum interrupt nesting depth to
	427	* 16 (without this, it would be ~240, which could easily lead
	428	* to kernel stack overflows).
	429	*/
	430	irq_enter();
	431	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	432	ia64_srlz_d();
	433	while (vector != IA64_SPURIOUS_INT_VECTOR) {
3be44b9c JS	434	if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
	435	smp_local_flush_tlb();
	436	kstat_this_cpu.irqs[vector]++;
	437	} else if (unlikely(IS_RESCHEDULE(vector)))
	438	kstat_this_cpu.irqs[vector]++;
9b3377f9	439	else {
1da177e4 LT	440	ia64_setreg(_IA64_REG_CR_TPR, vector);
	441	ia64_srlz_d();
	442
5fbb004a	443	generic_handle_irq(local_vector_to_irq(vector));
1da177e4 LT	444
	445	/*
	446	* Disable interrupts and send EOI:
	447	*/
	448	local_irq_disable();
	449	ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
	450	}
	451	ia64_eoi();
	452	vector = ia64_get_ivr();
	453	}
	454	/*
	455	* This must be done after the ia64_eoi(). For example, the keyboard softirq
	456	* handler needs to be able to wait for further keyboard interrupts, which can't
	457	* come through until ia64_eoi() has been done.
	458	*/
	459	irq_exit();
7d12e780	460	set_irq_regs(old_regs);
1da177e4 LT	461	}
	462
	463	#ifdef CONFIG_HOTPLUG_CPU
	464	/*
	465	* This function emulates a interrupt processing when a cpu is about to be
	466	* brought down.
	467	*/
	468	void ia64_process_pending_intr(void)
	469	{
	470	ia64_vector vector;
	471	unsigned long saved_tpr;
	472	extern unsigned int vectors_in_migration[NR_IRQS];
	473
	474	vector = ia64_get_ivr();
	475
	476	irq_enter();
	477	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	478	ia64_srlz_d();
	479
	480	/*
	481	* Perform normal interrupt style processing
	482	*/
	483	while (vector != IA64_SPURIOUS_INT_VECTOR) {
3be44b9c JS	484	if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
	485	smp_local_flush_tlb();
	486	kstat_this_cpu.irqs[vector]++;
	487	} else if (unlikely(IS_RESCHEDULE(vector)))
	488	kstat_this_cpu.irqs[vector]++;
9b3377f9	489	else {
8c1addbc TL	490	struct pt_regs *old_regs = set_irq_regs(NULL);
8c1addbc TL	491
1da177e4 LT	492	ia64_setreg(_IA64_REG_CR_TPR, vector);
	493	ia64_srlz_d();
	494
	495	/*
	496	* Now try calling normal ia64_handle_irq as it would have got called
	497	* from a real intr handler. Try passing null for pt_regs, hopefully
	498	* it will work. I hope it works!.
	499	* Probably could shared code.
	500	*/
	501	vectors_in_migration[local_vector_to_irq(vector)]=0;
5fbb004a	502	generic_handle_irq(local_vector_to_irq(vector));
8c1addbc	503	set_irq_regs(old_regs);
1da177e4 LT	504
	505	/*
	506	* Disable interrupts and send EOI
	507	*/
	508	local_irq_disable();
	509	ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
	510	}
	511	ia64_eoi();
	512	vector = ia64_get_ivr();
	513	}
	514	irq_exit();
	515	}
	516	#endif
	517
	518
	519	#ifdef CONFIG_SMP
1da177e4	520
9b3377f9 JS	521	static irqreturn_t dummy_handler (int irq, void *dev_id)
	522	{
	523	BUG();
	524	}
3be44b9c	525	extern irqreturn_t handle_IPI (int irq, void *dev_id);
9b3377f9	526
1da177e4 LT	527	static struct irqaction ipi_irqaction = {
1da177e4 LT	528	.handler = handle_IPI,
121a4226	529	.flags = IRQF_DISABLED,
1da177e4 LT	530	.name = "IPI"
1da177e4 LT	531	};
9b3377f9 JS	532
	533	static struct irqaction resched_irqaction = {
	534	.handler = dummy_handler,
38515e90	535	.flags = IRQF_DISABLED,
9b3377f9 JS	536	.name = "resched"
9b3377f9 JS	537	};
3be44b9c JS	538
	539	static struct irqaction tlb_irqaction = {
	540	.handler = dummy_handler,
5329571b	541	.flags = IRQF_DISABLED,
3be44b9c JS	542	.name = "tlb_flush"
	543	};
	544
1da177e4 LT	545	#endif
	546
	547	void
	548	register_percpu_irq (ia64_vector vec, struct irqaction *action)
	549	{
	550	irq_desc_t *desc;
	551	unsigned int irq;
	552
e1b30a39	553	irq = vec;
4994be1b	554	BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
e1b30a39 YI	555	desc = irq_desc + irq;
	556	desc->status \|= IRQ_PER_CPU;
	557	desc->chip = &irq_type_ia64_lsapic;
	558	if (action)
	559	setup_irq(irq, action);
1da177e4 LT	560	}
	561
	562	void __init
	563	init_IRQ (void)
	564	{
	565	register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
	566	#ifdef CONFIG_SMP
	567	register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
9b3377f9	568	register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
3be44b9c	569	register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
1da177e4 LT	570	#endif
	571	#ifdef CONFIG_PERFMON
	572	pfm_init_percpu();
	573	#endif
	574	platform_irq_init();
	575	}
	576
	577	void
	578	ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
	579	{
	580	void __iomem *ipi_addr;
	581	unsigned long ipi_data;
	582	unsigned long phys_cpu_id;
	583
	584	#ifdef CONFIG_SMP
	585	phys_cpu_id = cpu_physical_id(cpu);
	586	#else
	587	phys_cpu_id = (ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff;
	588	#endif
	589
	590	/*
	591	* cpu number is in 8bit ID and 8bit EID
	592	*/
	593
	594	ipi_data = (delivery_mode << 8) \| (vector & 0xff);
	595	ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) \| ((redirect & 1) << 3));
	596
	597	writeq(ipi_data, ipi_addr);
	598	}