[linux-2.6-block.git] / arch / ia64 / kernel / irq_ia64.c

/*
 * linux/arch/ia64/kernel/irq_ia64.c
 *
 * Copyright (C) 1998-2001 Hewlett-Packard Co
 *	Stephane Eranian <eranian@hpl.hp.com>
 *	David Mosberger-Tang <davidm@hpl.hp.com>
 *
 *  6/10/99: Updated to bring in sync with x86 version to facilitate
 *	     support for SMP and different interrupt controllers.
 *
 * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
 *                      PCI to vector allocation routine.
 * 04/14/2004 Ashok Raj <ashok.raj@intel.com>
 *						Added CPU Hotplug handling for IPF.
 */

#include <linux/module.h>

#include <linux/jiffies.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/kernel_stat.h>
#include <linux/slab.h>
#include <linux/ptrace.h>
#include <linux/random.h>	/* for rand_initialize_irq() */
#include <linux/signal.h>
#include <linux/smp.h>
#include <linux/threads.h>
#include <linux/bitops.h>
#include <linux/irq.h>

#include <asm/delay.h>
#include <asm/intrinsics.h>
#include <asm/io.h>
#include <asm/hw_irq.h>
#include <asm/machvec.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/tlbflush.h>

#ifdef CONFIG_PERFMON
# include <asm/perfmon.h>
#endif

#define IRQ_DEBUG	0

#define IRQ_VECTOR_UNASSIGNED	(0)

#define IRQ_UNUSED		(0)
#define IRQ_USED		(1)
#define IRQ_RSVD		(2)

/* These can be overridden in platform_irq_init */
int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;

/* default base addr of IPI table */
void __iomem *ipi_base_addr = ((void __iomem *)
			       (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR));

static cpumask_t vector_allocation_domain(int cpu);

/*
 * Legacy IRQ to IA-64 vector translation table.
 */
__u8 isa_irq_to_vector_map[16] = {
	/* 8259 IRQ translation, first 16 entries */
	0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
	0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
};
EXPORT_SYMBOL(isa_irq_to_vector_map);

DEFINE_SPINLOCK(vector_lock);

struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
	[0 ... NR_IRQS - 1] = {
		.vector = IRQ_VECTOR_UNASSIGNED,
		.domain = CPU_MASK_NONE
	}
};

DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
	[0 ... IA64_NUM_VECTORS - 1] = -1
};

static cpumask_t vector_table[IA64_NUM_VECTORS] = {
	[0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
};

static int irq_status[NR_IRQS] = {
	[0 ... NR_IRQS -1] = IRQ_UNUSED
};

int check_irq_used(int irq)
{
	if (irq_status[irq] == IRQ_USED)
		return 1;

	return -1;
}

static inline int find_unassigned_irq(void)
{
	int irq;

	for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
		if (irq_status[irq] == IRQ_UNUSED)
			return irq;
	return -ENOSPC;
}

static inline int find_unassigned_vector(cpumask_t domain)
{
	cpumask_t mask;
	int pos, vector;

	cpus_and(mask, domain, cpu_online_map);
	if (cpus_empty(mask))
		return -EINVAL;

	for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
		vector = IA64_FIRST_DEVICE_VECTOR + pos;
		cpus_and(mask, domain, vector_table[vector]);
		if (!cpus_empty(mask))
			continue;
		return vector;
	}
	return -ENOSPC;
}

static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
{
	cpumask_t mask;
	int cpu;
	struct irq_cfg *cfg = &irq_cfg[irq];

	BUG_ON((unsigned)irq >= NR_IRQS);
	BUG_ON((unsigned)vector >= IA64_NUM_VECTORS);

	cpus_and(mask, domain, cpu_online_map);
	if (cpus_empty(mask))
		return -EINVAL;
	if ((cfg->vector == vector) && cpus_equal(cfg->domain, domain))
		return 0;
	if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
		return -EBUSY;
	for_each_cpu_mask(cpu, mask)
		per_cpu(vector_irq, cpu)[vector] = irq;
	cfg->vector = vector;
	cfg->domain = domain;
	irq_status[irq] = IRQ_USED;
	cpus_or(vector_table[vector], vector_table[vector], domain);
	return 0;
}

int bind_irq_vector(int irq, int vector, cpumask_t domain)
{
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&vector_lock, flags);
	ret = __bind_irq_vector(irq, vector, domain);
	spin_unlock_irqrestore(&vector_lock, flags);
	return ret;
}

static void __clear_irq_vector(int irq)
{
	int vector, cpu;
	cpumask_t mask;
	cpumask_t domain;
	struct irq_cfg *cfg = &irq_cfg[irq];

	BUG_ON((unsigned)irq >= NR_IRQS);
	BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
	vector = cfg->vector;
	domain = cfg->domain;
	cpus_and(mask, cfg->domain, cpu_online_map);
	for_each_cpu_mask(cpu, mask)
		per_cpu(vector_irq, cpu)[vector] = -1;
	cfg->vector = IRQ_VECTOR_UNASSIGNED;
	cfg->domain = CPU_MASK_NONE;
	irq_status[irq] = IRQ_UNUSED;
	cpus_andnot(vector_table[vector], vector_table[vector], domain);
}

static void clear_irq_vector(int irq)
{
	unsigned long flags;

	spin_lock_irqsave(&vector_lock, flags);
	__clear_irq_vector(irq);
	spin_unlock_irqrestore(&vector_lock, flags);
}

int
assign_irq_vector (int irq)
{
	unsigned long flags;
	int vector, cpu;
	cpumask_t domain = CPU_MASK_NONE;

	vector = -ENOSPC;

	spin_lock_irqsave(&vector_lock, flags);
	for_each_online_cpu(cpu) {
		domain = vector_allocation_domain(cpu);
		vector = find_unassigned_vector(domain);
		if (vector >= 0)
			break;
	}
	if (vector < 0)
		goto out;
	if (irq == AUTO_ASSIGN)
		irq = vector;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
 out:
	spin_unlock_irqrestore(&vector_lock, flags);
	return vector;
}

void
free_irq_vector (int vector)
{
	if (vector < IA64_FIRST_DEVICE_VECTOR ||
	    vector > IA64_LAST_DEVICE_VECTOR)
		return;
	clear_irq_vector(vector);
}

int
reserve_irq_vector (int vector)
{
	if (vector < IA64_FIRST_DEVICE_VECTOR ||
	    vector > IA64_LAST_DEVICE_VECTOR)
		return -EINVAL;
	return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
}

/*
 * Initialize vector_irq on a new cpu. This function must be called
 * with vector_lock held.
 */
void __setup_vector_irq(int cpu)
{
	int irq, vector;

	/* Clear vector_irq */
	for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
		per_cpu(vector_irq, cpu)[vector] = -1;
	/* Mark the inuse vectors */
	for (irq = 0; irq < NR_IRQS; ++irq) {
		if (!cpu_isset(cpu, irq_cfg[irq].domain))
			continue;
		vector = irq_to_vector(irq);
		per_cpu(vector_irq, cpu)[vector] = irq;
	}
}

#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG))
static enum vector_domain_type {
	VECTOR_DOMAIN_NONE,
	VECTOR_DOMAIN_PERCPU
} vector_domain_type = VECTOR_DOMAIN_NONE;

static cpumask_t vector_allocation_domain(int cpu)
{
	if (vector_domain_type == VECTOR_DOMAIN_PERCPU)
		return cpumask_of_cpu(cpu);
	return CPU_MASK_ALL;
}

static int __init parse_vector_domain(char *arg)
{
	if (!arg)
		return -EINVAL;
	if (!strcmp(arg, "percpu")) {
		vector_domain_type = VECTOR_DOMAIN_PERCPU;
		no_int_routing = 1;
	}
	return 0;
}
early_param("vector", parse_vector_domain);
#else
static cpumask_t vector_allocation_domain(int cpu)
{
	return CPU_MASK_ALL;
}
#endif


void destroy_and_reserve_irq(unsigned int irq)
{
	unsigned long flags;

	dynamic_irq_cleanup(irq);

	spin_lock_irqsave(&vector_lock, flags);
	__clear_irq_vector(irq);
	irq_status[irq] = IRQ_RSVD;
	spin_unlock_irqrestore(&vector_lock, flags);
}

static int __reassign_irq_vector(int irq, int cpu)
{
	struct irq_cfg *cfg = &irq_cfg[irq];
	int vector;
	cpumask_t domain;

	if (cfg->vector == IRQ_VECTOR_UNASSIGNED || !cpu_online(cpu))
		return -EINVAL;
	if (cpu_isset(cpu, cfg->domain))
		return 0;
	domain = vector_allocation_domain(cpu);
	vector = find_unassigned_vector(domain);
	if (vector < 0)
		return -ENOSPC;
	__clear_irq_vector(irq);
	BUG_ON(__bind_irq_vector(irq, vector, domain));
	return 0;
}

int reassign_irq_vector(int irq, int cpu)
{
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&vector_lock, flags);
	ret = __reassign_irq_vector(irq, cpu);
	spin_unlock_irqrestore(&vector_lock, flags);
	return ret;
}

/*
 * Dynamic irq allocate and deallocation for MSI
 */
int create_irq(void)
{
	unsigned long flags;
	int irq, vector, cpu;
	cpumask_t domain = CPU_MASK_NONE;

	irq = vector = -ENOSPC;
	spin_lock_irqsave(&vector_lock, flags);
	for_each_online_cpu(cpu) {
		domain = vector_allocation_domain(cpu);
		vector = find_unassigned_vector(domain);
		if (vector >= 0)
			break;
	}
	if (vector < 0)
		goto out;
	irq = find_unassigned_irq();
	if (irq < 0)
		goto out;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
 out:
	spin_unlock_irqrestore(&vector_lock, flags);
	if (irq >= 0)
		dynamic_irq_init(irq);
	return irq;
}

void destroy_irq(unsigned int irq)
{
	dynamic_irq_cleanup(irq);
	clear_irq_vector(irq);
}

#ifdef CONFIG_SMP
#	define IS_RESCHEDULE(vec)	(vec == IA64_IPI_RESCHEDULE)
#	define IS_LOCAL_TLB_FLUSH(vec)	(vec == IA64_IPI_LOCAL_TLB_FLUSH)
#else
#	define IS_RESCHEDULE(vec)	(0)
#	define IS_LOCAL_TLB_FLUSH(vec)	(0)
#endif
/*
 * That's where the IVT branches when we get an external
 * interrupt. This branches to the correct hardware IRQ handler via
 * function ptr.
 */
void
ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
{
	struct pt_regs *old_regs = set_irq_regs(regs);
	unsigned long saved_tpr;

#if IRQ_DEBUG
	{
		unsigned long bsp, sp;

		/*
		 * Note: if the interrupt happened while executing in
		 * the context switch routine (ia64_switch_to), we may
		 * get a spurious stack overflow here.  This is
		 * because the register and the memory stack are not
		 * switched atomically.
		 */
		bsp = ia64_getreg(_IA64_REG_AR_BSP);
		sp = ia64_getreg(_IA64_REG_SP);

		if ((sp - bsp) < 1024) {
			static unsigned char count;
			static long last_time;

			if (jiffies - last_time > 5*HZ)
				count = 0;
			if (++count < 5) {
				last_time = jiffies;
				printk("ia64_handle_irq: DANGER: less than "
				       "1KB of free stack space!!\n"
				       "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
			}
		}
	}
#endif /* IRQ_DEBUG */

	/*
	 * Always set TPR to limit maximum interrupt nesting depth to
	 * 16 (without this, it would be ~240, which could easily lead
	 * to kernel stack overflows).
	 */
	irq_enter();
	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	ia64_srlz_d();
	while (vector != IA64_SPURIOUS_INT_VECTOR) {
		if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
			smp_local_flush_tlb();
			kstat_this_cpu.irqs[vector]++;
		} else if (unlikely(IS_RESCHEDULE(vector)))
			kstat_this_cpu.irqs[vector]++;
		else {
			int irq = local_vector_to_irq(vector);

			ia64_setreg(_IA64_REG_CR_TPR, vector);
			ia64_srlz_d();

			if (unlikely(irq < 0)) {
				printk(KERN_ERR "%s: Unexpected interrupt "
				       "vector %d on CPU %d is not mapped "
				       "to any IRQ!\n", __FUNCTION__, vector,
				       smp_processor_id());
			} else
				generic_handle_irq(irq);

			/*
			 * Disable interrupts and send EOI:
			 */
			local_irq_disable();
			ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
		}
		ia64_eoi();
		vector = ia64_get_ivr();
	}
	/*
	 * This must be done *after* the ia64_eoi().  For example, the keyboard softirq
	 * handler needs to be able to wait for further keyboard interrupts, which can't
	 * come through until ia64_eoi() has been done.
	 */
	irq_exit();
	set_irq_regs(old_regs);
}

#ifdef CONFIG_HOTPLUG_CPU
/*
 * This function emulates a interrupt processing when a cpu is about to be
 * brought down.
 */
void ia64_process_pending_intr(void)
{
	ia64_vector vector;
	unsigned long saved_tpr;
	extern unsigned int vectors_in_migration[NR_IRQS];

	vector = ia64_get_ivr();

	 irq_enter();
	 saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	 ia64_srlz_d();

	 /*
	  * Perform normal interrupt style processing
	  */
	while (vector != IA64_SPURIOUS_INT_VECTOR) {
		if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
			smp_local_flush_tlb();
			kstat_this_cpu.irqs[vector]++;
		} else if (unlikely(IS_RESCHEDULE(vector)))
			kstat_this_cpu.irqs[vector]++;
		else {
			struct pt_regs *old_regs = set_irq_regs(NULL);
			int irq = local_vector_to_irq(vector);

			ia64_setreg(_IA64_REG_CR_TPR, vector);
			ia64_srlz_d();

			/*
			 * Now try calling normal ia64_handle_irq as it would have got called
			 * from a real intr handler. Try passing null for pt_regs, hopefully
			 * it will work. I hope it works!.
			 * Probably could shared code.
			 */
			if (unlikely(irq < 0)) {
				printk(KERN_ERR "%s: Unexpected interrupt "
				       "vector %d on CPU %d not being mapped "
				       "to any IRQ!!\n", __FUNCTION__, vector,
				       smp_processor_id());
			} else {
				vectors_in_migration[irq]=0;
				generic_handle_irq(irq);
			}
			set_irq_regs(old_regs);

			/*
			 * Disable interrupts and send EOI
			 */
			local_irq_disable();
			ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
		}
		ia64_eoi();
		vector = ia64_get_ivr();
	}
	irq_exit();
}
#endif


#ifdef CONFIG_SMP

static irqreturn_t dummy_handler (int irq, void *dev_id)
{
	BUG();
}
extern irqreturn_t handle_IPI (int irq, void *dev_id);

static struct irqaction ipi_irqaction = {
	.handler =	handle_IPI,
	.flags =	IRQF_DISABLED,
	.name =		"IPI"
};

static struct irqaction resched_irqaction = {
	.handler =	dummy_handler,
	.flags =	IRQF_DISABLED,
	.name =		"resched"
};

static struct irqaction tlb_irqaction = {
	.handler =	dummy_handler,
	.flags =	IRQF_DISABLED,
	.name =		"tlb_flush"
};

#endif

void
register_percpu_irq (ia64_vector vec, struct irqaction *action)
{
	irq_desc_t *desc;
	unsigned int irq;

	irq = vec;
	BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
	desc = irq_desc + irq;
	desc->status |= IRQ_PER_CPU;
	desc->chip = &irq_type_ia64_lsapic;
	if (action)
		setup_irq(irq, action);
}

void __init
init_IRQ (void)
{
	register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
#ifdef CONFIG_SMP
	register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
	register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
	register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
#endif
#ifdef CONFIG_PERFMON
	pfm_init_percpu();
#endif
	platform_irq_init();
}

void
ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
{
	void __iomem *ipi_addr;
	unsigned long ipi_data;
	unsigned long phys_cpu_id;

#ifdef CONFIG_SMP
	phys_cpu_id = cpu_physical_id(cpu);
#else
	phys_cpu_id = (ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff;
#endif

	/*
	 * cpu number is in 8bit ID and 8bit EID
	 */

	ipi_data = (delivery_mode << 8) | (vector & 0xff);
	ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) | ((redirect & 1) << 3));

	writeq(ipi_data, ipi_addr);
}
Commit	Line	Data
1da177e4	1	/*
f30c2269	2	* linux/arch/ia64/kernel/irq_ia64.c
1da177e4 LT	3	*
	4	* Copyright (C) 1998-2001 Hewlett-Packard Co
	5	* Stephane Eranian <eranian@hpl.hp.com>
	6	* David Mosberger-Tang <davidm@hpl.hp.com>
	7	*
	8	* 6/10/99: Updated to bring in sync with x86 version to facilitate
	9	* support for SMP and different interrupt controllers.
	10	*
	11	* 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
	12	* PCI to vector allocation routine.
	13	* 04/14/2004 Ashok Raj <ashok.raj@intel.com>
	14	* Added CPU Hotplug handling for IPF.
	15	*/
	16
1da177e4 LT	17	#include <linux/module.h>
	18
	19	#include <linux/jiffies.h>
	20	#include <linux/errno.h>
	21	#include <linux/init.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/ioport.h>
	24	#include <linux/kernel_stat.h>
	25	#include <linux/slab.h>
	26	#include <linux/ptrace.h>
	27	#include <linux/random.h> /* for rand_initialize_irq() */
	28	#include <linux/signal.h>
	29	#include <linux/smp.h>
1da177e4 LT	30	#include <linux/threads.h>
1da177e4 LT	31	#include <linux/bitops.h>
b6cf2583	32	#include <linux/irq.h>
1da177e4 LT	33
	34	#include <asm/delay.h>
	35	#include <asm/intrinsics.h>
	36	#include <asm/io.h>
	37	#include <asm/hw_irq.h>
	38	#include <asm/machvec.h>
	39	#include <asm/pgtable.h>
	40	#include <asm/system.h>
3be44b9c	41	#include <asm/tlbflush.h>
1da177e4 LT	42
	43	#ifdef CONFIG_PERFMON
	44	# include <asm/perfmon.h>
	45	#endif
	46
	47	#define IRQ_DEBUG 0
	48
e1b30a39 YI	49	#define IRQ_VECTOR_UNASSIGNED (0)
	50
	51	#define IRQ_UNUSED (0)
	52	#define IRQ_USED (1)
	53	#define IRQ_RSVD (2)
	54
10083072 MM	55	/* These can be overridden in platform_irq_init */
	56	int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
	57	int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;
	58
1da177e4 LT	59	/* default base addr of IPI table */
	60	void __iomem ipi_base_addr = ((void __iomem )
	61	(__IA64_UNCACHED_OFFSET \| IA64_IPI_DEFAULT_BASE_ADDR));
	62
4994be1b YI	63	static cpumask_t vector_allocation_domain(int cpu);
4994be1b YI	64
1da177e4 LT	65	/*
	66	* Legacy IRQ to IA-64 vector translation table.
	67	*/
	68	__u8 isa_irq_to_vector_map[16] = {
	69	/* 8259 IRQ translation, first 16 entries */
	70	0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
	71	0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
	72	};
	73	EXPORT_SYMBOL(isa_irq_to_vector_map);
	74
e1b30a39 YI	75	DEFINE_SPINLOCK(vector_lock);
	76
	77	struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
4994be1b YI	78	[0 ... NR_IRQS - 1] = {
	79	.vector = IRQ_VECTOR_UNASSIGNED,
	80	.domain = CPU_MASK_NONE
	81	}
e1b30a39 YI	82	};
	83
	84	DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
17764d24	85	[0 ... IA64_NUM_VECTORS - 1] = -1
e1b30a39 YI	86	};
e1b30a39 YI	87
6ffbc823 KK	88	static cpumask_t vector_table[IA64_NUM_VECTORS] = {
6ffbc823 KK	89	[0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
4994be1b YI	90	};
4994be1b YI	91
e1b30a39 YI	92	static int irq_status[NR_IRQS] = {
	93	[0 ... NR_IRQS -1] = IRQ_UNUSED
	94	};
	95
	96	int check_irq_used(int irq)
	97	{
	98	if (irq_status[irq] == IRQ_USED)
	99	return 1;
	100
	101	return -1;
	102	}
	103
e1b30a39 YI	104	static inline int find_unassigned_irq(void)
	105	{
	106	int irq;
	107
	108	for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
	109	if (irq_status[irq] == IRQ_UNUSED)
	110	return irq;
	111	return -ENOSPC;
	112	}
	113
4994be1b	114	static inline int find_unassigned_vector(cpumask_t domain)
e1b30a39	115	{
4994be1b	116	cpumask_t mask;
6ffbc823	117	int pos, vector;
4994be1b YI	118
	119	cpus_and(mask, domain, cpu_online_map);
	120	if (cpus_empty(mask))
	121	return -EINVAL;
e1b30a39	122
4994be1b	123	for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
6ffbc823 KK	124	vector = IA64_FIRST_DEVICE_VECTOR + pos;
6ffbc823 KK	125	cpus_and(mask, domain, vector_table[vector]);
4994be1b YI	126	if (!cpus_empty(mask))
4994be1b YI	127	continue;
6ffbc823	128	return vector;
4994be1b	129	}
e1b30a39 YI	130	return -ENOSPC;
	131	}
	132
4994be1b	133	static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
e1b30a39	134	{
4994be1b	135	cpumask_t mask;
6ffbc823	136	int cpu;
4994be1b	137	struct irq_cfg *cfg = &irq_cfg[irq];
e1b30a39	138
6bde71ec KK	139	BUG_ON((unsigned)irq >= NR_IRQS);
	140	BUG_ON((unsigned)vector >= IA64_NUM_VECTORS);
	141
4994be1b YI	142	cpus_and(mask, domain, cpu_online_map);
	143	if (cpus_empty(mask))
	144	return -EINVAL;
	145	if ((cfg->vector == vector) && cpus_equal(cfg->domain, domain))
e1b30a39	146	return 0;
4994be1b	147	if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
e1b30a39	148	return -EBUSY;
4994be1b	149	for_each_cpu_mask(cpu, mask)
e1b30a39	150	per_cpu(vector_irq, cpu)[vector] = irq;
4994be1b YI	151	cfg->vector = vector;
4994be1b YI	152	cfg->domain = domain;
e1b30a39	153	irq_status[irq] = IRQ_USED;
6ffbc823	154	cpus_or(vector_table[vector], vector_table[vector], domain);
e1b30a39 YI	155	return 0;
	156	}
	157
4994be1b	158	int bind_irq_vector(int irq, int vector, cpumask_t domain)
e1b30a39 YI	159	{
	160	unsigned long flags;
	161	int ret;
	162
	163	spin_lock_irqsave(&vector_lock, flags);
4994be1b	164	ret = __bind_irq_vector(irq, vector, domain);
e1b30a39 YI	165	spin_unlock_irqrestore(&vector_lock, flags);
	166	return ret;
	167	}
	168
cd378f18	169	static void __clear_irq_vector(int irq)
e1b30a39	170	{
6ffbc823	171	int vector, cpu;
4994be1b YI	172	cpumask_t mask;
	173	cpumask_t domain;
	174	struct irq_cfg *cfg = &irq_cfg[irq];
e1b30a39	175
e1b30a39	176	BUG_ON((unsigned)irq >= NR_IRQS);
4994be1b YI	177	BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
	178	vector = cfg->vector;
	179	domain = cfg->domain;
	180	cpus_and(mask, cfg->domain, cpu_online_map);
	181	for_each_cpu_mask(cpu, mask)
17764d24	182	per_cpu(vector_irq, cpu)[vector] = -1;
4994be1b YI	183	cfg->vector = IRQ_VECTOR_UNASSIGNED;
4994be1b YI	184	cfg->domain = CPU_MASK_NONE;
e1b30a39	185	irq_status[irq] = IRQ_UNUSED;
6ffbc823	186	cpus_andnot(vector_table[vector], vector_table[vector], domain);
cd378f18 YI	187	}
	188
	189	static void clear_irq_vector(int irq)
	190	{
	191	unsigned long flags;
	192
	193	spin_lock_irqsave(&vector_lock, flags);
	194	__clear_irq_vector(irq);
e1b30a39 YI	195	spin_unlock_irqrestore(&vector_lock, flags);
e1b30a39 YI	196	}
1da177e4 LT	197
1da177e4 LT	198	int
3b5cc090	199	assign_irq_vector (int irq)
1da177e4	200	{
e1b30a39	201	unsigned long flags;
4994be1b	202	int vector, cpu;
373167e8	203	cpumask_t domain = CPU_MASK_NONE;
4994be1b YI	204
4994be1b YI	205	vector = -ENOSPC;
e1b30a39	206
4994be1b	207	spin_lock_irqsave(&vector_lock, flags);
4994be1b YI	208	for_each_online_cpu(cpu) {
	209	domain = vector_allocation_domain(cpu);
	210	vector = find_unassigned_vector(domain);
	211	if (vector >= 0)
	212	break;
	213	}
e1b30a39 YI	214	if (vector < 0)
e1b30a39 YI	215	goto out;
8f5ad1a8 YI	216	if (irq == AUTO_ASSIGN)
8f5ad1a8 YI	217	irq = vector;
4994be1b	218	BUG_ON(__bind_irq_vector(irq, vector, domain));
e1b30a39	219	out:
4994be1b	220	spin_unlock_irqrestore(&vector_lock, flags);
1da177e4 LT	221	return vector;
	222	}
	223
	224	void
	225	free_irq_vector (int vector)
	226	{
e1b30a39 YI	227	if (vector < IA64_FIRST_DEVICE_VECTOR \|\|
e1b30a39 YI	228	vector > IA64_LAST_DEVICE_VECTOR)
1da177e4	229	return;
e1b30a39	230	clear_irq_vector(vector);
1da177e4 LT	231	}
1da177e4 LT	232
10083072 MM	233	int
	234	reserve_irq_vector (int vector)
	235	{
10083072 MM	236	if (vector < IA64_FIRST_DEVICE_VECTOR \|\|
	237	vector > IA64_LAST_DEVICE_VECTOR)
	238	return -EINVAL;
4994be1b	239	return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
e1b30a39	240	}
10083072	241
e1b30a39 YI	242	/*
	243	* Initialize vector_irq on a new cpu. This function must be called
	244	* with vector_lock held.
	245	*/
	246	void __setup_vector_irq(int cpu)
	247	{
	248	int irq, vector;
	249
	250	/* Clear vector_irq */
	251	for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
17764d24	252	per_cpu(vector_irq, cpu)[vector] = -1;
e1b30a39 YI	253	/* Mark the inuse vectors */
e1b30a39 YI	254	for (irq = 0; irq < NR_IRQS; ++irq) {
4994be1b YI	255	if (!cpu_isset(cpu, irq_cfg[irq].domain))
	256	continue;
	257	vector = irq_to_vector(irq);
	258	per_cpu(vector_irq, cpu)[vector] = irq;
e1b30a39 YI	259	}
	260	}
	261
e5bd762b	262	#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) \|\| defined(CONFIG_IA64_DIG))
d080d397 YI	263	static enum vector_domain_type {
	264	VECTOR_DOMAIN_NONE,
	265	VECTOR_DOMAIN_PERCPU
	266	} vector_domain_type = VECTOR_DOMAIN_NONE;
	267
4994be1b YI	268	static cpumask_t vector_allocation_domain(int cpu)
4994be1b YI	269	{
d080d397 YI	270	if (vector_domain_type == VECTOR_DOMAIN_PERCPU)
d080d397 YI	271	return cpumask_of_cpu(cpu);
4994be1b YI	272	return CPU_MASK_ALL;
	273	}
	274
d080d397 YI	275	static int __init parse_vector_domain(char *arg)
	276	{
	277	if (!arg)
	278	return -EINVAL;
	279	if (!strcmp(arg, "percpu")) {
	280	vector_domain_type = VECTOR_DOMAIN_PERCPU;
	281	no_int_routing = 1;
	282	}
074ff856	283	return 0;
d080d397 YI	284	}
	285	early_param("vector", parse_vector_domain);
	286	#else
	287	static cpumask_t vector_allocation_domain(int cpu)
	288	{
	289	return CPU_MASK_ALL;
	290	}
	291	#endif
	292
4994be1b	293
e1b30a39 YI	294	void destroy_and_reserve_irq(unsigned int irq)
e1b30a39 YI	295	{
216fcd29 KK	296	unsigned long flags;
216fcd29 KK	297
e1b30a39 YI	298	dynamic_irq_cleanup(irq);
e1b30a39 YI	299
216fcd29 KK	300	spin_lock_irqsave(&vector_lock, flags);
	301	__clear_irq_vector(irq);
	302	irq_status[irq] = IRQ_RSVD;
	303	spin_unlock_irqrestore(&vector_lock, flags);
10083072 MM	304	}
10083072 MM	305
cd378f18 YI	306	static int __reassign_irq_vector(int irq, int cpu)
	307	{
	308	struct irq_cfg *cfg = &irq_cfg[irq];
	309	int vector;
	310	cpumask_t domain;
	311
	312	if (cfg->vector == IRQ_VECTOR_UNASSIGNED \|\| !cpu_online(cpu))
	313	return -EINVAL;
	314	if (cpu_isset(cpu, cfg->domain))
	315	return 0;
	316	domain = vector_allocation_domain(cpu);
	317	vector = find_unassigned_vector(domain);
	318	if (vector < 0)
	319	return -ENOSPC;
	320	__clear_irq_vector(irq);
	321	BUG_ON(__bind_irq_vector(irq, vector, domain));
	322	return 0;
	323	}
	324
	325	int reassign_irq_vector(int irq, int cpu)
	326	{
	327	unsigned long flags;
	328	int ret;
	329
	330	spin_lock_irqsave(&vector_lock, flags);
	331	ret = __reassign_irq_vector(irq, cpu);
	332	spin_unlock_irqrestore(&vector_lock, flags);
	333	return ret;
	334	}
	335
b6cf2583 EB	336	/*
	337	* Dynamic irq allocate and deallocation for MSI
	338	*/
	339	int create_irq(void)
	340	{
e1b30a39	341	unsigned long flags;
4994be1b	342	int irq, vector, cpu;
373167e8	343	cpumask_t domain = CPU_MASK_NONE;
e1b30a39	344
4994be1b	345	irq = vector = -ENOSPC;
e1b30a39	346	spin_lock_irqsave(&vector_lock, flags);
4994be1b YI	347	for_each_online_cpu(cpu) {
	348	domain = vector_allocation_domain(cpu);
	349	vector = find_unassigned_vector(domain);
	350	if (vector >= 0)
	351	break;
	352	}
e1b30a39 YI	353	if (vector < 0)
	354	goto out;
	355	irq = find_unassigned_irq();
	356	if (irq < 0)
	357	goto out;
4994be1b	358	BUG_ON(__bind_irq_vector(irq, vector, domain));
e1b30a39 YI	359	out:
	360	spin_unlock_irqrestore(&vector_lock, flags);
	361	if (irq >= 0)
	362	dynamic_irq_init(irq);
	363	return irq;
b6cf2583 EB	364	}
	365
	366	void destroy_irq(unsigned int irq)
	367	{
	368	dynamic_irq_cleanup(irq);
e1b30a39	369	clear_irq_vector(irq);
b6cf2583 EB	370	}
b6cf2583 EB	371
1da177e4 LT	372	#ifdef CONFIG_SMP
1da177e4 LT	373	# define IS_RESCHEDULE(vec) (vec == IA64_IPI_RESCHEDULE)
3be44b9c	374	# define IS_LOCAL_TLB_FLUSH(vec) (vec == IA64_IPI_LOCAL_TLB_FLUSH)
1da177e4 LT	375	#else
1da177e4 LT	376	# define IS_RESCHEDULE(vec) (0)
3be44b9c	377	# define IS_LOCAL_TLB_FLUSH(vec) (0)
1da177e4 LT	378	#endif
	379	/*
	380	* That's where the IVT branches when we get an external
	381	* interrupt. This branches to the correct hardware IRQ handler via
	382	* function ptr.
	383	*/
	384	void
	385	ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
	386	{
7d12e780	387	struct pt_regs *old_regs = set_irq_regs(regs);
1da177e4 LT	388	unsigned long saved_tpr;
	389
	390	#if IRQ_DEBUG
	391	{
	392	unsigned long bsp, sp;
	393
	394	/*
	395	* Note: if the interrupt happened while executing in
	396	* the context switch routine (ia64_switch_to), we may
	397	* get a spurious stack overflow here. This is
	398	* because the register and the memory stack are not
	399	* switched atomically.
	400	*/
	401	bsp = ia64_getreg(_IA64_REG_AR_BSP);
	402	sp = ia64_getreg(_IA64_REG_SP);
	403
	404	if ((sp - bsp) < 1024) {
	405	static unsigned char count;
	406	static long last_time;
	407
	408	if (jiffies - last_time > 5*HZ)
	409	count = 0;
	410	if (++count < 5) {
	411	last_time = jiffies;
	412	printk("ia64_handle_irq: DANGER: less than "
	413	"1KB of free stack space!!\n"
	414	"(bsp=0x%lx, sp=%lx)\n", bsp, sp);
	415	}
	416	}
	417	}
	418	#endif /* IRQ_DEBUG */
	419
	420	/*
	421	* Always set TPR to limit maximum interrupt nesting depth to
	422	* 16 (without this, it would be ~240, which could easily lead
	423	* to kernel stack overflows).
	424	*/
	425	irq_enter();
	426	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	427	ia64_srlz_d();
	428	while (vector != IA64_SPURIOUS_INT_VECTOR) {
3be44b9c JS	429	if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
	430	smp_local_flush_tlb();
	431	kstat_this_cpu.irqs[vector]++;
	432	} else if (unlikely(IS_RESCHEDULE(vector)))
	433	kstat_this_cpu.irqs[vector]++;
9b3377f9	434	else {
17764d24 KK	435	int irq = local_vector_to_irq(vector);
17764d24 KK	436
1da177e4 LT	437	ia64_setreg(_IA64_REG_CR_TPR, vector);
	438	ia64_srlz_d();
	439
17764d24 KK	440	if (unlikely(irq < 0)) {
	441	printk(KERN_ERR "%s: Unexpected interrupt "
	442	"vector %d on CPU %d is not mapped "
	443	"to any IRQ!\n", __FUNCTION__, vector,
	444	smp_processor_id());
	445	} else
	446	generic_handle_irq(irq);
1da177e4 LT	447
	448	/*
	449	* Disable interrupts and send EOI:
	450	*/
	451	local_irq_disable();
	452	ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
	453	}
	454	ia64_eoi();
	455	vector = ia64_get_ivr();
	456	}
	457	/*
	458	* This must be done after the ia64_eoi(). For example, the keyboard softirq
	459	* handler needs to be able to wait for further keyboard interrupts, which can't
	460	* come through until ia64_eoi() has been done.
	461	*/
	462	irq_exit();
7d12e780	463	set_irq_regs(old_regs);
1da177e4 LT	464	}
	465
	466	#ifdef CONFIG_HOTPLUG_CPU
	467	/*
	468	* This function emulates a interrupt processing when a cpu is about to be
	469	* brought down.
	470	*/
	471	void ia64_process_pending_intr(void)
	472	{
	473	ia64_vector vector;
	474	unsigned long saved_tpr;
	475	extern unsigned int vectors_in_migration[NR_IRQS];
	476
	477	vector = ia64_get_ivr();
	478
	479	irq_enter();
	480	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	481	ia64_srlz_d();
	482
	483	/*
	484	* Perform normal interrupt style processing
	485	*/
	486	while (vector != IA64_SPURIOUS_INT_VECTOR) {
3be44b9c JS	487	if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
	488	smp_local_flush_tlb();
	489	kstat_this_cpu.irqs[vector]++;
	490	} else if (unlikely(IS_RESCHEDULE(vector)))
	491	kstat_this_cpu.irqs[vector]++;
9b3377f9	492	else {
8c1addbc	493	struct pt_regs *old_regs = set_irq_regs(NULL);
17764d24	494	int irq = local_vector_to_irq(vector);
8c1addbc	495
1da177e4 LT	496	ia64_setreg(_IA64_REG_CR_TPR, vector);
	497	ia64_srlz_d();
	498
	499	/*
	500	* Now try calling normal ia64_handle_irq as it would have got called
	501	* from a real intr handler. Try passing null for pt_regs, hopefully
	502	* it will work. I hope it works!.
	503	* Probably could shared code.
	504	*/
17764d24 KK	505	if (unlikely(irq < 0)) {
	506	printk(KERN_ERR "%s: Unexpected interrupt "
	507	"vector %d on CPU %d not being mapped "
	508	"to any IRQ!!\n", __FUNCTION__, vector,
	509	smp_processor_id());
	510	} else {
	511	vectors_in_migration[irq]=0;
	512	generic_handle_irq(irq);
	513	}
8c1addbc	514	set_irq_regs(old_regs);
1da177e4 LT	515
	516	/*
	517	* Disable interrupts and send EOI
	518	*/
	519	local_irq_disable();
	520	ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
	521	}
	522	ia64_eoi();
	523	vector = ia64_get_ivr();
	524	}
	525	irq_exit();
	526	}
	527	#endif
	528
	529
	530	#ifdef CONFIG_SMP
1da177e4	531
9b3377f9 JS	532	static irqreturn_t dummy_handler (int irq, void *dev_id)
	533	{
	534	BUG();
	535	}
3be44b9c	536	extern irqreturn_t handle_IPI (int irq, void *dev_id);
9b3377f9	537
1da177e4 LT	538	static struct irqaction ipi_irqaction = {
1da177e4 LT	539	.handler = handle_IPI,
121a4226	540	.flags = IRQF_DISABLED,
1da177e4 LT	541	.name = "IPI"
1da177e4 LT	542	};
9b3377f9 JS	543
	544	static struct irqaction resched_irqaction = {
	545	.handler = dummy_handler,
38515e90	546	.flags = IRQF_DISABLED,
9b3377f9 JS	547	.name = "resched"
9b3377f9 JS	548	};
3be44b9c JS	549
	550	static struct irqaction tlb_irqaction = {
	551	.handler = dummy_handler,
5329571b	552	.flags = IRQF_DISABLED,
3be44b9c JS	553	.name = "tlb_flush"
	554	};
	555
1da177e4 LT	556	#endif
	557
	558	void
	559	register_percpu_irq (ia64_vector vec, struct irqaction *action)
	560	{
	561	irq_desc_t *desc;
	562	unsigned int irq;
	563
e1b30a39	564	irq = vec;
4994be1b	565	BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
e1b30a39 YI	566	desc = irq_desc + irq;
	567	desc->status \|= IRQ_PER_CPU;
	568	desc->chip = &irq_type_ia64_lsapic;
	569	if (action)
	570	setup_irq(irq, action);
1da177e4 LT	571	}
	572
	573	void __init
	574	init_IRQ (void)
	575	{
	576	register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
	577	#ifdef CONFIG_SMP
	578	register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
9b3377f9	579	register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
3be44b9c	580	register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
1da177e4 LT	581	#endif
	582	#ifdef CONFIG_PERFMON
	583	pfm_init_percpu();
	584	#endif
	585	platform_irq_init();
	586	}
	587
	588	void
	589	ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
	590	{
	591	void __iomem *ipi_addr;
	592	unsigned long ipi_data;
	593	unsigned long phys_cpu_id;
	594
	595	#ifdef CONFIG_SMP
	596	phys_cpu_id = cpu_physical_id(cpu);
	597	#else
	598	phys_cpu_id = (ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff;
	599	#endif
	600
	601	/*
	602	* cpu number is in 8bit ID and 8bit EID
	603	*/
	604
	605	ipi_data = (delivery_mode << 8) \| (vector & 0xff);
	606	ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) \| ((redirect & 1) << 3));
	607
	608	writeq(ipi_data, ipi_addr);
	609	}