[linux-2.6-block.git] / arch / ia64 / kernel / irq_ia64.c

/*
 * linux/arch/ia64/kernel/irq_ia64.c
 *
 * Copyright (C) 1998-2001 Hewlett-Packard Co
 *	Stephane Eranian <eranian@hpl.hp.com>
 *	David Mosberger-Tang <davidm@hpl.hp.com>
 *
 *  6/10/99: Updated to bring in sync with x86 version to facilitate
 *	     support for SMP and different interrupt controllers.
 *
 * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
 *                      PCI to vector allocation routine.
 * 04/14/2004 Ashok Raj <ashok.raj@intel.com>
 *						Added CPU Hotplug handling for IPF.
 */

#include <linux/module.h>

#include <linux/jiffies.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/kernel_stat.h>
#include <linux/slab.h>
#include <linux/ptrace.h>
#include <linux/random.h>	/* for rand_initialize_irq() */
#include <linux/signal.h>
#include <linux/smp.h>
#include <linux/threads.h>
#include <linux/bitops.h>
#include <linux/irq.h>

#include <asm/delay.h>
#include <asm/intrinsics.h>
#include <asm/io.h>
#include <asm/hw_irq.h>
#include <asm/machvec.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/tlbflush.h>

#ifdef CONFIG_PERFMON
# include <asm/perfmon.h>
#endif

#define IRQ_DEBUG	0

#define IRQ_VECTOR_UNASSIGNED	(0)

#define IRQ_UNUSED		(0)
#define IRQ_USED		(1)
#define IRQ_RSVD		(2)

/* These can be overridden in platform_irq_init */
int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;

/* default base addr of IPI table */
void __iomem *ipi_base_addr = ((void __iomem *)
			       (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR));

static cpumask_t vector_allocation_domain(int cpu);

/*
 * Legacy IRQ to IA-64 vector translation table.
 */
__u8 isa_irq_to_vector_map[16] = {
	/* 8259 IRQ translation, first 16 entries */
	0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
	0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
};
EXPORT_SYMBOL(isa_irq_to_vector_map);

DEFINE_SPINLOCK(vector_lock);

struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
	[0 ... NR_IRQS - 1] = {
		.vector = IRQ_VECTOR_UNASSIGNED,
		.domain = CPU_MASK_NONE
	}
};

DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
	[0 ... IA64_NUM_VECTORS - 1] = -1
};

static cpumask_t vector_table[IA64_NUM_VECTORS] = {
	[0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
};

static int irq_status[NR_IRQS] = {
	[0 ... NR_IRQS -1] = IRQ_UNUSED
};

int check_irq_used(int irq)
{
	if (irq_status[irq] == IRQ_USED)
		return 1;

	return -1;
}

static inline int find_unassigned_irq(void)
{
	int irq;

	for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
		if (irq_status[irq] == IRQ_UNUSED)
			return irq;
	return -ENOSPC;
}

static inline int find_unassigned_vector(cpumask_t domain)
{
	cpumask_t mask;
	int pos, vector;

	cpus_and(mask, domain, cpu_online_map);
	if (cpus_empty(mask))
		return -EINVAL;

	for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
		vector = IA64_FIRST_DEVICE_VECTOR + pos;
		cpus_and(mask, domain, vector_table[vector]);
		if (!cpus_empty(mask))
			continue;
		return vector;
	}
	return -ENOSPC;
}

static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
{
	cpumask_t mask;
	int cpu;
	struct irq_cfg *cfg = &irq_cfg[irq];

	BUG_ON((unsigned)irq >= NR_IRQS);
	BUG_ON((unsigned)vector >= IA64_NUM_VECTORS);

	cpus_and(mask, domain, cpu_online_map);
	if (cpus_empty(mask))
		return -EINVAL;
	if ((cfg->vector == vector) && cpus_equal(cfg->domain, domain))
		return 0;
	if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
		return -EBUSY;
	for_each_cpu_mask(cpu, mask)
		per_cpu(vector_irq, cpu)[vector] = irq;
	cfg->vector = vector;
	cfg->domain = domain;
	irq_status[irq] = IRQ_USED;
	cpus_or(vector_table[vector], vector_table[vector], domain);
	return 0;
}

int bind_irq_vector(int irq, int vector, cpumask_t domain)
{
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&vector_lock, flags);
	ret = __bind_irq_vector(irq, vector, domain);
	spin_unlock_irqrestore(&vector_lock, flags);
	return ret;
}

static void __clear_irq_vector(int irq)
{
	int vector, cpu;
	cpumask_t mask;
	cpumask_t domain;
	struct irq_cfg *cfg = &irq_cfg[irq];

	BUG_ON((unsigned)irq >= NR_IRQS);
	BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
	vector = cfg->vector;
	domain = cfg->domain;
	cpus_and(mask, cfg->domain, cpu_online_map);
	for_each_cpu_mask(cpu, mask)
		per_cpu(vector_irq, cpu)[vector] = -1;
	cfg->vector = IRQ_VECTOR_UNASSIGNED;
	cfg->domain = CPU_MASK_NONE;
	irq_status[irq] = IRQ_UNUSED;
	cpus_andnot(vector_table[vector], vector_table[vector], domain);
}

static void clear_irq_vector(int irq)
{
	unsigned long flags;

	spin_lock_irqsave(&vector_lock, flags);
	__clear_irq_vector(irq);
	spin_unlock_irqrestore(&vector_lock, flags);
}

int
ia64_native_assign_irq_vector (int irq)
{
	unsigned long flags;
	int vector, cpu;
	cpumask_t domain = CPU_MASK_NONE;

	vector = -ENOSPC;

	spin_lock_irqsave(&vector_lock, flags);
	for_each_online_cpu(cpu) {
		domain = vector_allocation_domain(cpu);
		vector = find_unassigned_vector(domain);
		if (vector >= 0)
			break;
	}
	if (vector < 0)
		goto out;
	if (irq == AUTO_ASSIGN)
		irq = vector;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
 out:
	spin_unlock_irqrestore(&vector_lock, flags);
	return vector;
}

void
ia64_native_free_irq_vector (int vector)
{
	if (vector < IA64_FIRST_DEVICE_VECTOR ||
	    vector > IA64_LAST_DEVICE_VECTOR)
		return;
	clear_irq_vector(vector);
}

int
reserve_irq_vector (int vector)
{
	if (vector < IA64_FIRST_DEVICE_VECTOR ||
	    vector > IA64_LAST_DEVICE_VECTOR)
		return -EINVAL;
	return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
}

/*
 * Initialize vector_irq on a new cpu. This function must be called
 * with vector_lock held.
 */
void __setup_vector_irq(int cpu)
{
	int irq, vector;

	/* Clear vector_irq */
	for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
		per_cpu(vector_irq, cpu)[vector] = -1;
	/* Mark the inuse vectors */
	for (irq = 0; irq < NR_IRQS; ++irq) {
		if (!cpu_isset(cpu, irq_cfg[irq].domain))
			continue;
		vector = irq_to_vector(irq);
		per_cpu(vector_irq, cpu)[vector] = irq;
	}
}

#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG))
#define IA64_IRQ_MOVE_VECTOR	IA64_DEF_FIRST_DEVICE_VECTOR

static enum vector_domain_type {
	VECTOR_DOMAIN_NONE,
	VECTOR_DOMAIN_PERCPU
} vector_domain_type = VECTOR_DOMAIN_NONE;

static cpumask_t vector_allocation_domain(int cpu)
{
	if (vector_domain_type == VECTOR_DOMAIN_PERCPU)
		return cpumask_of_cpu(cpu);
	return CPU_MASK_ALL;
}

static int __irq_prepare_move(int irq, int cpu)
{
	struct irq_cfg *cfg = &irq_cfg[irq];
	int vector;
	cpumask_t domain;

	if (cfg->move_in_progress || cfg->move_cleanup_count)
		return -EBUSY;
	if (cfg->vector == IRQ_VECTOR_UNASSIGNED || !cpu_online(cpu))
		return -EINVAL;
	if (cpu_isset(cpu, cfg->domain))
		return 0;
	domain = vector_allocation_domain(cpu);
	vector = find_unassigned_vector(domain);
	if (vector < 0)
		return -ENOSPC;
	cfg->move_in_progress = 1;
	cfg->old_domain = cfg->domain;
	cfg->vector = IRQ_VECTOR_UNASSIGNED;
	cfg->domain = CPU_MASK_NONE;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
	return 0;
}

int irq_prepare_move(int irq, int cpu)
{
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&vector_lock, flags);
	ret = __irq_prepare_move(irq, cpu);
	spin_unlock_irqrestore(&vector_lock, flags);
	return ret;
}

void irq_complete_move(unsigned irq)
{
	struct irq_cfg *cfg = &irq_cfg[irq];
	cpumask_t cleanup_mask;
	int i;

	if (likely(!cfg->move_in_progress))
		return;

	if (unlikely(cpu_isset(smp_processor_id(), cfg->old_domain)))
		return;

	cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
	cfg->move_cleanup_count = cpus_weight(cleanup_mask);
	for_each_cpu_mask(i, cleanup_mask)
		platform_send_ipi(i, IA64_IRQ_MOVE_VECTOR, IA64_IPI_DM_INT, 0);
	cfg->move_in_progress = 0;
}

static irqreturn_t smp_irq_move_cleanup_interrupt(int irq, void *dev_id)
{
	int me = smp_processor_id();
	ia64_vector vector;
	unsigned long flags;

	for (vector = IA64_FIRST_DEVICE_VECTOR;
	     vector < IA64_LAST_DEVICE_VECTOR; vector++) {
		int irq;
		struct irq_desc *desc;
		struct irq_cfg *cfg;
		irq = __get_cpu_var(vector_irq)[vector];
		if (irq < 0)
			continue;

		desc = irq_desc + irq;
		cfg = irq_cfg + irq;
		spin_lock(&desc->lock);
		if (!cfg->move_cleanup_count)
			goto unlock;

		if (!cpu_isset(me, cfg->old_domain))
			goto unlock;

		spin_lock_irqsave(&vector_lock, flags);
		__get_cpu_var(vector_irq)[vector] = -1;
		cpu_clear(me, vector_table[vector]);
		spin_unlock_irqrestore(&vector_lock, flags);
		cfg->move_cleanup_count--;
	unlock:
		spin_unlock(&desc->lock);
	}
	return IRQ_HANDLED;
}

static struct irqaction irq_move_irqaction = {
	.handler =	smp_irq_move_cleanup_interrupt,
	.flags =	IRQF_DISABLED,
	.name =		"irq_move"
};

static int __init parse_vector_domain(char *arg)
{
	if (!arg)
		return -EINVAL;
	if (!strcmp(arg, "percpu")) {
		vector_domain_type = VECTOR_DOMAIN_PERCPU;
		no_int_routing = 1;
	}
	return 0;
}
early_param("vector", parse_vector_domain);
#else
static cpumask_t vector_allocation_domain(int cpu)
{
	return CPU_MASK_ALL;
}
#endif


void destroy_and_reserve_irq(unsigned int irq)
{
	unsigned long flags;

	dynamic_irq_cleanup(irq);

	spin_lock_irqsave(&vector_lock, flags);
	__clear_irq_vector(irq);
	irq_status[irq] = IRQ_RSVD;
	spin_unlock_irqrestore(&vector_lock, flags);
}

/*
 * Dynamic irq allocate and deallocation for MSI
 */
int create_irq(void)
{
	unsigned long flags;
	int irq, vector, cpu;
	cpumask_t domain = CPU_MASK_NONE;

	irq = vector = -ENOSPC;
	spin_lock_irqsave(&vector_lock, flags);
	for_each_online_cpu(cpu) {
		domain = vector_allocation_domain(cpu);
		vector = find_unassigned_vector(domain);
		if (vector >= 0)
			break;
	}
	if (vector < 0)
		goto out;
	irq = find_unassigned_irq();
	if (irq < 0)
		goto out;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
 out:
	spin_unlock_irqrestore(&vector_lock, flags);
	if (irq >= 0)
		dynamic_irq_init(irq);
	return irq;
}

void destroy_irq(unsigned int irq)
{
	dynamic_irq_cleanup(irq);
	clear_irq_vector(irq);
}

#ifdef CONFIG_SMP
#	define IS_RESCHEDULE(vec)	(vec == IA64_IPI_RESCHEDULE)
#	define IS_LOCAL_TLB_FLUSH(vec)	(vec == IA64_IPI_LOCAL_TLB_FLUSH)
#else
#	define IS_RESCHEDULE(vec)	(0)
#	define IS_LOCAL_TLB_FLUSH(vec)	(0)
#endif
/*
 * That's where the IVT branches when we get an external
 * interrupt. This branches to the correct hardware IRQ handler via
 * function ptr.
 */
void
ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
{
	struct pt_regs *old_regs = set_irq_regs(regs);
	unsigned long saved_tpr;

#if IRQ_DEBUG
	{
		unsigned long bsp, sp;

		/*
		 * Note: if the interrupt happened while executing in
		 * the context switch routine (ia64_switch_to), we may
		 * get a spurious stack overflow here.  This is
		 * because the register and the memory stack are not
		 * switched atomically.
		 */
		bsp = ia64_getreg(_IA64_REG_AR_BSP);
		sp = ia64_getreg(_IA64_REG_SP);

		if ((sp - bsp) < 1024) {
			static unsigned char count;
			static long last_time;

			if (time_after(jiffies, last_time + 5 * HZ))
				count = 0;
			if (++count < 5) {
				last_time = jiffies;
				printk("ia64_handle_irq: DANGER: less than "
				       "1KB of free stack space!!\n"
				       "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
			}
		}
	}
#endif /* IRQ_DEBUG */

	/*
	 * Always set TPR to limit maximum interrupt nesting depth to
	 * 16 (without this, it would be ~240, which could easily lead
	 * to kernel stack overflows).
	 */
	irq_enter();
	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	ia64_srlz_d();
	while (vector != IA64_SPURIOUS_INT_VECTOR) {
		if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
			smp_local_flush_tlb();
			kstat_this_cpu.irqs[vector]++;
		} else if (unlikely(IS_RESCHEDULE(vector)))
			kstat_this_cpu.irqs[vector]++;
		else {
			int irq = local_vector_to_irq(vector);

			ia64_setreg(_IA64_REG_CR_TPR, vector);
			ia64_srlz_d();

			if (unlikely(irq < 0)) {
				printk(KERN_ERR "%s: Unexpected interrupt "
				       "vector %d on CPU %d is not mapped "
				       "to any IRQ!\n", __func__, vector,
				       smp_processor_id());
			} else
				generic_handle_irq(irq);

			/*
			 * Disable interrupts and send EOI:
			 */
			local_irq_disable();
			ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
		}
		ia64_eoi();
		vector = ia64_get_ivr();
	}
	/*
	 * This must be done *after* the ia64_eoi().  For example, the keyboard softirq
	 * handler needs to be able to wait for further keyboard interrupts, which can't
	 * come through until ia64_eoi() has been done.
	 */
	irq_exit();
	set_irq_regs(old_regs);
}

#ifdef CONFIG_HOTPLUG_CPU
/*
 * This function emulates a interrupt processing when a cpu is about to be
 * brought down.
 */
void ia64_process_pending_intr(void)
{
	ia64_vector vector;
	unsigned long saved_tpr;
	extern unsigned int vectors_in_migration[NR_IRQS];

	vector = ia64_get_ivr();

	 irq_enter();
	 saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	 ia64_srlz_d();

	 /*
	  * Perform normal interrupt style processing
	  */
	while (vector != IA64_SPURIOUS_INT_VECTOR) {
		if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
			smp_local_flush_tlb();
			kstat_this_cpu.irqs[vector]++;
		} else if (unlikely(IS_RESCHEDULE(vector)))
			kstat_this_cpu.irqs[vector]++;
		else {
			struct pt_regs *old_regs = set_irq_regs(NULL);
			int irq = local_vector_to_irq(vector);

			ia64_setreg(_IA64_REG_CR_TPR, vector);
			ia64_srlz_d();

			/*
			 * Now try calling normal ia64_handle_irq as it would have got called
			 * from a real intr handler. Try passing null for pt_regs, hopefully
			 * it will work. I hope it works!.
			 * Probably could shared code.
			 */
			if (unlikely(irq < 0)) {
				printk(KERN_ERR "%s: Unexpected interrupt "
				       "vector %d on CPU %d not being mapped "
				       "to any IRQ!!\n", __func__, vector,
				       smp_processor_id());
			} else {
				vectors_in_migration[irq]=0;
				generic_handle_irq(irq);
			}
			set_irq_regs(old_regs);

			/*
			 * Disable interrupts and send EOI
			 */
			local_irq_disable();
			ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
		}
		ia64_eoi();
		vector = ia64_get_ivr();
	}
	irq_exit();
}
#endif


#ifdef CONFIG_SMP

static irqreturn_t dummy_handler (int irq, void *dev_id)
{
	BUG();
}

static struct irqaction ipi_irqaction = {
	.handler =	handle_IPI,
	.flags =	IRQF_DISABLED,
	.name =		"IPI"
};

static struct irqaction resched_irqaction = {
	.handler =	dummy_handler,
	.flags =	IRQF_DISABLED,
	.name =		"resched"
};

static struct irqaction tlb_irqaction = {
	.handler =	dummy_handler,
	.flags =	IRQF_DISABLED,
	.name =		"tlb_flush"
};

#endif

void
ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action)
{
	irq_desc_t *desc;
	unsigned int irq;

	irq = vec;
	BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
	desc = irq_desc + irq;
	desc->status |= IRQ_PER_CPU;
	desc->chip = &irq_type_ia64_lsapic;
	if (action)
		setup_irq(irq, action);
}

void __init
ia64_native_register_ipi(void)
{
#ifdef CONFIG_SMP
	register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
	register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
	register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
#endif
}

void __init
init_IRQ (void)
{
	ia64_register_ipi();
	register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
#ifdef CONFIG_SMP
#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG)
	if (vector_domain_type != VECTOR_DOMAIN_NONE) {
		BUG_ON(IA64_FIRST_DEVICE_VECTOR != IA64_IRQ_MOVE_VECTOR);
		IA64_FIRST_DEVICE_VECTOR++;
		register_percpu_irq(IA64_IRQ_MOVE_VECTOR, &irq_move_irqaction);
	}
#endif
#endif
#ifdef CONFIG_PERFMON
	pfm_init_percpu();
#endif
	platform_irq_init();
}

void
ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
{
	void __iomem *ipi_addr;
	unsigned long ipi_data;
	unsigned long phys_cpu_id;

	phys_cpu_id = cpu_physical_id(cpu);

	/*
	 * cpu number is in 8bit ID and 8bit EID
	 */

	ipi_data = (delivery_mode << 8) | (vector & 0xff);
	ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) | ((redirect & 1) << 3));

	writeq(ipi_data, ipi_addr);
}
Commit	Line	Data
1da177e4	1	/*
f30c2269	2	* linux/arch/ia64/kernel/irq_ia64.c
1da177e4 LT	3	*
	4	* Copyright (C) 1998-2001 Hewlett-Packard Co
	5	* Stephane Eranian <eranian@hpl.hp.com>
	6	* David Mosberger-Tang <davidm@hpl.hp.com>
	7	*
	8	* 6/10/99: Updated to bring in sync with x86 version to facilitate
	9	* support for SMP and different interrupt controllers.
	10	*
	11	* 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
	12	* PCI to vector allocation routine.
	13	* 04/14/2004 Ashok Raj <ashok.raj@intel.com>
	14	* Added CPU Hotplug handling for IPF.
	15	*/
	16
1da177e4 LT	17	#include <linux/module.h>
	18
	19	#include <linux/jiffies.h>
	20	#include <linux/errno.h>
	21	#include <linux/init.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/ioport.h>
	24	#include <linux/kernel_stat.h>
	25	#include <linux/slab.h>
	26	#include <linux/ptrace.h>
	27	#include <linux/random.h> /* for rand_initialize_irq() */
	28	#include <linux/signal.h>
	29	#include <linux/smp.h>
1da177e4 LT	30	#include <linux/threads.h>
1da177e4 LT	31	#include <linux/bitops.h>
b6cf2583	32	#include <linux/irq.h>
1da177e4 LT	33
	34	#include <asm/delay.h>
	35	#include <asm/intrinsics.h>
	36	#include <asm/io.h>
	37	#include <asm/hw_irq.h>
	38	#include <asm/machvec.h>
	39	#include <asm/pgtable.h>
	40	#include <asm/system.h>
3be44b9c	41	#include <asm/tlbflush.h>
1da177e4 LT	42
	43	#ifdef CONFIG_PERFMON
	44	# include <asm/perfmon.h>
	45	#endif
	46
	47	#define IRQ_DEBUG 0
	48
e1b30a39 YI	49	#define IRQ_VECTOR_UNASSIGNED (0)
	50
	51	#define IRQ_UNUSED (0)
	52	#define IRQ_USED (1)
	53	#define IRQ_RSVD (2)
	54
10083072 MM	55	/* These can be overridden in platform_irq_init */
	56	int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
	57	int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;
	58
1da177e4 LT	59	/* default base addr of IPI table */
	60	void __iomem ipi_base_addr = ((void __iomem )
	61	(__IA64_UNCACHED_OFFSET \| IA64_IPI_DEFAULT_BASE_ADDR));
	62
4994be1b YI	63	static cpumask_t vector_allocation_domain(int cpu);
4994be1b YI	64
1da177e4 LT	65	/*
	66	* Legacy IRQ to IA-64 vector translation table.
	67	*/
	68	__u8 isa_irq_to_vector_map[16] = {
	69	/* 8259 IRQ translation, first 16 entries */
	70	0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
	71	0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
	72	};
	73	EXPORT_SYMBOL(isa_irq_to_vector_map);
	74
e1b30a39 YI	75	DEFINE_SPINLOCK(vector_lock);
	76
	77	struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
4994be1b YI	78	[0 ... NR_IRQS - 1] = {
	79	.vector = IRQ_VECTOR_UNASSIGNED,
	80	.domain = CPU_MASK_NONE
	81	}
e1b30a39 YI	82	};
	83
	84	DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
17764d24	85	[0 ... IA64_NUM_VECTORS - 1] = -1
e1b30a39 YI	86	};
e1b30a39 YI	87
6ffbc823 KK	88	static cpumask_t vector_table[IA64_NUM_VECTORS] = {
6ffbc823 KK	89	[0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
4994be1b YI	90	};
4994be1b YI	91
e1b30a39 YI	92	static int irq_status[NR_IRQS] = {
	93	[0 ... NR_IRQS -1] = IRQ_UNUSED
	94	};
	95
	96	int check_irq_used(int irq)
	97	{
	98	if (irq_status[irq] == IRQ_USED)
	99	return 1;
	100
	101	return -1;
	102	}
	103
e1b30a39 YI	104	static inline int find_unassigned_irq(void)
	105	{
	106	int irq;
	107
	108	for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
	109	if (irq_status[irq] == IRQ_UNUSED)
	110	return irq;
	111	return -ENOSPC;
	112	}
	113
4994be1b	114	static inline int find_unassigned_vector(cpumask_t domain)
e1b30a39	115	{
4994be1b	116	cpumask_t mask;
6ffbc823	117	int pos, vector;
4994be1b YI	118
	119	cpus_and(mask, domain, cpu_online_map);
	120	if (cpus_empty(mask))
	121	return -EINVAL;
e1b30a39	122
4994be1b	123	for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
6ffbc823 KK	124	vector = IA64_FIRST_DEVICE_VECTOR + pos;
6ffbc823 KK	125	cpus_and(mask, domain, vector_table[vector]);
4994be1b YI	126	if (!cpus_empty(mask))
4994be1b YI	127	continue;
6ffbc823	128	return vector;
4994be1b	129	}
e1b30a39 YI	130	return -ENOSPC;
	131	}
	132
4994be1b	133	static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
e1b30a39	134	{
4994be1b	135	cpumask_t mask;
6ffbc823	136	int cpu;
4994be1b	137	struct irq_cfg *cfg = &irq_cfg[irq];
e1b30a39	138
6bde71ec KK	139	BUG_ON((unsigned)irq >= NR_IRQS);
	140	BUG_ON((unsigned)vector >= IA64_NUM_VECTORS);
	141
4994be1b YI	142	cpus_and(mask, domain, cpu_online_map);
	143	if (cpus_empty(mask))
	144	return -EINVAL;
	145	if ((cfg->vector == vector) && cpus_equal(cfg->domain, domain))
e1b30a39	146	return 0;
4994be1b	147	if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
e1b30a39	148	return -EBUSY;
4994be1b	149	for_each_cpu_mask(cpu, mask)
e1b30a39	150	per_cpu(vector_irq, cpu)[vector] = irq;
4994be1b YI	151	cfg->vector = vector;
4994be1b YI	152	cfg->domain = domain;
e1b30a39	153	irq_status[irq] = IRQ_USED;
6ffbc823	154	cpus_or(vector_table[vector], vector_table[vector], domain);
e1b30a39 YI	155	return 0;
	156	}
	157
4994be1b	158	int bind_irq_vector(int irq, int vector, cpumask_t domain)
e1b30a39 YI	159	{
	160	unsigned long flags;
	161	int ret;
	162
	163	spin_lock_irqsave(&vector_lock, flags);
4994be1b	164	ret = __bind_irq_vector(irq, vector, domain);
e1b30a39 YI	165	spin_unlock_irqrestore(&vector_lock, flags);
	166	return ret;
	167	}
	168
cd378f18	169	static void __clear_irq_vector(int irq)
e1b30a39	170	{
6ffbc823	171	int vector, cpu;
4994be1b YI	172	cpumask_t mask;
	173	cpumask_t domain;
	174	struct irq_cfg *cfg = &irq_cfg[irq];
e1b30a39	175
e1b30a39	176	BUG_ON((unsigned)irq >= NR_IRQS);
4994be1b YI	177	BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
	178	vector = cfg->vector;
	179	domain = cfg->domain;
	180	cpus_and(mask, cfg->domain, cpu_online_map);
	181	for_each_cpu_mask(cpu, mask)
17764d24	182	per_cpu(vector_irq, cpu)[vector] = -1;
4994be1b YI	183	cfg->vector = IRQ_VECTOR_UNASSIGNED;
4994be1b YI	184	cfg->domain = CPU_MASK_NONE;
e1b30a39	185	irq_status[irq] = IRQ_UNUSED;
6ffbc823	186	cpus_andnot(vector_table[vector], vector_table[vector], domain);
cd378f18 YI	187	}
	188
	189	static void clear_irq_vector(int irq)
	190	{
	191	unsigned long flags;
	192
	193	spin_lock_irqsave(&vector_lock, flags);
	194	__clear_irq_vector(irq);
e1b30a39 YI	195	spin_unlock_irqrestore(&vector_lock, flags);
e1b30a39 YI	196	}
1da177e4 LT	197
1da177e4 LT	198	int
85cbc503	199	ia64_native_assign_irq_vector (int irq)
1da177e4	200	{
e1b30a39	201	unsigned long flags;
4994be1b	202	int vector, cpu;
373167e8	203	cpumask_t domain = CPU_MASK_NONE;
4994be1b YI	204
4994be1b YI	205	vector = -ENOSPC;
e1b30a39	206
4994be1b	207	spin_lock_irqsave(&vector_lock, flags);
4994be1b YI	208	for_each_online_cpu(cpu) {
	209	domain = vector_allocation_domain(cpu);
	210	vector = find_unassigned_vector(domain);
	211	if (vector >= 0)
	212	break;
	213	}
e1b30a39 YI	214	if (vector < 0)
e1b30a39 YI	215	goto out;
8f5ad1a8 YI	216	if (irq == AUTO_ASSIGN)
8f5ad1a8 YI	217	irq = vector;
4994be1b	218	BUG_ON(__bind_irq_vector(irq, vector, domain));
e1b30a39	219	out:
4994be1b	220	spin_unlock_irqrestore(&vector_lock, flags);
1da177e4 LT	221	return vector;
	222	}
	223
	224	void
85cbc503	225	ia64_native_free_irq_vector (int vector)
1da177e4	226	{
e1b30a39 YI	227	if (vector < IA64_FIRST_DEVICE_VECTOR \|\|
e1b30a39 YI	228	vector > IA64_LAST_DEVICE_VECTOR)
1da177e4	229	return;
e1b30a39	230	clear_irq_vector(vector);
1da177e4 LT	231	}
1da177e4 LT	232
10083072 MM	233	int
	234	reserve_irq_vector (int vector)
	235	{
10083072 MM	236	if (vector < IA64_FIRST_DEVICE_VECTOR \|\|
	237	vector > IA64_LAST_DEVICE_VECTOR)
	238	return -EINVAL;
4994be1b	239	return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
e1b30a39	240	}
10083072	241
e1b30a39 YI	242	/*
	243	* Initialize vector_irq on a new cpu. This function must be called
	244	* with vector_lock held.
	245	*/
	246	void __setup_vector_irq(int cpu)
	247	{
	248	int irq, vector;
	249
	250	/* Clear vector_irq */
	251	for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
17764d24	252	per_cpu(vector_irq, cpu)[vector] = -1;
e1b30a39 YI	253	/* Mark the inuse vectors */
e1b30a39 YI	254	for (irq = 0; irq < NR_IRQS; ++irq) {
4994be1b YI	255	if (!cpu_isset(cpu, irq_cfg[irq].domain))
	256	continue;
	257	vector = irq_to_vector(irq);
	258	per_cpu(vector_irq, cpu)[vector] = irq;
e1b30a39 YI	259	}
	260	}
	261
e5bd762b	262	#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) \|\| defined(CONFIG_IA64_DIG))
a6cd6322 KK	263	#define IA64_IRQ_MOVE_VECTOR IA64_DEF_FIRST_DEVICE_VECTOR
a6cd6322 KK	264
d080d397 YI	265	static enum vector_domain_type {
	266	VECTOR_DOMAIN_NONE,
	267	VECTOR_DOMAIN_PERCPU
	268	} vector_domain_type = VECTOR_DOMAIN_NONE;
	269
4994be1b YI	270	static cpumask_t vector_allocation_domain(int cpu)
4994be1b YI	271	{
d080d397 YI	272	if (vector_domain_type == VECTOR_DOMAIN_PERCPU)
d080d397 YI	273	return cpumask_of_cpu(cpu);
4994be1b YI	274	return CPU_MASK_ALL;
	275	}
	276
a6cd6322 KK	277	static int __irq_prepare_move(int irq, int cpu)
	278	{
	279	struct irq_cfg *cfg = &irq_cfg[irq];
	280	int vector;
	281	cpumask_t domain;
	282
	283	if (cfg->move_in_progress \|\| cfg->move_cleanup_count)
	284	return -EBUSY;
	285	if (cfg->vector == IRQ_VECTOR_UNASSIGNED \|\| !cpu_online(cpu))
	286	return -EINVAL;
	287	if (cpu_isset(cpu, cfg->domain))
	288	return 0;
	289	domain = vector_allocation_domain(cpu);
	290	vector = find_unassigned_vector(domain);
	291	if (vector < 0)
	292	return -ENOSPC;
	293	cfg->move_in_progress = 1;
	294	cfg->old_domain = cfg->domain;
	295	cfg->vector = IRQ_VECTOR_UNASSIGNED;
	296	cfg->domain = CPU_MASK_NONE;
	297	BUG_ON(__bind_irq_vector(irq, vector, domain));
	298	return 0;
	299	}
	300
	301	int irq_prepare_move(int irq, int cpu)
	302	{
	303	unsigned long flags;
	304	int ret;
	305
	306	spin_lock_irqsave(&vector_lock, flags);
	307	ret = __irq_prepare_move(irq, cpu);
	308	spin_unlock_irqrestore(&vector_lock, flags);
	309	return ret;
	310	}
	311
	312	void irq_complete_move(unsigned irq)
	313	{
	314	struct irq_cfg *cfg = &irq_cfg[irq];
	315	cpumask_t cleanup_mask;
	316	int i;
	317
	318	if (likely(!cfg->move_in_progress))
	319	return;
	320
	321	if (unlikely(cpu_isset(smp_processor_id(), cfg->old_domain)))
	322	return;
	323
	324	cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
	325	cfg->move_cleanup_count = cpus_weight(cleanup_mask);
	326	for_each_cpu_mask(i, cleanup_mask)
	327	platform_send_ipi(i, IA64_IRQ_MOVE_VECTOR, IA64_IPI_DM_INT, 0);
	328	cfg->move_in_progress = 0;
	329	}
	330
	331	static irqreturn_t smp_irq_move_cleanup_interrupt(int irq, void *dev_id)
	332	{
	333	int me = smp_processor_id();
	334	ia64_vector vector;
	335	unsigned long flags;
	336
	337	for (vector = IA64_FIRST_DEVICE_VECTOR;
	338	vector < IA64_LAST_DEVICE_VECTOR; vector++) {
	339	int irq;
	340	struct irq_desc *desc;
341	struct irq_cfg *cfg;
342	irq = __get_cpu_var(vector_irq)[vector];
343	if (irq < 0)
344	continue;
345
346	desc = irq_desc + irq;
347	cfg = irq_cfg + irq;
348	spin_lock(&desc->lock);
349	if (!cfg->move_cleanup_count)
350	goto unlock;
351
352	if (!cpu_isset(me, cfg->old_domain))
353	goto unlock;
354
355	spin_lock_irqsave(&vector_lock, flags);
356	__get_cpu_var(vector_irq)[vector] = -1;
357	cpu_clear(me, vector_table[vector]);
358	spin_unlock_irqrestore(&vector_lock, flags);
359	cfg->move_cleanup_count--;
360	unlock:
361	spin_unlock(&desc->lock);
362	}
363	return IRQ_HANDLED;
364	}
365
366	static struct irqaction irq_move_irqaction = {
367	.handler = smp_irq_move_cleanup_interrupt,
368	.flags = IRQF_DISABLED,
369	.name = "irq_move"
370	};
371
d080d397 YI	372	static int __init parse_vector_domain(char *arg)
	373	{
	374	if (!arg)
	375	return -EINVAL;
	376	if (!strcmp(arg, "percpu")) {
	377	vector_domain_type = VECTOR_DOMAIN_PERCPU;
	378	no_int_routing = 1;
	379	}
074ff856	380	return 0;
d080d397 YI	381	}
	382	early_param("vector", parse_vector_domain);
	383	#else
	384	static cpumask_t vector_allocation_domain(int cpu)
	385	{
	386	return CPU_MASK_ALL;
	387	}
	388	#endif
	389
4994be1b	390
e1b30a39 YI	391	void destroy_and_reserve_irq(unsigned int irq)
e1b30a39 YI	392	{
216fcd29 KK	393	unsigned long flags;
216fcd29 KK	394
e1b30a39 YI	395	dynamic_irq_cleanup(irq);
e1b30a39 YI	396
216fcd29 KK	397	spin_lock_irqsave(&vector_lock, flags);
	398	__clear_irq_vector(irq);
	399	irq_status[irq] = IRQ_RSVD;
	400	spin_unlock_irqrestore(&vector_lock, flags);
10083072 MM	401	}
10083072 MM	402
b6cf2583 EB	403	/*
	404	* Dynamic irq allocate and deallocation for MSI
	405	*/
	406	int create_irq(void)
	407	{
e1b30a39	408	unsigned long flags;
4994be1b	409	int irq, vector, cpu;
373167e8	410	cpumask_t domain = CPU_MASK_NONE;
e1b30a39	411
4994be1b	412	irq = vector = -ENOSPC;
e1b30a39	413	spin_lock_irqsave(&vector_lock, flags);
4994be1b YI	414	for_each_online_cpu(cpu) {
	415	domain = vector_allocation_domain(cpu);
	416	vector = find_unassigned_vector(domain);
	417	if (vector >= 0)
	418	break;
	419	}
e1b30a39 YI	420	if (vector < 0)
	421	goto out;
	422	irq = find_unassigned_irq();
	423	if (irq < 0)
	424	goto out;
4994be1b	425	BUG_ON(__bind_irq_vector(irq, vector, domain));
e1b30a39 YI	426	out:
	427	spin_unlock_irqrestore(&vector_lock, flags);
	428	if (irq >= 0)
	429	dynamic_irq_init(irq);
	430	return irq;
b6cf2583 EB	431	}
	432
	433	void destroy_irq(unsigned int irq)
	434	{
	435	dynamic_irq_cleanup(irq);
e1b30a39	436	clear_irq_vector(irq);
b6cf2583 EB	437	}
b6cf2583 EB	438
1da177e4 LT	439	#ifdef CONFIG_SMP
1da177e4 LT	440	# define IS_RESCHEDULE(vec) (vec == IA64_IPI_RESCHEDULE)
3be44b9c	441	# define IS_LOCAL_TLB_FLUSH(vec) (vec == IA64_IPI_LOCAL_TLB_FLUSH)
1da177e4 LT	442	#else
1da177e4 LT	443	# define IS_RESCHEDULE(vec) (0)
3be44b9c	444	# define IS_LOCAL_TLB_FLUSH(vec) (0)
1da177e4 LT	445	#endif
	446	/*
	447	* That's where the IVT branches when we get an external
	448	* interrupt. This branches to the correct hardware IRQ handler via
	449	* function ptr.
	450	*/
	451	void
	452	ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
	453	{
7d12e780	454	struct pt_regs *old_regs = set_irq_regs(regs);
1da177e4 LT	455	unsigned long saved_tpr;
	456
	457	#if IRQ_DEBUG
	458	{
	459	unsigned long bsp, sp;
	460
	461	/*
	462	* Note: if the interrupt happened while executing in
	463	* the context switch routine (ia64_switch_to), we may
	464	* get a spurious stack overflow here. This is
	465	* because the register and the memory stack are not
	466	* switched atomically.
	467	*/
	468	bsp = ia64_getreg(_IA64_REG_AR_BSP);
	469	sp = ia64_getreg(_IA64_REG_SP);
	470
	471	if ((sp - bsp) < 1024) {
	472	static unsigned char count;
	473	static long last_time;
	474
5cf1f7ce	475	if (time_after(jiffies, last_time + 5 * HZ))
1da177e4 LT	476	count = 0;
	477	if (++count < 5) {
	478	last_time = jiffies;
	479	printk("ia64_handle_irq: DANGER: less than "
	480	"1KB of free stack space!!\n"
	481	"(bsp=0x%lx, sp=%lx)\n", bsp, sp);
	482	}
	483	}
	484	}
	485	#endif /* IRQ_DEBUG */
	486
	487	/*
	488	* Always set TPR to limit maximum interrupt nesting depth to
	489	* 16 (without this, it would be ~240, which could easily lead
	490	* to kernel stack overflows).
	491	*/
	492	irq_enter();
	493	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	494	ia64_srlz_d();
	495	while (vector != IA64_SPURIOUS_INT_VECTOR) {
3be44b9c JS	496	if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
	497	smp_local_flush_tlb();
	498	kstat_this_cpu.irqs[vector]++;
	499	} else if (unlikely(IS_RESCHEDULE(vector)))
	500	kstat_this_cpu.irqs[vector]++;
9b3377f9	501	else {
17764d24 KK	502	int irq = local_vector_to_irq(vector);
17764d24 KK	503
1da177e4 LT	504	ia64_setreg(_IA64_REG_CR_TPR, vector);
	505	ia64_srlz_d();
	506
17764d24 KK	507	if (unlikely(irq < 0)) {
	508	printk(KERN_ERR "%s: Unexpected interrupt "
	509	"vector %d on CPU %d is not mapped "
d4ed8084	510	"to any IRQ!\n", __func__, vector,
17764d24 KK	511	smp_processor_id());
	512	} else
	513	generic_handle_irq(irq);
1da177e4 LT	514
	515	/*
	516	* Disable interrupts and send EOI:
	517	*/
	518	local_irq_disable();
	519	ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
	520	}
	521	ia64_eoi();
	522	vector = ia64_get_ivr();
	523	}
	524	/*
	525	* This must be done after the ia64_eoi(). For example, the keyboard softirq
	526	* handler needs to be able to wait for further keyboard interrupts, which can't
	527	* come through until ia64_eoi() has been done.
	528	*/
	529	irq_exit();
7d12e780	530	set_irq_regs(old_regs);
1da177e4 LT	531	}
	532
	533	#ifdef CONFIG_HOTPLUG_CPU
	534	/*
	535	* This function emulates a interrupt processing when a cpu is about to be
	536	* brought down.
	537	*/
	538	void ia64_process_pending_intr(void)
	539	{
	540	ia64_vector vector;
	541	unsigned long saved_tpr;
	542	extern unsigned int vectors_in_migration[NR_IRQS];
	543
	544	vector = ia64_get_ivr();
	545
	546	irq_enter();
	547	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	548	ia64_srlz_d();
	549
	550	/*
	551	* Perform normal interrupt style processing
	552	*/
	553	while (vector != IA64_SPURIOUS_INT_VECTOR) {
3be44b9c JS	554	if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
	555	smp_local_flush_tlb();
	556	kstat_this_cpu.irqs[vector]++;
	557	} else if (unlikely(IS_RESCHEDULE(vector)))
	558	kstat_this_cpu.irqs[vector]++;
9b3377f9	559	else {
8c1addbc	560	struct pt_regs *old_regs = set_irq_regs(NULL);
17764d24	561	int irq = local_vector_to_irq(vector);
8c1addbc	562
1da177e4 LT	563	ia64_setreg(_IA64_REG_CR_TPR, vector);
	564	ia64_srlz_d();
	565
	566	/*
	567	* Now try calling normal ia64_handle_irq as it would have got called
	568	* from a real intr handler. Try passing null for pt_regs, hopefully
	569	* it will work. I hope it works!.
	570	* Probably could shared code.
	571	*/
17764d24 KK	572	if (unlikely(irq < 0)) {
	573	printk(KERN_ERR "%s: Unexpected interrupt "
	574	"vector %d on CPU %d not being mapped "
d4ed8084	575	"to any IRQ!!\n", __func__, vector,
17764d24 KK	576	smp_processor_id());
	577	} else {
	578	vectors_in_migration[irq]=0;
	579	generic_handle_irq(irq);
	580	}
8c1addbc	581	set_irq_regs(old_regs);
1da177e4 LT	582
	583	/*
	584	* Disable interrupts and send EOI
	585	*/
	586	local_irq_disable();
	587	ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
	588	}
	589	ia64_eoi();
	590	vector = ia64_get_ivr();
	591	}
	592	irq_exit();
	593	}
	594	#endif
	595
	596
	597	#ifdef CONFIG_SMP
1da177e4	598
9b3377f9 JS	599	static irqreturn_t dummy_handler (int irq, void *dev_id)
	600	{
	601	BUG();
	602	}
	603
1da177e4 LT	604	static struct irqaction ipi_irqaction = {
1da177e4 LT	605	.handler = handle_IPI,
121a4226	606	.flags = IRQF_DISABLED,
1da177e4 LT	607	.name = "IPI"
1da177e4 LT	608	};
9b3377f9 JS	609
	610	static struct irqaction resched_irqaction = {
	611	.handler = dummy_handler,
38515e90	612	.flags = IRQF_DISABLED,
9b3377f9 JS	613	.name = "resched"
9b3377f9 JS	614	};
3be44b9c JS	615
	616	static struct irqaction tlb_irqaction = {
	617	.handler = dummy_handler,
5329571b	618	.flags = IRQF_DISABLED,
3be44b9c JS	619	.name = "tlb_flush"
	620	};
	621
1da177e4 LT	622	#endif
	623
	624	void
85cbc503	625	ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action)
1da177e4 LT	626	{
	627	irq_desc_t *desc;
	628	unsigned int irq;
	629
e1b30a39	630	irq = vec;
4994be1b	631	BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
e1b30a39 YI	632	desc = irq_desc + irq;
	633	desc->status \|= IRQ_PER_CPU;
	634	desc->chip = &irq_type_ia64_lsapic;
	635	if (action)
	636	setup_irq(irq, action);
1da177e4 LT	637	}
	638
	639	void __init
85cbc503	640	ia64_native_register_ipi(void)
1da177e4	641	{
1da177e4 LT	642	#ifdef CONFIG_SMP
1da177e4 LT	643	register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
9b3377f9	644	register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
3be44b9c	645	register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
85cbc503 IY	646	#endif
	647	}
	648
	649	void __init
	650	init_IRQ (void)
	651	{
	652	ia64_register_ipi();
	653	register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
	654	#ifdef CONFIG_SMP
a6cd6322 KK	655	#if defined(CONFIG_IA64_GENERIC) \|\| defined(CONFIG_IA64_DIG)
	656	if (vector_domain_type != VECTOR_DOMAIN_NONE) {
	657	BUG_ON(IA64_FIRST_DEVICE_VECTOR != IA64_IRQ_MOVE_VECTOR);
	658	IA64_FIRST_DEVICE_VECTOR++;
	659	register_percpu_irq(IA64_IRQ_MOVE_VECTOR, &irq_move_irqaction);
	660	}
	661	#endif
1da177e4 LT	662	#endif
	663	#ifdef CONFIG_PERFMON
	664	pfm_init_percpu();
	665	#endif
	666	platform_irq_init();
	667	}
	668
	669	void
	670	ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
	671	{
	672	void __iomem *ipi_addr;
	673	unsigned long ipi_data;
	674	unsigned long phys_cpu_id;
	675
1da177e4	676	phys_cpu_id = cpu_physical_id(cpu);
1da177e4 LT	677
	678	/*
	679	* cpu number is in 8bit ID and 8bit EID
	680	*/
	681
	682	ipi_data = (delivery_mode << 8) \| (vector & 0xff);
	683	ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) \| ((redirect & 1) << 3));
	684
	685	writeq(ipi_data, ipi_addr);
	686	}