Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * I/O SAPIC support. | |
3 | * | |
4 | * Copyright (C) 1999 Intel Corp. | |
5 | * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com> | |
6 | * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com> | |
7 | * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co. | |
8 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
9 | * Copyright (C) 1999 VA Linux Systems | |
10 | * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com> | |
11 | * | |
46cba3dc ST |
12 | * 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O |
13 | * APIC code. In particular, we now have separate | |
14 | * handlers for edge and level triggered | |
15 | * interrupts. | |
16 | * 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector | |
17 | * allocation PCI to vector mapping, shared PCI | |
18 | * interrupts. | |
19 | * 00/10/27 D. Mosberger Document things a bit more to make them more | |
20 | * understandable. Clean up much of the old | |
21 | * IOSAPIC cruft. | |
22 | * 01/07/27 J.I. Lee PCI irq routing, Platform/Legacy interrupts | |
23 | * and fixes for ACPI S5(SoftOff) support. | |
1da177e4 | 24 | * 02/01/23 J.I. Lee iosapic pgm fixes for PCI irq routing from _PRT |
46cba3dc ST |
25 | * 02/01/07 E. Focht <efocht@ess.nec.de> Redirectable interrupt |
26 | * vectors in iosapic_set_affinity(), | |
27 | * initializations for /proc/irq/#/smp_affinity | |
1da177e4 LT |
28 | * 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing. |
29 | * 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq | |
46cba3dc ST |
30 | * 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to |
31 | * IOSAPIC mapping error | |
1da177e4 | 32 | * 02/07/29 T. Kochi Allocate interrupt vectors dynamically |
46cba3dc ST |
33 | * 02/08/04 T. Kochi Cleaned up terminology (irq, global system |
34 | * interrupt, vector, etc.) | |
35 | * 02/09/20 D. Mosberger Simplified by taking advantage of ACPI's | |
36 | * pci_irq code. | |
1da177e4 | 37 | * 03/02/19 B. Helgaas Make pcat_compat system-wide, not per-IOSAPIC. |
46cba3dc ST |
38 | * Remove iosapic_address & gsi_base from |
39 | * external interfaces. Rationalize | |
40 | * __init/__devinit attributes. | |
1da177e4 | 41 | * 04/12/04 Ashok Raj <ashok.raj@intel.com> Intel Corporation 2004 |
46cba3dc ST |
42 | * Updated to work with irq migration necessary |
43 | * for CPU Hotplug | |
1da177e4 LT |
44 | */ |
45 | /* | |
46cba3dc ST |
46 | * Here is what the interrupt logic between a PCI device and the kernel looks |
47 | * like: | |
1da177e4 | 48 | * |
46cba3dc ST |
49 | * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC, |
50 | * INTD). The device is uniquely identified by its bus-, and slot-number | |
51 | * (the function number does not matter here because all functions share | |
52 | * the same interrupt lines). | |
1da177e4 | 53 | * |
46cba3dc ST |
54 | * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC |
55 | * controller. Multiple interrupt lines may have to share the same | |
56 | * IOSAPIC pin (if they're level triggered and use the same polarity). | |
57 | * Each interrupt line has a unique Global System Interrupt (GSI) number | |
58 | * which can be calculated as the sum of the controller's base GSI number | |
59 | * and the IOSAPIC pin number to which the line connects. | |
1da177e4 | 60 | * |
46cba3dc ST |
61 | * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the |
62 | * IOSAPIC pin into the IA-64 interrupt vector. This interrupt vector is then | |
63 | * sent to the CPU. | |
1da177e4 | 64 | * |
46cba3dc ST |
65 | * (4) The kernel recognizes an interrupt as an IRQ. The IRQ interface is |
66 | * used as architecture-independent interrupt handling mechanism in Linux. | |
67 | * As an IRQ is a number, we have to have | |
68 | * IA-64 interrupt vector number <-> IRQ number mapping. On smaller | |
69 | * systems, we use one-to-one mapping between IA-64 vector and IRQ. A | |
70 | * platform can implement platform_irq_to_vector(irq) and | |
1da177e4 LT |
71 | * platform_local_vector_to_irq(vector) APIs to differentiate the mapping. |
72 | * Please see also include/asm-ia64/hw_irq.h for those APIs. | |
73 | * | |
74 | * To sum up, there are three levels of mappings involved: | |
75 | * | |
76 | * PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ | |
77 | * | |
46cba3dc ST |
78 | * Note: The term "IRQ" is loosely used everywhere in Linux kernel to |
79 | * describeinterrupts. Now we use "IRQ" only for Linux IRQ's. ISA IRQ | |
80 | * (isa_irq) is the only exception in this source code. | |
1da177e4 | 81 | */ |
1da177e4 LT |
82 | |
83 | #include <linux/acpi.h> | |
84 | #include <linux/init.h> | |
85 | #include <linux/irq.h> | |
86 | #include <linux/kernel.h> | |
87 | #include <linux/list.h> | |
88 | #include <linux/pci.h> | |
89 | #include <linux/smp.h> | |
1da177e4 | 90 | #include <linux/string.h> |
24eeb568 | 91 | #include <linux/bootmem.h> |
1da177e4 LT |
92 | |
93 | #include <asm/delay.h> | |
94 | #include <asm/hw_irq.h> | |
95 | #include <asm/io.h> | |
96 | #include <asm/iosapic.h> | |
97 | #include <asm/machvec.h> | |
98 | #include <asm/processor.h> | |
99 | #include <asm/ptrace.h> | |
100 | #include <asm/system.h> | |
101 | ||
1da177e4 LT |
102 | #undef DEBUG_INTERRUPT_ROUTING |
103 | ||
104 | #ifdef DEBUG_INTERRUPT_ROUTING | |
105 | #define DBG(fmt...) printk(fmt) | |
106 | #else | |
107 | #define DBG(fmt...) | |
108 | #endif | |
109 | ||
46cba3dc ST |
110 | #define NR_PREALLOCATE_RTE_ENTRIES \ |
111 | (PAGE_SIZE / sizeof(struct iosapic_rte_info)) | |
24eeb568 KK |
112 | #define RTE_PREALLOCATED (1) |
113 | ||
1da177e4 LT |
114 | static DEFINE_SPINLOCK(iosapic_lock); |
115 | ||
46cba3dc ST |
116 | /* |
117 | * These tables map IA-64 vectors to the IOSAPIC pin that generates this | |
118 | * vector. | |
119 | */ | |
c5e3f9e5 YI |
120 | static struct iosapic { |
121 | char __iomem *addr; /* base address of IOSAPIC */ | |
122 | unsigned int gsi_base; /* GSI base */ | |
123 | unsigned short num_rte; /* # of RTEs on this IOSAPIC */ | |
124 | int rtes_inuse; /* # of RTEs in use on this IOSAPIC */ | |
125 | #ifdef CONFIG_NUMA | |
126 | unsigned short node; /* numa node association via pxm */ | |
127 | #endif | |
c1726d6f | 128 | spinlock_t lock; /* lock for indirect reg access */ |
c5e3f9e5 | 129 | } iosapic_lists[NR_IOSAPICS]; |
1da177e4 | 130 | |
24eeb568 | 131 | struct iosapic_rte_info { |
c5e3f9e5 | 132 | struct list_head rte_list; /* RTEs sharing the same vector */ |
24eeb568 KK |
133 | char rte_index; /* IOSAPIC RTE index */ |
134 | int refcnt; /* reference counter */ | |
135 | unsigned int flags; /* flags */ | |
c5e3f9e5 | 136 | struct iosapic *iosapic; |
24eeb568 KK |
137 | } ____cacheline_aligned; |
138 | ||
139 | static struct iosapic_intr_info { | |
46cba3dc ST |
140 | struct list_head rtes; /* RTEs using this vector (empty => |
141 | * not an IOSAPIC interrupt) */ | |
24eeb568 | 142 | int count; /* # of RTEs that shares this vector */ |
46cba3dc ST |
143 | u32 low32; /* current value of low word of |
144 | * Redirection table entry */ | |
24eeb568 | 145 | unsigned int dest; /* destination CPU physical ID */ |
1da177e4 | 146 | unsigned char dmode : 3; /* delivery mode (see iosapic.h) */ |
46cba3dc ST |
147 | unsigned char polarity: 1; /* interrupt polarity |
148 | * (see iosapic.h) */ | |
1da177e4 | 149 | unsigned char trigger : 1; /* trigger mode (see iosapic.h) */ |
1da177e4 LT |
150 | } iosapic_intr_info[IA64_NUM_VECTORS]; |
151 | ||
0e888adc | 152 | static unsigned char pcat_compat __devinitdata; /* 8259 compatibility flag */ |
1da177e4 | 153 | |
24eeb568 KK |
154 | static int iosapic_kmalloc_ok; |
155 | static LIST_HEAD(free_rte_list); | |
1da177e4 | 156 | |
c1726d6f YI |
157 | static inline void |
158 | iosapic_write(struct iosapic *iosapic, unsigned int reg, u32 val) | |
159 | { | |
160 | unsigned long flags; | |
161 | ||
162 | spin_lock_irqsave(&iosapic->lock, flags); | |
163 | __iosapic_write(iosapic->addr, reg, val); | |
164 | spin_unlock_irqrestore(&iosapic->lock, flags); | |
165 | } | |
166 | ||
1da177e4 LT |
167 | /* |
168 | * Find an IOSAPIC associated with a GSI | |
169 | */ | |
170 | static inline int | |
171 | find_iosapic (unsigned int gsi) | |
172 | { | |
173 | int i; | |
174 | ||
0e888adc | 175 | for (i = 0; i < NR_IOSAPICS; i++) { |
46cba3dc ST |
176 | if ((unsigned) (gsi - iosapic_lists[i].gsi_base) < |
177 | iosapic_lists[i].num_rte) | |
1da177e4 LT |
178 | return i; |
179 | } | |
180 | ||
181 | return -1; | |
182 | } | |
183 | ||
184 | static inline int | |
185 | _gsi_to_vector (unsigned int gsi) | |
186 | { | |
187 | struct iosapic_intr_info *info; | |
24eeb568 | 188 | struct iosapic_rte_info *rte; |
1da177e4 | 189 | |
46cba3dc ST |
190 | for (info = iosapic_intr_info; info < |
191 | iosapic_intr_info + IA64_NUM_VECTORS; ++info) | |
24eeb568 | 192 | list_for_each_entry(rte, &info->rtes, rte_list) |
c5e3f9e5 | 193 | if (rte->iosapic->gsi_base + rte->rte_index == gsi) |
24eeb568 | 194 | return info - iosapic_intr_info; |
1da177e4 LT |
195 | return -1; |
196 | } | |
197 | ||
198 | /* | |
199 | * Translate GSI number to the corresponding IA-64 interrupt vector. If no | |
200 | * entry exists, return -1. | |
201 | */ | |
202 | inline int | |
203 | gsi_to_vector (unsigned int gsi) | |
204 | { | |
205 | return _gsi_to_vector(gsi); | |
206 | } | |
207 | ||
208 | int | |
209 | gsi_to_irq (unsigned int gsi) | |
210 | { | |
24eeb568 KK |
211 | unsigned long flags; |
212 | int irq; | |
1da177e4 | 213 | /* |
46cba3dc ST |
214 | * XXX fix me: this assumes an identity mapping between IA-64 vector |
215 | * and Linux irq numbers... | |
1da177e4 | 216 | */ |
24eeb568 | 217 | spin_lock_irqsave(&iosapic_lock, flags); |
e3a8f7b8 | 218 | irq = _gsi_to_vector(gsi); |
24eeb568 KK |
219 | spin_unlock_irqrestore(&iosapic_lock, flags); |
220 | ||
221 | return irq; | |
222 | } | |
223 | ||
46cba3dc ST |
224 | static struct iosapic_rte_info *gsi_vector_to_rte(unsigned int gsi, |
225 | unsigned int vec) | |
24eeb568 KK |
226 | { |
227 | struct iosapic_rte_info *rte; | |
228 | ||
229 | list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) | |
c5e3f9e5 | 230 | if (rte->iosapic->gsi_base + rte->rte_index == gsi) |
24eeb568 KK |
231 | return rte; |
232 | return NULL; | |
1da177e4 LT |
233 | } |
234 | ||
235 | static void | |
24eeb568 | 236 | set_rte (unsigned int gsi, unsigned int vector, unsigned int dest, int mask) |
1da177e4 LT |
237 | { |
238 | unsigned long pol, trigger, dmode; | |
239 | u32 low32, high32; | |
1da177e4 LT |
240 | int rte_index; |
241 | char redir; | |
24eeb568 | 242 | struct iosapic_rte_info *rte; |
1da177e4 LT |
243 | |
244 | DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest); | |
245 | ||
24eeb568 KK |
246 | rte = gsi_vector_to_rte(gsi, vector); |
247 | if (!rte) | |
1da177e4 LT |
248 | return; /* not an IOSAPIC interrupt */ |
249 | ||
24eeb568 | 250 | rte_index = rte->rte_index; |
1da177e4 LT |
251 | pol = iosapic_intr_info[vector].polarity; |
252 | trigger = iosapic_intr_info[vector].trigger; | |
253 | dmode = iosapic_intr_info[vector].dmode; | |
1da177e4 LT |
254 | |
255 | redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0; | |
256 | ||
257 | #ifdef CONFIG_SMP | |
258 | { | |
259 | unsigned int irq; | |
260 | ||
261 | for (irq = 0; irq < NR_IRQS; ++irq) | |
262 | if (irq_to_vector(irq) == vector) { | |
46cba3dc ST |
263 | set_irq_affinity_info(irq, |
264 | (int)(dest & 0xffff), | |
265 | redir); | |
1da177e4 LT |
266 | break; |
267 | } | |
268 | } | |
269 | #endif | |
270 | ||
271 | low32 = ((pol << IOSAPIC_POLARITY_SHIFT) | | |
272 | (trigger << IOSAPIC_TRIGGER_SHIFT) | | |
273 | (dmode << IOSAPIC_DELIVERY_SHIFT) | | |
274 | ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) | | |
275 | vector); | |
276 | ||
277 | /* dest contains both id and eid */ | |
278 | high32 = (dest << IOSAPIC_DEST_SHIFT); | |
279 | ||
c1726d6f YI |
280 | iosapic_write(rte->iosapic, IOSAPIC_RTE_HIGH(rte_index), high32); |
281 | iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32); | |
1da177e4 | 282 | iosapic_intr_info[vector].low32 = low32; |
24eeb568 | 283 | iosapic_intr_info[vector].dest = dest; |
1da177e4 LT |
284 | } |
285 | ||
286 | static void | |
46cba3dc | 287 | nop (unsigned int irq) |
1da177e4 LT |
288 | { |
289 | /* do nothing... */ | |
290 | } | |
291 | ||
a7956113 ZN |
292 | |
293 | #ifdef CONFIG_KEXEC | |
294 | void | |
295 | kexec_disable_iosapic(void) | |
296 | { | |
297 | struct iosapic_intr_info *info; | |
298 | struct iosapic_rte_info *rte; | |
299 | u8 vec = 0; | |
300 | for (info = iosapic_intr_info; info < | |
301 | iosapic_intr_info + IA64_NUM_VECTORS; ++info, ++vec) { | |
302 | list_for_each_entry(rte, &info->rtes, | |
303 | rte_list) { | |
c1726d6f | 304 | iosapic_write(rte->iosapic, |
a7956113 ZN |
305 | IOSAPIC_RTE_LOW(rte->rte_index), |
306 | IOSAPIC_MASK|vec); | |
c5e3f9e5 | 307 | iosapic_eoi(rte->iosapic->addr, vec); |
a7956113 ZN |
308 | } |
309 | } | |
310 | } | |
311 | #endif | |
312 | ||
1da177e4 LT |
313 | static void |
314 | mask_irq (unsigned int irq) | |
315 | { | |
1da177e4 LT |
316 | u32 low32; |
317 | int rte_index; | |
318 | ia64_vector vec = irq_to_vector(irq); | |
24eeb568 | 319 | struct iosapic_rte_info *rte; |
1da177e4 | 320 | |
24eeb568 | 321 | if (list_empty(&iosapic_intr_info[vec].rtes)) |
1da177e4 LT |
322 | return; /* not an IOSAPIC interrupt! */ |
323 | ||
e3a8f7b8 YI |
324 | /* set only the mask bit */ |
325 | low32 = iosapic_intr_info[vec].low32 |= IOSAPIC_MASK; | |
326 | list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) { | |
e3a8f7b8 | 327 | rte_index = rte->rte_index; |
c1726d6f | 328 | iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32); |
1da177e4 | 329 | } |
1da177e4 LT |
330 | } |
331 | ||
332 | static void | |
333 | unmask_irq (unsigned int irq) | |
334 | { | |
1da177e4 LT |
335 | u32 low32; |
336 | int rte_index; | |
337 | ia64_vector vec = irq_to_vector(irq); | |
24eeb568 | 338 | struct iosapic_rte_info *rte; |
1da177e4 | 339 | |
24eeb568 | 340 | if (list_empty(&iosapic_intr_info[vec].rtes)) |
1da177e4 LT |
341 | return; /* not an IOSAPIC interrupt! */ |
342 | ||
e3a8f7b8 YI |
343 | low32 = iosapic_intr_info[vec].low32 &= ~IOSAPIC_MASK; |
344 | list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) { | |
e3a8f7b8 | 345 | rte_index = rte->rte_index; |
c1726d6f | 346 | iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32); |
1da177e4 | 347 | } |
1da177e4 LT |
348 | } |
349 | ||
350 | ||
351 | static void | |
352 | iosapic_set_affinity (unsigned int irq, cpumask_t mask) | |
353 | { | |
354 | #ifdef CONFIG_SMP | |
1da177e4 LT |
355 | u32 high32, low32; |
356 | int dest, rte_index; | |
1da177e4 LT |
357 | int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0; |
358 | ia64_vector vec; | |
24eeb568 | 359 | struct iosapic_rte_info *rte; |
c1726d6f | 360 | struct iosapic *iosapic; |
1da177e4 LT |
361 | |
362 | irq &= (~IA64_IRQ_REDIRECTED); | |
363 | vec = irq_to_vector(irq); | |
364 | ||
365 | if (cpus_empty(mask)) | |
366 | return; | |
367 | ||
368 | dest = cpu_physical_id(first_cpu(mask)); | |
369 | ||
24eeb568 | 370 | if (list_empty(&iosapic_intr_info[vec].rtes)) |
1da177e4 LT |
371 | return; /* not an IOSAPIC interrupt */ |
372 | ||
373 | set_irq_affinity_info(irq, dest, redir); | |
374 | ||
375 | /* dest contains both id and eid */ | |
376 | high32 = dest << IOSAPIC_DEST_SHIFT; | |
377 | ||
e3a8f7b8 YI |
378 | low32 = iosapic_intr_info[vec].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT); |
379 | if (redir) | |
380 | /* change delivery mode to lowest priority */ | |
381 | low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT); | |
382 | else | |
383 | /* change delivery mode to fixed */ | |
384 | low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT); | |
385 | ||
386 | iosapic_intr_info[vec].low32 = low32; | |
387 | iosapic_intr_info[vec].dest = dest; | |
388 | list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) { | |
c1726d6f | 389 | iosapic = rte->iosapic; |
e3a8f7b8 | 390 | rte_index = rte->rte_index; |
c1726d6f YI |
391 | iosapic_write(iosapic, IOSAPIC_RTE_HIGH(rte_index), high32); |
392 | iosapic_write(iosapic, IOSAPIC_RTE_LOW(rte_index), low32); | |
1da177e4 | 393 | } |
1da177e4 LT |
394 | #endif |
395 | } | |
396 | ||
397 | /* | |
398 | * Handlers for level-triggered interrupts. | |
399 | */ | |
400 | ||
401 | static unsigned int | |
402 | iosapic_startup_level_irq (unsigned int irq) | |
403 | { | |
404 | unmask_irq(irq); | |
405 | return 0; | |
406 | } | |
407 | ||
408 | static void | |
409 | iosapic_end_level_irq (unsigned int irq) | |
410 | { | |
411 | ia64_vector vec = irq_to_vector(irq); | |
24eeb568 | 412 | struct iosapic_rte_info *rte; |
1da177e4 | 413 | |
41503def | 414 | move_native_irq(irq); |
24eeb568 | 415 | list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) |
c5e3f9e5 | 416 | iosapic_eoi(rte->iosapic->addr, vec); |
1da177e4 LT |
417 | } |
418 | ||
419 | #define iosapic_shutdown_level_irq mask_irq | |
420 | #define iosapic_enable_level_irq unmask_irq | |
421 | #define iosapic_disable_level_irq mask_irq | |
422 | #define iosapic_ack_level_irq nop | |
423 | ||
e253eb0c | 424 | struct irq_chip irq_type_iosapic_level = { |
06344db3 | 425 | .name = "IO-SAPIC-level", |
1da177e4 LT |
426 | .startup = iosapic_startup_level_irq, |
427 | .shutdown = iosapic_shutdown_level_irq, | |
428 | .enable = iosapic_enable_level_irq, | |
429 | .disable = iosapic_disable_level_irq, | |
430 | .ack = iosapic_ack_level_irq, | |
431 | .end = iosapic_end_level_irq, | |
e253eb0c KH |
432 | .mask = mask_irq, |
433 | .unmask = unmask_irq, | |
1da177e4 LT |
434 | .set_affinity = iosapic_set_affinity |
435 | }; | |
436 | ||
437 | /* | |
438 | * Handlers for edge-triggered interrupts. | |
439 | */ | |
440 | ||
441 | static unsigned int | |
442 | iosapic_startup_edge_irq (unsigned int irq) | |
443 | { | |
444 | unmask_irq(irq); | |
445 | /* | |
446 | * IOSAPIC simply drops interrupts pended while the | |
447 | * corresponding pin was masked, so we can't know if an | |
448 | * interrupt is pending already. Let's hope not... | |
449 | */ | |
450 | return 0; | |
451 | } | |
452 | ||
453 | static void | |
454 | iosapic_ack_edge_irq (unsigned int irq) | |
455 | { | |
a8553acd | 456 | irq_desc_t *idesc = irq_desc + irq; |
1da177e4 | 457 | |
41503def | 458 | move_native_irq(irq); |
1da177e4 LT |
459 | /* |
460 | * Once we have recorded IRQ_PENDING already, we can mask the | |
461 | * interrupt for real. This prevents IRQ storms from unhandled | |
462 | * devices. | |
463 | */ | |
46cba3dc ST |
464 | if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) == |
465 | (IRQ_PENDING|IRQ_DISABLED)) | |
1da177e4 LT |
466 | mask_irq(irq); |
467 | } | |
468 | ||
469 | #define iosapic_enable_edge_irq unmask_irq | |
470 | #define iosapic_disable_edge_irq nop | |
471 | #define iosapic_end_edge_irq nop | |
472 | ||
e253eb0c | 473 | struct irq_chip irq_type_iosapic_edge = { |
06344db3 | 474 | .name = "IO-SAPIC-edge", |
1da177e4 LT |
475 | .startup = iosapic_startup_edge_irq, |
476 | .shutdown = iosapic_disable_edge_irq, | |
477 | .enable = iosapic_enable_edge_irq, | |
478 | .disable = iosapic_disable_edge_irq, | |
479 | .ack = iosapic_ack_edge_irq, | |
480 | .end = iosapic_end_edge_irq, | |
e253eb0c KH |
481 | .mask = mask_irq, |
482 | .unmask = unmask_irq, | |
1da177e4 LT |
483 | .set_affinity = iosapic_set_affinity |
484 | }; | |
485 | ||
486 | unsigned int | |
487 | iosapic_version (char __iomem *addr) | |
488 | { | |
489 | /* | |
490 | * IOSAPIC Version Register return 32 bit structure like: | |
491 | * { | |
492 | * unsigned int version : 8; | |
493 | * unsigned int reserved1 : 8; | |
494 | * unsigned int max_redir : 8; | |
495 | * unsigned int reserved2 : 8; | |
496 | * } | |
497 | */ | |
c1726d6f | 498 | return __iosapic_read(addr, IOSAPIC_VERSION); |
1da177e4 LT |
499 | } |
500 | ||
46cba3dc ST |
501 | static int iosapic_find_sharable_vector (unsigned long trigger, |
502 | unsigned long pol) | |
24eeb568 | 503 | { |
40598cbe | 504 | int i, vector = -ENOSPC, min_count = -1; |
24eeb568 KK |
505 | struct iosapic_intr_info *info; |
506 | ||
507 | /* | |
508 | * shared vectors for edge-triggered interrupts are not | |
509 | * supported yet | |
510 | */ | |
511 | if (trigger == IOSAPIC_EDGE) | |
40598cbe | 512 | return -EINVAL; |
24eeb568 KK |
513 | |
514 | for (i = IA64_FIRST_DEVICE_VECTOR; i <= IA64_LAST_DEVICE_VECTOR; i++) { | |
515 | info = &iosapic_intr_info[i]; | |
516 | if (info->trigger == trigger && info->polarity == pol && | |
46cba3dc ST |
517 | (info->dmode == IOSAPIC_FIXED || info->dmode == |
518 | IOSAPIC_LOWEST_PRIORITY)) { | |
24eeb568 KK |
519 | if (min_count == -1 || info->count < min_count) { |
520 | vector = i; | |
521 | min_count = info->count; | |
522 | } | |
523 | } | |
524 | } | |
24eeb568 KK |
525 | |
526 | return vector; | |
527 | } | |
528 | ||
1da177e4 LT |
529 | /* |
530 | * if the given vector is already owned by other, | |
531 | * assign a new vector for the other and make the vector available | |
532 | */ | |
533 | static void __init | |
534 | iosapic_reassign_vector (int vector) | |
535 | { | |
eb21ab24 | 536 | int irq, new_vector; |
1da177e4 | 537 | |
24eeb568 | 538 | if (!list_empty(&iosapic_intr_info[vector].rtes)) { |
eb21ab24 YI |
539 | irq = create_irq(); |
540 | if (irq < 0) | |
3b5cc090 | 541 | panic("%s: out of interrupt vectors!\n", __FUNCTION__); |
eb21ab24 | 542 | new_vector = irq_to_vector(irq); |
46cba3dc ST |
543 | printk(KERN_INFO "Reassigning vector %d to %d\n", |
544 | vector, new_vector); | |
1da177e4 LT |
545 | memcpy(&iosapic_intr_info[new_vector], &iosapic_intr_info[vector], |
546 | sizeof(struct iosapic_intr_info)); | |
24eeb568 | 547 | INIT_LIST_HEAD(&iosapic_intr_info[new_vector].rtes); |
46cba3dc ST |
548 | list_move(iosapic_intr_info[vector].rtes.next, |
549 | &iosapic_intr_info[new_vector].rtes); | |
550 | memset(&iosapic_intr_info[vector], 0, | |
551 | sizeof(struct iosapic_intr_info)); | |
24eeb568 KK |
552 | iosapic_intr_info[vector].low32 = IOSAPIC_MASK; |
553 | INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes); | |
1da177e4 LT |
554 | } |
555 | } | |
556 | ||
24eeb568 KK |
557 | static struct iosapic_rte_info *iosapic_alloc_rte (void) |
558 | { | |
559 | int i; | |
560 | struct iosapic_rte_info *rte; | |
561 | int preallocated = 0; | |
562 | ||
563 | if (!iosapic_kmalloc_ok && list_empty(&free_rte_list)) { | |
46cba3dc ST |
564 | rte = alloc_bootmem(sizeof(struct iosapic_rte_info) * |
565 | NR_PREALLOCATE_RTE_ENTRIES); | |
24eeb568 KK |
566 | if (!rte) |
567 | return NULL; | |
568 | for (i = 0; i < NR_PREALLOCATE_RTE_ENTRIES; i++, rte++) | |
569 | list_add(&rte->rte_list, &free_rte_list); | |
570 | } | |
571 | ||
572 | if (!list_empty(&free_rte_list)) { | |
46cba3dc ST |
573 | rte = list_entry(free_rte_list.next, struct iosapic_rte_info, |
574 | rte_list); | |
24eeb568 KK |
575 | list_del(&rte->rte_list); |
576 | preallocated++; | |
577 | } else { | |
578 | rte = kmalloc(sizeof(struct iosapic_rte_info), GFP_ATOMIC); | |
579 | if (!rte) | |
580 | return NULL; | |
581 | } | |
582 | ||
583 | memset(rte, 0, sizeof(struct iosapic_rte_info)); | |
584 | if (preallocated) | |
585 | rte->flags |= RTE_PREALLOCATED; | |
586 | ||
587 | return rte; | |
588 | } | |
589 | ||
590 | static void iosapic_free_rte (struct iosapic_rte_info *rte) | |
591 | { | |
592 | if (rte->flags & RTE_PREALLOCATED) | |
593 | list_add_tail(&rte->rte_list, &free_rte_list); | |
594 | else | |
595 | kfree(rte); | |
596 | } | |
597 | ||
598 | static inline int vector_is_shared (int vector) | |
599 | { | |
600 | return (iosapic_intr_info[vector].count > 1); | |
601 | } | |
602 | ||
14454a1b | 603 | static int |
1da177e4 LT |
604 | register_intr (unsigned int gsi, int vector, unsigned char delivery, |
605 | unsigned long polarity, unsigned long trigger) | |
606 | { | |
607 | irq_desc_t *idesc; | |
608 | struct hw_interrupt_type *irq_type; | |
1da177e4 | 609 | int index; |
24eeb568 | 610 | struct iosapic_rte_info *rte; |
1da177e4 LT |
611 | |
612 | index = find_iosapic(gsi); | |
613 | if (index < 0) { | |
46cba3dc ST |
614 | printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n", |
615 | __FUNCTION__, gsi); | |
14454a1b | 616 | return -ENODEV; |
1da177e4 LT |
617 | } |
618 | ||
24eeb568 KK |
619 | rte = gsi_vector_to_rte(gsi, vector); |
620 | if (!rte) { | |
621 | rte = iosapic_alloc_rte(); | |
622 | if (!rte) { | |
46cba3dc ST |
623 | printk(KERN_WARNING "%s: cannot allocate memory\n", |
624 | __FUNCTION__); | |
14454a1b | 625 | return -ENOMEM; |
24eeb568 KK |
626 | } |
627 | ||
c5e3f9e5 YI |
628 | rte->iosapic = &iosapic_lists[index]; |
629 | rte->rte_index = gsi - rte->iosapic->gsi_base; | |
24eeb568 KK |
630 | rte->refcnt++; |
631 | list_add_tail(&rte->rte_list, &iosapic_intr_info[vector].rtes); | |
632 | iosapic_intr_info[vector].count++; | |
0e888adc | 633 | iosapic_lists[index].rtes_inuse++; |
24eeb568 KK |
634 | } |
635 | else if (vector_is_shared(vector)) { | |
636 | struct iosapic_intr_info *info = &iosapic_intr_info[vector]; | |
637 | if (info->trigger != trigger || info->polarity != polarity) { | |
46cba3dc ST |
638 | printk (KERN_WARNING |
639 | "%s: cannot override the interrupt\n", | |
640 | __FUNCTION__); | |
14454a1b | 641 | return -EINVAL; |
24eeb568 KK |
642 | } |
643 | } | |
644 | ||
1da177e4 LT |
645 | iosapic_intr_info[vector].polarity = polarity; |
646 | iosapic_intr_info[vector].dmode = delivery; | |
1da177e4 | 647 | iosapic_intr_info[vector].trigger = trigger; |
1da177e4 LT |
648 | |
649 | if (trigger == IOSAPIC_EDGE) | |
650 | irq_type = &irq_type_iosapic_edge; | |
651 | else | |
652 | irq_type = &irq_type_iosapic_level; | |
653 | ||
a8553acd | 654 | idesc = irq_desc + vector; |
d1bef4ed IM |
655 | if (idesc->chip != irq_type) { |
656 | if (idesc->chip != &no_irq_type) | |
46cba3dc ST |
657 | printk(KERN_WARNING |
658 | "%s: changing vector %d from %s to %s\n", | |
659 | __FUNCTION__, vector, | |
351a5839 | 660 | idesc->chip->name, irq_type->name); |
d1bef4ed | 661 | idesc->chip = irq_type; |
1da177e4 | 662 | } |
14454a1b | 663 | return 0; |
1da177e4 LT |
664 | } |
665 | ||
666 | static unsigned int | |
667 | get_target_cpu (unsigned int gsi, int vector) | |
668 | { | |
669 | #ifdef CONFIG_SMP | |
670 | static int cpu = -1; | |
ff741906 | 671 | extern int cpe_vector; |
1da177e4 | 672 | |
24eeb568 KK |
673 | /* |
674 | * In case of vector shared by multiple RTEs, all RTEs that | |
675 | * share the vector need to use the same destination CPU. | |
676 | */ | |
677 | if (!list_empty(&iosapic_intr_info[vector].rtes)) | |
678 | return iosapic_intr_info[vector].dest; | |
679 | ||
1da177e4 LT |
680 | /* |
681 | * If the platform supports redirection via XTP, let it | |
682 | * distribute interrupts. | |
683 | */ | |
684 | if (smp_int_redirect & SMP_IRQ_REDIRECTION) | |
685 | return cpu_physical_id(smp_processor_id()); | |
686 | ||
687 | /* | |
688 | * Some interrupts (ACPI SCI, for instance) are registered | |
689 | * before the BSP is marked as online. | |
690 | */ | |
691 | if (!cpu_online(smp_processor_id())) | |
692 | return cpu_physical_id(smp_processor_id()); | |
693 | ||
ff741906 | 694 | #ifdef CONFIG_ACPI |
b88e9265 AR |
695 | if (cpe_vector > 0 && vector == IA64_CPEP_VECTOR) |
696 | return get_cpei_target_cpu(); | |
ff741906 AR |
697 | #endif |
698 | ||
1da177e4 LT |
699 | #ifdef CONFIG_NUMA |
700 | { | |
701 | int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0; | |
702 | cpumask_t cpu_mask; | |
703 | ||
704 | iosapic_index = find_iosapic(gsi); | |
705 | if (iosapic_index < 0 || | |
706 | iosapic_lists[iosapic_index].node == MAX_NUMNODES) | |
707 | goto skip_numa_setup; | |
708 | ||
709 | cpu_mask = node_to_cpumask(iosapic_lists[iosapic_index].node); | |
710 | ||
711 | for_each_cpu_mask(numa_cpu, cpu_mask) { | |
712 | if (!cpu_online(numa_cpu)) | |
713 | cpu_clear(numa_cpu, cpu_mask); | |
714 | } | |
715 | ||
716 | num_cpus = cpus_weight(cpu_mask); | |
717 | ||
718 | if (!num_cpus) | |
719 | goto skip_numa_setup; | |
720 | ||
46cba3dc | 721 | /* Use vector assignment to distribute across cpus in node */ |
1da177e4 LT |
722 | cpu_index = vector % num_cpus; |
723 | ||
724 | for (numa_cpu = first_cpu(cpu_mask) ; i < cpu_index ; i++) | |
725 | numa_cpu = next_cpu(numa_cpu, cpu_mask); | |
726 | ||
727 | if (numa_cpu != NR_CPUS) | |
728 | return cpu_physical_id(numa_cpu); | |
729 | } | |
730 | skip_numa_setup: | |
731 | #endif | |
732 | /* | |
733 | * Otherwise, round-robin interrupt vectors across all the | |
734 | * processors. (It'd be nice if we could be smarter in the | |
735 | * case of NUMA.) | |
736 | */ | |
737 | do { | |
738 | if (++cpu >= NR_CPUS) | |
739 | cpu = 0; | |
740 | } while (!cpu_online(cpu)); | |
741 | ||
742 | return cpu_physical_id(cpu); | |
46cba3dc | 743 | #else /* CONFIG_SMP */ |
1da177e4 LT |
744 | return cpu_physical_id(smp_processor_id()); |
745 | #endif | |
746 | } | |
747 | ||
748 | /* | |
749 | * ACPI can describe IOSAPIC interrupts via static tables and namespace | |
750 | * methods. This provides an interface to register those interrupts and | |
751 | * program the IOSAPIC RTE. | |
752 | */ | |
753 | int | |
754 | iosapic_register_intr (unsigned int gsi, | |
755 | unsigned long polarity, unsigned long trigger) | |
756 | { | |
eb21ab24 | 757 | int irq, vector, mask = 1, err; |
1da177e4 LT |
758 | unsigned int dest; |
759 | unsigned long flags; | |
24eeb568 KK |
760 | struct iosapic_rte_info *rte; |
761 | u32 low32; | |
40598cbe | 762 | |
1da177e4 LT |
763 | /* |
764 | * If this GSI has already been registered (i.e., it's a | |
765 | * shared interrupt, or we lost a race to register it), | |
766 | * don't touch the RTE. | |
767 | */ | |
768 | spin_lock_irqsave(&iosapic_lock, flags); | |
e3a8f7b8 YI |
769 | vector = gsi_to_vector(gsi); |
770 | if (vector > 0) { | |
771 | rte = gsi_vector_to_rte(gsi, vector); | |
772 | rte->refcnt++; | |
40598cbe | 773 | goto unlock_iosapic_lock; |
24eeb568 | 774 | } |
24eeb568 KK |
775 | |
776 | /* If vector is running out, we try to find a sharable vector */ | |
eb21ab24 YI |
777 | irq = create_irq(); |
778 | if (irq < 0) { | |
24eeb568 | 779 | vector = iosapic_find_sharable_vector(trigger, polarity); |
14454a1b | 780 | if (vector < 0) |
40598cbe | 781 | goto unlock_iosapic_lock; |
eb21ab24 YI |
782 | } else |
783 | vector = irq_to_vector(irq); | |
1da177e4 | 784 | |
40598cbe | 785 | spin_lock(&irq_desc[vector].lock); |
e3a8f7b8 YI |
786 | dest = get_target_cpu(gsi, vector); |
787 | err = register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY, | |
788 | polarity, trigger); | |
789 | if (err < 0) { | |
40598cbe YI |
790 | vector = err; |
791 | goto unlock_all; | |
1da177e4 | 792 | } |
e3a8f7b8 YI |
793 | |
794 | /* | |
795 | * If the vector is shared and already unmasked for other | |
796 | * interrupt sources, don't mask it. | |
797 | */ | |
798 | low32 = iosapic_intr_info[vector].low32; | |
799 | if (vector_is_shared(vector) && !(low32 & IOSAPIC_MASK)) | |
800 | mask = 0; | |
801 | set_rte(gsi, vector, dest, mask); | |
1da177e4 LT |
802 | |
803 | printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n", | |
804 | gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), | |
805 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | |
806 | cpu_logical_id(dest), dest, vector); | |
40598cbe YI |
807 | unlock_all: |
808 | spin_unlock(&irq_desc[vector].lock); | |
809 | unlock_iosapic_lock: | |
810 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1da177e4 LT |
811 | return vector; |
812 | } | |
813 | ||
1da177e4 LT |
814 | void |
815 | iosapic_unregister_intr (unsigned int gsi) | |
816 | { | |
817 | unsigned long flags; | |
0e888adc | 818 | int irq, vector, index; |
1da177e4 | 819 | irq_desc_t *idesc; |
24eeb568 | 820 | u32 low32; |
1da177e4 | 821 | unsigned long trigger, polarity; |
24eeb568 KK |
822 | unsigned int dest; |
823 | struct iosapic_rte_info *rte; | |
1da177e4 LT |
824 | |
825 | /* | |
826 | * If the irq associated with the gsi is not found, | |
827 | * iosapic_unregister_intr() is unbalanced. We need to check | |
828 | * this again after getting locks. | |
829 | */ | |
830 | irq = gsi_to_irq(gsi); | |
831 | if (irq < 0) { | |
46cba3dc ST |
832 | printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n", |
833 | gsi); | |
1da177e4 LT |
834 | WARN_ON(1); |
835 | return; | |
836 | } | |
837 | vector = irq_to_vector(irq); | |
838 | ||
40598cbe | 839 | spin_lock_irqsave(&iosapic_lock, flags); |
e3a8f7b8 YI |
840 | if ((rte = gsi_vector_to_rte(gsi, vector)) == NULL) { |
841 | printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n", | |
842 | gsi); | |
843 | WARN_ON(1); | |
844 | goto out; | |
845 | } | |
1da177e4 | 846 | |
e3a8f7b8 YI |
847 | if (--rte->refcnt > 0) |
848 | goto out; | |
1da177e4 | 849 | |
40598cbe YI |
850 | /* Remove the rte entry from the list */ |
851 | idesc = irq_desc + irq; | |
852 | spin_lock(&idesc->lock); | |
853 | list_del(&rte->rte_list); | |
854 | spin_unlock(&idesc->lock); | |
855 | ||
e3a8f7b8 YI |
856 | /* Mask the interrupt */ |
857 | low32 = iosapic_intr_info[vector].low32 | IOSAPIC_MASK; | |
c1726d6f | 858 | iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte->rte_index), low32); |
1da177e4 | 859 | |
e3a8f7b8 YI |
860 | iosapic_intr_info[vector].count--; |
861 | iosapic_free_rte(rte); | |
862 | index = find_iosapic(gsi); | |
863 | iosapic_lists[index].rtes_inuse--; | |
864 | WARN_ON(iosapic_lists[index].rtes_inuse < 0); | |
24eeb568 | 865 | |
e3a8f7b8 YI |
866 | trigger = iosapic_intr_info[vector].trigger; |
867 | polarity = iosapic_intr_info[vector].polarity; | |
868 | dest = iosapic_intr_info[vector].dest; | |
869 | printk(KERN_INFO | |
870 | "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n", | |
871 | gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), | |
872 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | |
873 | cpu_logical_id(dest), dest, vector); | |
24eeb568 | 874 | |
e3a8f7b8 YI |
875 | if (list_empty(&iosapic_intr_info[vector].rtes)) { |
876 | /* Sanity check */ | |
877 | BUG_ON(iosapic_intr_info[vector].count); | |
451fe00c | 878 | #ifdef CONFIG_SMP |
e3a8f7b8 YI |
879 | /* Clear affinity */ |
880 | cpus_setall(idesc->affinity); | |
451fe00c | 881 | #endif |
e3a8f7b8 YI |
882 | /* Clear the interrupt information */ |
883 | memset(&iosapic_intr_info[vector], 0, | |
884 | sizeof(struct iosapic_intr_info)); | |
885 | iosapic_intr_info[vector].low32 |= IOSAPIC_MASK; | |
886 | INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes); | |
1da177e4 | 887 | |
eb21ab24 YI |
888 | /* Destroy IRQ */ |
889 | destroy_irq(irq); | |
1da177e4 | 890 | } |
24eeb568 | 891 | out: |
40598cbe | 892 | spin_unlock_irqrestore(&iosapic_lock, flags); |
1da177e4 | 893 | } |
1da177e4 LT |
894 | |
895 | /* | |
896 | * ACPI calls this when it finds an entry for a platform interrupt. | |
1da177e4 LT |
897 | */ |
898 | int __init | |
899 | iosapic_register_platform_intr (u32 int_type, unsigned int gsi, | |
900 | int iosapic_vector, u16 eid, u16 id, | |
901 | unsigned long polarity, unsigned long trigger) | |
902 | { | |
903 | static const char * const name[] = {"unknown", "PMI", "INIT", "CPEI"}; | |
904 | unsigned char delivery; | |
eb21ab24 | 905 | int irq, vector, mask = 0; |
1da177e4 LT |
906 | unsigned int dest = ((id << 8) | eid) & 0xffff; |
907 | ||
908 | switch (int_type) { | |
909 | case ACPI_INTERRUPT_PMI: | |
910 | vector = iosapic_vector; | |
911 | /* | |
912 | * since PMI vector is alloc'd by FW(ACPI) not by kernel, | |
913 | * we need to make sure the vector is available | |
914 | */ | |
915 | iosapic_reassign_vector(vector); | |
916 | delivery = IOSAPIC_PMI; | |
917 | break; | |
918 | case ACPI_INTERRUPT_INIT: | |
eb21ab24 YI |
919 | irq = create_irq(); |
920 | if (irq < 0) | |
3b5cc090 | 921 | panic("%s: out of interrupt vectors!\n", __FUNCTION__); |
eb21ab24 | 922 | vector = irq_to_vector(irq); |
1da177e4 LT |
923 | delivery = IOSAPIC_INIT; |
924 | break; | |
925 | case ACPI_INTERRUPT_CPEI: | |
926 | vector = IA64_CPE_VECTOR; | |
927 | delivery = IOSAPIC_LOWEST_PRIORITY; | |
928 | mask = 1; | |
929 | break; | |
930 | default: | |
46cba3dc ST |
931 | printk(KERN_ERR "%s: invalid int type 0x%x\n", __FUNCTION__, |
932 | int_type); | |
1da177e4 LT |
933 | return -1; |
934 | } | |
935 | ||
936 | register_intr(gsi, vector, delivery, polarity, trigger); | |
937 | ||
46cba3dc ST |
938 | printk(KERN_INFO |
939 | "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x)" | |
940 | " vector %d\n", | |
1da177e4 LT |
941 | int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown", |
942 | int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), | |
943 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | |
944 | cpu_logical_id(dest), dest, vector); | |
945 | ||
24eeb568 | 946 | set_rte(gsi, vector, dest, mask); |
1da177e4 LT |
947 | return vector; |
948 | } | |
949 | ||
1da177e4 LT |
950 | /* |
951 | * ACPI calls this when it finds an entry for a legacy ISA IRQ override. | |
1da177e4 | 952 | */ |
0f7ac29e | 953 | void __devinit |
1da177e4 LT |
954 | iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi, |
955 | unsigned long polarity, | |
956 | unsigned long trigger) | |
957 | { | |
958 | int vector; | |
959 | unsigned int dest = cpu_physical_id(smp_processor_id()); | |
960 | ||
961 | vector = isa_irq_to_vector(isa_irq); | |
962 | ||
963 | register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY, polarity, trigger); | |
964 | ||
965 | DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n", | |
966 | isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level", | |
967 | polarity == IOSAPIC_POL_HIGH ? "high" : "low", | |
968 | cpu_logical_id(dest), dest, vector); | |
969 | ||
24eeb568 | 970 | set_rte(gsi, vector, dest, 1); |
1da177e4 LT |
971 | } |
972 | ||
973 | void __init | |
974 | iosapic_system_init (int system_pcat_compat) | |
975 | { | |
976 | int vector; | |
977 | ||
24eeb568 KK |
978 | for (vector = 0; vector < IA64_NUM_VECTORS; ++vector) { |
979 | iosapic_intr_info[vector].low32 = IOSAPIC_MASK; | |
46cba3dc ST |
980 | /* mark as unused */ |
981 | INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes); | |
24eeb568 | 982 | } |
1da177e4 LT |
983 | |
984 | pcat_compat = system_pcat_compat; | |
985 | if (pcat_compat) { | |
986 | /* | |
46cba3dc ST |
987 | * Disable the compatibility mode interrupts (8259 style), |
988 | * needs IN/OUT support enabled. | |
1da177e4 | 989 | */ |
46cba3dc ST |
990 | printk(KERN_INFO |
991 | "%s: Disabling PC-AT compatible 8259 interrupts\n", | |
992 | __FUNCTION__); | |
1da177e4 LT |
993 | outb(0xff, 0xA1); |
994 | outb(0xff, 0x21); | |
995 | } | |
996 | } | |
997 | ||
0e888adc KK |
998 | static inline int |
999 | iosapic_alloc (void) | |
1000 | { | |
1001 | int index; | |
1002 | ||
1003 | for (index = 0; index < NR_IOSAPICS; index++) | |
1004 | if (!iosapic_lists[index].addr) | |
1005 | return index; | |
1006 | ||
1007 | printk(KERN_WARNING "%s: failed to allocate iosapic\n", __FUNCTION__); | |
1008 | return -1; | |
1009 | } | |
1010 | ||
1011 | static inline void | |
1012 | iosapic_free (int index) | |
1013 | { | |
1014 | memset(&iosapic_lists[index], 0, sizeof(iosapic_lists[0])); | |
1015 | } | |
1016 | ||
1017 | static inline int | |
1018 | iosapic_check_gsi_range (unsigned int gsi_base, unsigned int ver) | |
1019 | { | |
1020 | int index; | |
1021 | unsigned int gsi_end, base, end; | |
1022 | ||
1023 | /* check gsi range */ | |
1024 | gsi_end = gsi_base + ((ver >> 16) & 0xff); | |
1025 | for (index = 0; index < NR_IOSAPICS; index++) { | |
1026 | if (!iosapic_lists[index].addr) | |
1027 | continue; | |
1028 | ||
1029 | base = iosapic_lists[index].gsi_base; | |
1030 | end = base + iosapic_lists[index].num_rte - 1; | |
1031 | ||
e6d1ba5c | 1032 | if (gsi_end < base || end < gsi_base) |
0e888adc KK |
1033 | continue; /* OK */ |
1034 | ||
1035 | return -EBUSY; | |
1036 | } | |
1037 | return 0; | |
1038 | } | |
1039 | ||
1040 | int __devinit | |
1da177e4 LT |
1041 | iosapic_init (unsigned long phys_addr, unsigned int gsi_base) |
1042 | { | |
0e888adc | 1043 | int num_rte, err, index; |
1da177e4 LT |
1044 | unsigned int isa_irq, ver; |
1045 | char __iomem *addr; | |
0e888adc KK |
1046 | unsigned long flags; |
1047 | ||
1048 | spin_lock_irqsave(&iosapic_lock, flags); | |
c1726d6f YI |
1049 | index = find_iosapic(gsi_base); |
1050 | if (index >= 0) { | |
1051 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1052 | return -EBUSY; | |
1053 | } | |
1054 | ||
e3a8f7b8 YI |
1055 | addr = ioremap(phys_addr, 0); |
1056 | ver = iosapic_version(addr); | |
e3a8f7b8 YI |
1057 | if ((err = iosapic_check_gsi_range(gsi_base, ver))) { |
1058 | iounmap(addr); | |
1059 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1060 | return err; | |
1061 | } | |
1da177e4 | 1062 | |
e3a8f7b8 YI |
1063 | /* |
1064 | * The MAX_REDIR register holds the highest input pin number | |
1065 | * (starting from 0). We add 1 so that we can use it for | |
1066 | * number of pins (= RTEs) | |
1067 | */ | |
1068 | num_rte = ((ver >> 16) & 0xff) + 1; | |
1da177e4 | 1069 | |
e3a8f7b8 YI |
1070 | index = iosapic_alloc(); |
1071 | iosapic_lists[index].addr = addr; | |
1072 | iosapic_lists[index].gsi_base = gsi_base; | |
1073 | iosapic_lists[index].num_rte = num_rte; | |
1da177e4 | 1074 | #ifdef CONFIG_NUMA |
e3a8f7b8 | 1075 | iosapic_lists[index].node = MAX_NUMNODES; |
1da177e4 | 1076 | #endif |
c1726d6f | 1077 | spin_lock_init(&iosapic_lists[index].lock); |
0e888adc | 1078 | spin_unlock_irqrestore(&iosapic_lock, flags); |
1da177e4 LT |
1079 | |
1080 | if ((gsi_base == 0) && pcat_compat) { | |
1081 | /* | |
46cba3dc ST |
1082 | * Map the legacy ISA devices into the IOSAPIC data. Some of |
1083 | * these may get reprogrammed later on with data from the ACPI | |
1084 | * Interrupt Source Override table. | |
1da177e4 LT |
1085 | */ |
1086 | for (isa_irq = 0; isa_irq < 16; ++isa_irq) | |
46cba3dc ST |
1087 | iosapic_override_isa_irq(isa_irq, isa_irq, |
1088 | IOSAPIC_POL_HIGH, | |
1089 | IOSAPIC_EDGE); | |
1da177e4 | 1090 | } |
0e888adc KK |
1091 | return 0; |
1092 | } | |
1093 | ||
1094 | #ifdef CONFIG_HOTPLUG | |
1095 | int | |
1096 | iosapic_remove (unsigned int gsi_base) | |
1097 | { | |
1098 | int index, err = 0; | |
1099 | unsigned long flags; | |
1100 | ||
1101 | spin_lock_irqsave(&iosapic_lock, flags); | |
e3a8f7b8 YI |
1102 | index = find_iosapic(gsi_base); |
1103 | if (index < 0) { | |
1104 | printk(KERN_WARNING "%s: No IOSAPIC for GSI base %u\n", | |
1105 | __FUNCTION__, gsi_base); | |
1106 | goto out; | |
1107 | } | |
0e888adc | 1108 | |
e3a8f7b8 YI |
1109 | if (iosapic_lists[index].rtes_inuse) { |
1110 | err = -EBUSY; | |
1111 | printk(KERN_WARNING "%s: IOSAPIC for GSI base %u is busy\n", | |
1112 | __FUNCTION__, gsi_base); | |
1113 | goto out; | |
0e888adc | 1114 | } |
e3a8f7b8 YI |
1115 | |
1116 | iounmap(iosapic_lists[index].addr); | |
1117 | iosapic_free(index); | |
0e888adc KK |
1118 | out: |
1119 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1120 | return err; | |
1da177e4 | 1121 | } |
0e888adc | 1122 | #endif /* CONFIG_HOTPLUG */ |
1da177e4 LT |
1123 | |
1124 | #ifdef CONFIG_NUMA | |
0e888adc | 1125 | void __devinit |
1da177e4 LT |
1126 | map_iosapic_to_node(unsigned int gsi_base, int node) |
1127 | { | |
1128 | int index; | |
1129 | ||
1130 | index = find_iosapic(gsi_base); | |
1131 | if (index < 0) { | |
1132 | printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n", | |
1133 | __FUNCTION__, gsi_base); | |
1134 | return; | |
1135 | } | |
1136 | iosapic_lists[index].node = node; | |
1137 | return; | |
1138 | } | |
1139 | #endif | |
24eeb568 KK |
1140 | |
1141 | static int __init iosapic_enable_kmalloc (void) | |
1142 | { | |
1143 | iosapic_kmalloc_ok = 1; | |
1144 | return 0; | |
1145 | } | |
1146 | core_initcall (iosapic_enable_kmalloc); |