Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * I/O SAPIC support. | |
3 | * | |
4 | * Copyright (C) 1999 Intel Corp. | |
5 | * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com> | |
6 | * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com> | |
7 | * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co. | |
8 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
9 | * Copyright (C) 1999 VA Linux Systems | |
10 | * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com> | |
11 | * | |
46cba3dc ST |
12 | * 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O |
13 | * APIC code. In particular, we now have separate | |
14 | * handlers for edge and level triggered | |
15 | * interrupts. | |
16 | * 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector | |
17 | * allocation PCI to vector mapping, shared PCI | |
18 | * interrupts. | |
19 | * 00/10/27 D. Mosberger Document things a bit more to make them more | |
20 | * understandable. Clean up much of the old | |
21 | * IOSAPIC cruft. | |
22 | * 01/07/27 J.I. Lee PCI irq routing, Platform/Legacy interrupts | |
23 | * and fixes for ACPI S5(SoftOff) support. | |
1da177e4 | 24 | * 02/01/23 J.I. Lee iosapic pgm fixes for PCI irq routing from _PRT |
46cba3dc ST |
25 | * 02/01/07 E. Focht <efocht@ess.nec.de> Redirectable interrupt |
26 | * vectors in iosapic_set_affinity(), | |
27 | * initializations for /proc/irq/#/smp_affinity | |
1da177e4 LT |
28 | * 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing. |
29 | * 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq | |
46cba3dc ST |
30 | * 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to |
31 | * IOSAPIC mapping error | |
1da177e4 | 32 | * 02/07/29 T. Kochi Allocate interrupt vectors dynamically |
46cba3dc ST |
33 | * 02/08/04 T. Kochi Cleaned up terminology (irq, global system |
34 | * interrupt, vector, etc.) | |
35 | * 02/09/20 D. Mosberger Simplified by taking advantage of ACPI's | |
36 | * pci_irq code. | |
1da177e4 | 37 | * 03/02/19 B. Helgaas Make pcat_compat system-wide, not per-IOSAPIC. |
46cba3dc ST |
38 | * Remove iosapic_address & gsi_base from |
39 | * external interfaces. Rationalize | |
40 | * __init/__devinit attributes. | |
1da177e4 | 41 | * 04/12/04 Ashok Raj <ashok.raj@intel.com> Intel Corporation 2004 |
46cba3dc ST |
42 | * Updated to work with irq migration necessary |
43 | * for CPU Hotplug | |
1da177e4 LT |
44 | */ |
45 | /* | |
46cba3dc ST |
46 | * Here is what the interrupt logic between a PCI device and the kernel looks |
47 | * like: | |
1da177e4 | 48 | * |
46cba3dc ST |
49 | * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC, |
50 | * INTD). The device is uniquely identified by its bus-, and slot-number | |
51 | * (the function number does not matter here because all functions share | |
52 | * the same interrupt lines). | |
1da177e4 | 53 | * |
46cba3dc ST |
54 | * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC |
55 | * controller. Multiple interrupt lines may have to share the same | |
56 | * IOSAPIC pin (if they're level triggered and use the same polarity). | |
57 | * Each interrupt line has a unique Global System Interrupt (GSI) number | |
58 | * which can be calculated as the sum of the controller's base GSI number | |
59 | * and the IOSAPIC pin number to which the line connects. | |
1da177e4 | 60 | * |
46cba3dc ST |
61 | * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the |
62 | * IOSAPIC pin into the IA-64 interrupt vector. This interrupt vector is then | |
63 | * sent to the CPU. | |
1da177e4 | 64 | * |
46cba3dc ST |
65 | * (4) The kernel recognizes an interrupt as an IRQ. The IRQ interface is |
66 | * used as architecture-independent interrupt handling mechanism in Linux. | |
67 | * As an IRQ is a number, we have to have | |
68 | * IA-64 interrupt vector number <-> IRQ number mapping. On smaller | |
69 | * systems, we use one-to-one mapping between IA-64 vector and IRQ. A | |
70 | * platform can implement platform_irq_to_vector(irq) and | |
1da177e4 LT |
71 | * platform_local_vector_to_irq(vector) APIs to differentiate the mapping. |
72 | * Please see also include/asm-ia64/hw_irq.h for those APIs. | |
73 | * | |
74 | * To sum up, there are three levels of mappings involved: | |
75 | * | |
76 | * PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ | |
77 | * | |
46cba3dc ST |
78 | * Note: The term "IRQ" is loosely used everywhere in Linux kernel to |
79 | * describeinterrupts. Now we use "IRQ" only for Linux IRQ's. ISA IRQ | |
80 | * (isa_irq) is the only exception in this source code. | |
1da177e4 | 81 | */ |
1da177e4 LT |
82 | |
83 | #include <linux/acpi.h> | |
84 | #include <linux/init.h> | |
85 | #include <linux/irq.h> | |
86 | #include <linux/kernel.h> | |
87 | #include <linux/list.h> | |
88 | #include <linux/pci.h> | |
89 | #include <linux/smp.h> | |
90 | #include <linux/smp_lock.h> | |
91 | #include <linux/string.h> | |
24eeb568 | 92 | #include <linux/bootmem.h> |
1da177e4 LT |
93 | |
94 | #include <asm/delay.h> | |
95 | #include <asm/hw_irq.h> | |
96 | #include <asm/io.h> | |
97 | #include <asm/iosapic.h> | |
98 | #include <asm/machvec.h> | |
99 | #include <asm/processor.h> | |
100 | #include <asm/ptrace.h> | |
101 | #include <asm/system.h> | |
102 | ||
1da177e4 LT |
103 | #undef DEBUG_INTERRUPT_ROUTING |
104 | ||
105 | #ifdef DEBUG_INTERRUPT_ROUTING | |
106 | #define DBG(fmt...) printk(fmt) | |
107 | #else | |
108 | #define DBG(fmt...) | |
109 | #endif | |
110 | ||
46cba3dc ST |
111 | #define NR_PREALLOCATE_RTE_ENTRIES \ |
112 | (PAGE_SIZE / sizeof(struct iosapic_rte_info)) | |
24eeb568 KK |
113 | #define RTE_PREALLOCATED (1) |
114 | ||
1da177e4 LT |
115 | static DEFINE_SPINLOCK(iosapic_lock); |
116 | ||
46cba3dc ST |
117 | /* |
118 | * These tables map IA-64 vectors to the IOSAPIC pin that generates this | |
119 | * vector. | |
120 | */ | |
1da177e4 | 121 | |
24eeb568 | 122 | struct iosapic_rte_info { |
46cba3dc ST |
123 | struct list_head rte_list; /* node in list of RTEs sharing the |
124 | * same vector */ | |
1da177e4 | 125 | char __iomem *addr; /* base address of IOSAPIC */ |
46cba3dc ST |
126 | unsigned int gsi_base; /* first GSI assigned to this |
127 | * IOSAPIC */ | |
24eeb568 KK |
128 | char rte_index; /* IOSAPIC RTE index */ |
129 | int refcnt; /* reference counter */ | |
130 | unsigned int flags; /* flags */ | |
131 | } ____cacheline_aligned; | |
132 | ||
133 | static struct iosapic_intr_info { | |
46cba3dc ST |
134 | struct list_head rtes; /* RTEs using this vector (empty => |
135 | * not an IOSAPIC interrupt) */ | |
24eeb568 | 136 | int count; /* # of RTEs that shares this vector */ |
46cba3dc ST |
137 | u32 low32; /* current value of low word of |
138 | * Redirection table entry */ | |
24eeb568 | 139 | unsigned int dest; /* destination CPU physical ID */ |
1da177e4 | 140 | unsigned char dmode : 3; /* delivery mode (see iosapic.h) */ |
46cba3dc ST |
141 | unsigned char polarity: 1; /* interrupt polarity |
142 | * (see iosapic.h) */ | |
1da177e4 | 143 | unsigned char trigger : 1; /* trigger mode (see iosapic.h) */ |
1da177e4 LT |
144 | } iosapic_intr_info[IA64_NUM_VECTORS]; |
145 | ||
146 | static struct iosapic { | |
147 | char __iomem *addr; /* base address of IOSAPIC */ | |
46cba3dc ST |
148 | unsigned int gsi_base; /* first GSI assigned to this |
149 | * IOSAPIC */ | |
150 | unsigned short num_rte; /* # of RTEs on this IOSAPIC */ | |
0e888adc | 151 | int rtes_inuse; /* # of RTEs in use on this IOSAPIC */ |
1da177e4 LT |
152 | #ifdef CONFIG_NUMA |
153 | unsigned short node; /* numa node association via pxm */ | |
154 | #endif | |
155 | } iosapic_lists[NR_IOSAPICS]; | |
156 | ||
0e888adc | 157 | static unsigned char pcat_compat __devinitdata; /* 8259 compatibility flag */ |
1da177e4 | 158 | |
24eeb568 KK |
159 | static int iosapic_kmalloc_ok; |
160 | static LIST_HEAD(free_rte_list); | |
1da177e4 LT |
161 | |
162 | /* | |
163 | * Find an IOSAPIC associated with a GSI | |
164 | */ | |
165 | static inline int | |
166 | find_iosapic (unsigned int gsi) | |
167 | { | |
168 | int i; | |
169 | ||
0e888adc | 170 | for (i = 0; i < NR_IOSAPICS; i++) { |
46cba3dc ST |
171 | if ((unsigned) (gsi - iosapic_lists[i].gsi_base) < |
172 | iosapic_lists[i].num_rte) | |
1da177e4 LT |
173 | return i; |
174 | } | |
175 | ||
176 | return -1; | |
177 | } | |
178 | ||
179 | static inline int | |
180 | _gsi_to_vector (unsigned int gsi) | |
181 | { | |
182 | struct iosapic_intr_info *info; | |
24eeb568 | 183 | struct iosapic_rte_info *rte; |
1da177e4 | 184 | |
46cba3dc ST |
185 | for (info = iosapic_intr_info; info < |
186 | iosapic_intr_info + IA64_NUM_VECTORS; ++info) | |
24eeb568 KK |
187 | list_for_each_entry(rte, &info->rtes, rte_list) |
188 | if (rte->gsi_base + rte->rte_index == gsi) | |
189 | return info - iosapic_intr_info; | |
1da177e4 LT |
190 | return -1; |
191 | } | |
192 | ||
193 | /* | |
194 | * Translate GSI number to the corresponding IA-64 interrupt vector. If no | |
195 | * entry exists, return -1. | |
196 | */ | |
197 | inline int | |
198 | gsi_to_vector (unsigned int gsi) | |
199 | { | |
200 | return _gsi_to_vector(gsi); | |
201 | } | |
202 | ||
203 | int | |
204 | gsi_to_irq (unsigned int gsi) | |
205 | { | |
24eeb568 KK |
206 | unsigned long flags; |
207 | int irq; | |
1da177e4 | 208 | /* |
46cba3dc ST |
209 | * XXX fix me: this assumes an identity mapping between IA-64 vector |
210 | * and Linux irq numbers... | |
1da177e4 | 211 | */ |
24eeb568 KK |
212 | spin_lock_irqsave(&iosapic_lock, flags); |
213 | { | |
214 | irq = _gsi_to_vector(gsi); | |
215 | } | |
216 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
217 | ||
218 | return irq; | |
219 | } | |
220 | ||
46cba3dc ST |
221 | static struct iosapic_rte_info *gsi_vector_to_rte(unsigned int gsi, |
222 | unsigned int vec) | |
24eeb568 KK |
223 | { |
224 | struct iosapic_rte_info *rte; | |
225 | ||
226 | list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) | |
227 | if (rte->gsi_base + rte->rte_index == gsi) | |
228 | return rte; | |
229 | return NULL; | |
1da177e4 LT |
230 | } |
231 | ||
232 | static void | |
24eeb568 | 233 | set_rte (unsigned int gsi, unsigned int vector, unsigned int dest, int mask) |
1da177e4 LT |
234 | { |
235 | unsigned long pol, trigger, dmode; | |
236 | u32 low32, high32; | |
237 | char __iomem *addr; | |
238 | int rte_index; | |
239 | char redir; | |
24eeb568 | 240 | struct iosapic_rte_info *rte; |
1da177e4 LT |
241 | |
242 | DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest); | |
243 | ||
24eeb568 KK |
244 | rte = gsi_vector_to_rte(gsi, vector); |
245 | if (!rte) | |
1da177e4 LT |
246 | return; /* not an IOSAPIC interrupt */ |
247 | ||
24eeb568 KK |
248 | rte_index = rte->rte_index; |
249 | addr = rte->addr; | |
1da177e4 LT |
250 | pol = iosapic_intr_info[vector].polarity; |
251 | trigger = iosapic_intr_info[vector].trigger; | |
252 | dmode = iosapic_intr_info[vector].dmode; | |
1da177e4 LT |
253 | |
254 | redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0; | |
255 | ||
256 | #ifdef CONFIG_SMP | |
257 | { | |
258 | unsigned int irq; | |
259 | ||
260 | for (irq = 0; irq < NR_IRQS; ++irq) | |
261 | if (irq_to_vector(irq) == vector) { | |
46cba3dc ST |
262 | set_irq_affinity_info(irq, |
263 | (int)(dest & 0xffff), | |
264 | redir); | |
1da177e4 LT |
265 | break; |
266 | } | |
267 | } | |
268 | #endif | |
269 | ||
270 | low32 = ((pol << IOSAPIC_POLARITY_SHIFT) | | |
271 | (trigger << IOSAPIC_TRIGGER_SHIFT) | | |
272 | (dmode << IOSAPIC_DELIVERY_SHIFT) | | |
273 | ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) | | |
274 | vector); | |
275 | ||
276 | /* dest contains both id and eid */ | |
277 | high32 = (dest << IOSAPIC_DEST_SHIFT); | |
278 | ||
279 | iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32); | |
280 | iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32); | |
281 | iosapic_intr_info[vector].low32 = low32; | |
24eeb568 | 282 | iosapic_intr_info[vector].dest = dest; |
1da177e4 LT |
283 | } |
284 | ||
285 | static void | |
46cba3dc | 286 | nop (unsigned int irq) |
1da177e4 LT |
287 | { |
288 | /* do nothing... */ | |
289 | } | |
290 | ||
291 | static void | |
292 | mask_irq (unsigned int irq) | |
293 | { | |
294 | unsigned long flags; | |
295 | char __iomem *addr; | |
296 | u32 low32; | |
297 | int rte_index; | |
298 | ia64_vector vec = irq_to_vector(irq); | |
24eeb568 | 299 | struct iosapic_rte_info *rte; |
1da177e4 | 300 | |
24eeb568 | 301 | if (list_empty(&iosapic_intr_info[vec].rtes)) |
1da177e4 LT |
302 | return; /* not an IOSAPIC interrupt! */ |
303 | ||
304 | spin_lock_irqsave(&iosapic_lock, flags); | |
305 | { | |
306 | /* set only the mask bit */ | |
307 | low32 = iosapic_intr_info[vec].low32 |= IOSAPIC_MASK; | |
46cba3dc ST |
308 | list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, |
309 | rte_list) { | |
24eeb568 KK |
310 | addr = rte->addr; |
311 | rte_index = rte->rte_index; | |
312 | iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32); | |
313 | } | |
1da177e4 LT |
314 | } |
315 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
316 | } | |
317 | ||
318 | static void | |
319 | unmask_irq (unsigned int irq) | |
320 | { | |
321 | unsigned long flags; | |
322 | char __iomem *addr; | |
323 | u32 low32; | |
324 | int rte_index; | |
325 | ia64_vector vec = irq_to_vector(irq); | |
24eeb568 | 326 | struct iosapic_rte_info *rte; |
1da177e4 | 327 | |
24eeb568 | 328 | if (list_empty(&iosapic_intr_info[vec].rtes)) |
1da177e4 LT |
329 | return; /* not an IOSAPIC interrupt! */ |
330 | ||
331 | spin_lock_irqsave(&iosapic_lock, flags); | |
332 | { | |
333 | low32 = iosapic_intr_info[vec].low32 &= ~IOSAPIC_MASK; | |
46cba3dc ST |
334 | list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, |
335 | rte_list) { | |
24eeb568 KK |
336 | addr = rte->addr; |
337 | rte_index = rte->rte_index; | |
338 | iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32); | |
339 | } | |
1da177e4 LT |
340 | } |
341 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
342 | } | |
343 | ||
344 | ||
345 | static void | |
346 | iosapic_set_affinity (unsigned int irq, cpumask_t mask) | |
347 | { | |
348 | #ifdef CONFIG_SMP | |
349 | unsigned long flags; | |
350 | u32 high32, low32; | |
351 | int dest, rte_index; | |
352 | char __iomem *addr; | |
353 | int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0; | |
354 | ia64_vector vec; | |
24eeb568 | 355 | struct iosapic_rte_info *rte; |
1da177e4 LT |
356 | |
357 | irq &= (~IA64_IRQ_REDIRECTED); | |
358 | vec = irq_to_vector(irq); | |
359 | ||
360 | if (cpus_empty(mask)) | |
361 | return; | |
362 | ||
363 | dest = cpu_physical_id(first_cpu(mask)); | |
364 | ||
24eeb568 | 365 | if (list_empty(&iosapic_intr_info[vec].rtes)) |
1da177e4 LT |
366 | return; /* not an IOSAPIC interrupt */ |
367 | ||
368 | set_irq_affinity_info(irq, dest, redir); | |
369 | ||
370 | /* dest contains both id and eid */ | |
371 | high32 = dest << IOSAPIC_DEST_SHIFT; | |
372 | ||
373 | spin_lock_irqsave(&iosapic_lock, flags); | |
374 | { | |
46cba3dc ST |
375 | low32 = iosapic_intr_info[vec].low32 & |
376 | ~(7 << IOSAPIC_DELIVERY_SHIFT); | |
1da177e4 LT |
377 | |
378 | if (redir) | |
379 | /* change delivery mode to lowest priority */ | |
46cba3dc ST |
380 | low32 |= (IOSAPIC_LOWEST_PRIORITY << |
381 | IOSAPIC_DELIVERY_SHIFT); | |
1da177e4 LT |
382 | else |
383 | /* change delivery mode to fixed */ | |
384 | low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT); | |
385 | ||
386 | iosapic_intr_info[vec].low32 = low32; | |
24eeb568 | 387 | iosapic_intr_info[vec].dest = dest; |
46cba3dc ST |
388 | list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, |
389 | rte_list) { | |
24eeb568 KK |
390 | addr = rte->addr; |
391 | rte_index = rte->rte_index; | |
46cba3dc ST |
392 | iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), |
393 | high32); | |
24eeb568 KK |
394 | iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32); |
395 | } | |
1da177e4 LT |
396 | } |
397 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
398 | #endif | |
399 | } | |
400 | ||
401 | /* | |
402 | * Handlers for level-triggered interrupts. | |
403 | */ | |
404 | ||
405 | static unsigned int | |
406 | iosapic_startup_level_irq (unsigned int irq) | |
407 | { | |
408 | unmask_irq(irq); | |
409 | return 0; | |
410 | } | |
411 | ||
412 | static void | |
413 | iosapic_end_level_irq (unsigned int irq) | |
414 | { | |
415 | ia64_vector vec = irq_to_vector(irq); | |
24eeb568 | 416 | struct iosapic_rte_info *rte; |
1da177e4 | 417 | |
41503def | 418 | move_native_irq(irq); |
24eeb568 KK |
419 | list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) |
420 | iosapic_eoi(rte->addr, vec); | |
1da177e4 LT |
421 | } |
422 | ||
423 | #define iosapic_shutdown_level_irq mask_irq | |
424 | #define iosapic_enable_level_irq unmask_irq | |
425 | #define iosapic_disable_level_irq mask_irq | |
426 | #define iosapic_ack_level_irq nop | |
427 | ||
428 | struct hw_interrupt_type irq_type_iosapic_level = { | |
429 | .typename = "IO-SAPIC-level", | |
430 | .startup = iosapic_startup_level_irq, | |
431 | .shutdown = iosapic_shutdown_level_irq, | |
432 | .enable = iosapic_enable_level_irq, | |
433 | .disable = iosapic_disable_level_irq, | |
434 | .ack = iosapic_ack_level_irq, | |
435 | .end = iosapic_end_level_irq, | |
436 | .set_affinity = iosapic_set_affinity | |
437 | }; | |
438 | ||
439 | /* | |
440 | * Handlers for edge-triggered interrupts. | |
441 | */ | |
442 | ||
443 | static unsigned int | |
444 | iosapic_startup_edge_irq (unsigned int irq) | |
445 | { | |
446 | unmask_irq(irq); | |
447 | /* | |
448 | * IOSAPIC simply drops interrupts pended while the | |
449 | * corresponding pin was masked, so we can't know if an | |
450 | * interrupt is pending already. Let's hope not... | |
451 | */ | |
452 | return 0; | |
453 | } | |
454 | ||
455 | static void | |
456 | iosapic_ack_edge_irq (unsigned int irq) | |
457 | { | |
a8553acd | 458 | irq_desc_t *idesc = irq_desc + irq; |
1da177e4 | 459 | |
41503def | 460 | move_native_irq(irq); |
1da177e4 LT |
461 | /* |
462 | * Once we have recorded IRQ_PENDING already, we can mask the | |
463 | * interrupt for real. This prevents IRQ storms from unhandled | |
464 | * devices. | |
465 | */ | |
46cba3dc ST |
466 | if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) == |
467 | (IRQ_PENDING|IRQ_DISABLED)) | |
1da177e4 LT |
468 | mask_irq(irq); |
469 | } | |
470 | ||
471 | #define iosapic_enable_edge_irq unmask_irq | |
472 | #define iosapic_disable_edge_irq nop | |
473 | #define iosapic_end_edge_irq nop | |
474 | ||
475 | struct hw_interrupt_type irq_type_iosapic_edge = { | |
476 | .typename = "IO-SAPIC-edge", | |
477 | .startup = iosapic_startup_edge_irq, | |
478 | .shutdown = iosapic_disable_edge_irq, | |
479 | .enable = iosapic_enable_edge_irq, | |
480 | .disable = iosapic_disable_edge_irq, | |
481 | .ack = iosapic_ack_edge_irq, | |
482 | .end = iosapic_end_edge_irq, | |
483 | .set_affinity = iosapic_set_affinity | |
484 | }; | |
485 | ||
486 | unsigned int | |
487 | iosapic_version (char __iomem *addr) | |
488 | { | |
489 | /* | |
490 | * IOSAPIC Version Register return 32 bit structure like: | |
491 | * { | |
492 | * unsigned int version : 8; | |
493 | * unsigned int reserved1 : 8; | |
494 | * unsigned int max_redir : 8; | |
495 | * unsigned int reserved2 : 8; | |
496 | * } | |
497 | */ | |
498 | return iosapic_read(addr, IOSAPIC_VERSION); | |
499 | } | |
500 | ||
46cba3dc ST |
501 | static int iosapic_find_sharable_vector (unsigned long trigger, |
502 | unsigned long pol) | |
24eeb568 KK |
503 | { |
504 | int i, vector = -1, min_count = -1; | |
505 | struct iosapic_intr_info *info; | |
506 | ||
507 | /* | |
508 | * shared vectors for edge-triggered interrupts are not | |
509 | * supported yet | |
510 | */ | |
511 | if (trigger == IOSAPIC_EDGE) | |
512 | return -1; | |
513 | ||
514 | for (i = IA64_FIRST_DEVICE_VECTOR; i <= IA64_LAST_DEVICE_VECTOR; i++) { | |
515 | info = &iosapic_intr_info[i]; | |
516 | if (info->trigger == trigger && info->polarity == pol && | |
46cba3dc ST |
517 | (info->dmode == IOSAPIC_FIXED || info->dmode == |
518 | IOSAPIC_LOWEST_PRIORITY)) { | |
24eeb568 KK |
519 | if (min_count == -1 || info->count < min_count) { |
520 | vector = i; | |
521 | min_count = info->count; | |
522 | } | |
523 | } | |
524 | } | |
24eeb568 KK |
525 | |
526 | return vector; | |
527 | } | |
528 | ||
1da177e4 LT |
529 | /* |
530 | * if the given vector is already owned by other, | |
531 | * assign a new vector for the other and make the vector available | |
532 | */ | |
533 | static void __init | |
534 | iosapic_reassign_vector (int vector) | |
535 | { | |
536 | int new_vector; | |
537 | ||
24eeb568 | 538 | if (!list_empty(&iosapic_intr_info[vector].rtes)) { |
1da177e4 | 539 | new_vector = assign_irq_vector(AUTO_ASSIGN); |
3b5cc090 KK |
540 | if (new_vector < 0) |
541 | panic("%s: out of interrupt vectors!\n", __FUNCTION__); | |
46cba3dc ST |
542 | printk(KERN_INFO "Reassigning vector %d to %d\n", |
543 | vector, new_vector); | |
1da177e4 LT |
544 | memcpy(&iosapic_intr_info[new_vector], &iosapic_intr_info[vector], |
545 | sizeof(struct iosapic_intr_info)); | |
24eeb568 | 546 | INIT_LIST_HEAD(&iosapic_intr_info[new_vector].rtes); |
46cba3dc ST |
547 | list_move(iosapic_intr_info[vector].rtes.next, |
548 | &iosapic_intr_info[new_vector].rtes); | |
549 | memset(&iosapic_intr_info[vector], 0, | |
550 | sizeof(struct iosapic_intr_info)); | |
24eeb568 KK |
551 | iosapic_intr_info[vector].low32 = IOSAPIC_MASK; |
552 | INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes); | |
1da177e4 LT |
553 | } |
554 | } | |
555 | ||
24eeb568 KK |
556 | static struct iosapic_rte_info *iosapic_alloc_rte (void) |
557 | { | |
558 | int i; | |
559 | struct iosapic_rte_info *rte; | |
560 | int preallocated = 0; | |
561 | ||
562 | if (!iosapic_kmalloc_ok && list_empty(&free_rte_list)) { | |
46cba3dc ST |
563 | rte = alloc_bootmem(sizeof(struct iosapic_rte_info) * |
564 | NR_PREALLOCATE_RTE_ENTRIES); | |
24eeb568 KK |
565 | if (!rte) |
566 | return NULL; | |
567 | for (i = 0; i < NR_PREALLOCATE_RTE_ENTRIES; i++, rte++) | |
568 | list_add(&rte->rte_list, &free_rte_list); | |
569 | } | |
570 | ||
571 | if (!list_empty(&free_rte_list)) { | |
46cba3dc ST |
572 | rte = list_entry(free_rte_list.next, struct iosapic_rte_info, |
573 | rte_list); | |
24eeb568 KK |
574 | list_del(&rte->rte_list); |
575 | preallocated++; | |
576 | } else { | |
577 | rte = kmalloc(sizeof(struct iosapic_rte_info), GFP_ATOMIC); | |
578 | if (!rte) | |
579 | return NULL; | |
580 | } | |
581 | ||
582 | memset(rte, 0, sizeof(struct iosapic_rte_info)); | |
583 | if (preallocated) | |
584 | rte->flags |= RTE_PREALLOCATED; | |
585 | ||
586 | return rte; | |
587 | } | |
588 | ||
589 | static void iosapic_free_rte (struct iosapic_rte_info *rte) | |
590 | { | |
591 | if (rte->flags & RTE_PREALLOCATED) | |
592 | list_add_tail(&rte->rte_list, &free_rte_list); | |
593 | else | |
594 | kfree(rte); | |
595 | } | |
596 | ||
597 | static inline int vector_is_shared (int vector) | |
598 | { | |
599 | return (iosapic_intr_info[vector].count > 1); | |
600 | } | |
601 | ||
14454a1b | 602 | static int |
1da177e4 LT |
603 | register_intr (unsigned int gsi, int vector, unsigned char delivery, |
604 | unsigned long polarity, unsigned long trigger) | |
605 | { | |
606 | irq_desc_t *idesc; | |
607 | struct hw_interrupt_type *irq_type; | |
608 | int rte_index; | |
609 | int index; | |
610 | unsigned long gsi_base; | |
611 | void __iomem *iosapic_address; | |
24eeb568 | 612 | struct iosapic_rte_info *rte; |
1da177e4 LT |
613 | |
614 | index = find_iosapic(gsi); | |
615 | if (index < 0) { | |
46cba3dc ST |
616 | printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n", |
617 | __FUNCTION__, gsi); | |
14454a1b | 618 | return -ENODEV; |
1da177e4 LT |
619 | } |
620 | ||
621 | iosapic_address = iosapic_lists[index].addr; | |
622 | gsi_base = iosapic_lists[index].gsi_base; | |
623 | ||
24eeb568 KK |
624 | rte = gsi_vector_to_rte(gsi, vector); |
625 | if (!rte) { | |
626 | rte = iosapic_alloc_rte(); | |
627 | if (!rte) { | |
46cba3dc ST |
628 | printk(KERN_WARNING "%s: cannot allocate memory\n", |
629 | __FUNCTION__); | |
14454a1b | 630 | return -ENOMEM; |
24eeb568 KK |
631 | } |
632 | ||
633 | rte_index = gsi - gsi_base; | |
634 | rte->rte_index = rte_index; | |
635 | rte->addr = iosapic_address; | |
636 | rte->gsi_base = gsi_base; | |
637 | rte->refcnt++; | |
638 | list_add_tail(&rte->rte_list, &iosapic_intr_info[vector].rtes); | |
639 | iosapic_intr_info[vector].count++; | |
0e888adc | 640 | iosapic_lists[index].rtes_inuse++; |
24eeb568 KK |
641 | } |
642 | else if (vector_is_shared(vector)) { | |
643 | struct iosapic_intr_info *info = &iosapic_intr_info[vector]; | |
644 | if (info->trigger != trigger || info->polarity != polarity) { | |
46cba3dc ST |
645 | printk (KERN_WARNING |
646 | "%s: cannot override the interrupt\n", | |
647 | __FUNCTION__); | |
14454a1b | 648 | return -EINVAL; |
24eeb568 KK |
649 | } |
650 | } | |
651 | ||
1da177e4 LT |
652 | iosapic_intr_info[vector].polarity = polarity; |
653 | iosapic_intr_info[vector].dmode = delivery; | |
1da177e4 | 654 | iosapic_intr_info[vector].trigger = trigger; |
1da177e4 LT |
655 | |
656 | if (trigger == IOSAPIC_EDGE) | |
657 | irq_type = &irq_type_iosapic_edge; | |
658 | else | |
659 | irq_type = &irq_type_iosapic_level; | |
660 | ||
a8553acd | 661 | idesc = irq_desc + vector; |
d1bef4ed IM |
662 | if (idesc->chip != irq_type) { |
663 | if (idesc->chip != &no_irq_type) | |
46cba3dc ST |
664 | printk(KERN_WARNING |
665 | "%s: changing vector %d from %s to %s\n", | |
666 | __FUNCTION__, vector, | |
d1bef4ed IM |
667 | idesc->chip->typename, irq_type->typename); |
668 | idesc->chip = irq_type; | |
1da177e4 | 669 | } |
14454a1b | 670 | return 0; |
1da177e4 LT |
671 | } |
672 | ||
673 | static unsigned int | |
674 | get_target_cpu (unsigned int gsi, int vector) | |
675 | { | |
676 | #ifdef CONFIG_SMP | |
677 | static int cpu = -1; | |
ff741906 | 678 | extern int cpe_vector; |
1da177e4 | 679 | |
24eeb568 KK |
680 | /* |
681 | * In case of vector shared by multiple RTEs, all RTEs that | |
682 | * share the vector need to use the same destination CPU. | |
683 | */ | |
684 | if (!list_empty(&iosapic_intr_info[vector].rtes)) | |
685 | return iosapic_intr_info[vector].dest; | |
686 | ||
1da177e4 LT |
687 | /* |
688 | * If the platform supports redirection via XTP, let it | |
689 | * distribute interrupts. | |
690 | */ | |
691 | if (smp_int_redirect & SMP_IRQ_REDIRECTION) | |
692 | return cpu_physical_id(smp_processor_id()); | |
693 | ||
694 | /* | |
695 | * Some interrupts (ACPI SCI, for instance) are registered | |
696 | * before the BSP is marked as online. | |
697 | */ | |
698 | if (!cpu_online(smp_processor_id())) | |
699 | return cpu_physical_id(smp_processor_id()); | |
700 | ||
ff741906 | 701 | #ifdef CONFIG_ACPI |
b88e9265 AR |
702 | if (cpe_vector > 0 && vector == IA64_CPEP_VECTOR) |
703 | return get_cpei_target_cpu(); | |
ff741906 AR |
704 | #endif |
705 | ||
1da177e4 LT |
706 | #ifdef CONFIG_NUMA |
707 | { | |
708 | int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0; | |
709 | cpumask_t cpu_mask; | |
710 | ||
711 | iosapic_index = find_iosapic(gsi); | |
712 | if (iosapic_index < 0 || | |
713 | iosapic_lists[iosapic_index].node == MAX_NUMNODES) | |
714 | goto skip_numa_setup; | |
715 | ||
716 | cpu_mask = node_to_cpumask(iosapic_lists[iosapic_index].node); | |
717 | ||
718 | for_each_cpu_mask(numa_cpu, cpu_mask) { | |
719 | if (!cpu_online(numa_cpu)) | |
720 | cpu_clear(numa_cpu, cpu_mask); | |
721 | } | |
722 | ||
723 | num_cpus = cpus_weight(cpu_mask); | |
724 | ||
725 | if (!num_cpus) | |
726 | goto skip_numa_setup; | |
727 | ||
46cba3dc | 728 | /* Use vector assignment to distribute across cpus in node */ |
1da177e4 LT |
729 | cpu_index = vector % num_cpus; |
730 | ||
731 | for (numa_cpu = first_cpu(cpu_mask) ; i < cpu_index ; i++) | |
732 | numa_cpu = next_cpu(numa_cpu, cpu_mask); | |
733 | ||
734 | if (numa_cpu != NR_CPUS) | |
735 | return cpu_physical_id(numa_cpu); | |
736 | } | |
737 | skip_numa_setup: | |
738 | #endif | |
739 | /* | |
740 | * Otherwise, round-robin interrupt vectors across all the | |
741 | * processors. (It'd be nice if we could be smarter in the | |
742 | * case of NUMA.) | |
743 | */ | |
744 | do { | |
745 | if (++cpu >= NR_CPUS) | |
746 | cpu = 0; | |
747 | } while (!cpu_online(cpu)); | |
748 | ||
749 | return cpu_physical_id(cpu); | |
46cba3dc | 750 | #else /* CONFIG_SMP */ |
1da177e4 LT |
751 | return cpu_physical_id(smp_processor_id()); |
752 | #endif | |
753 | } | |
754 | ||
755 | /* | |
756 | * ACPI can describe IOSAPIC interrupts via static tables and namespace | |
757 | * methods. This provides an interface to register those interrupts and | |
758 | * program the IOSAPIC RTE. | |
759 | */ | |
760 | int | |
761 | iosapic_register_intr (unsigned int gsi, | |
762 | unsigned long polarity, unsigned long trigger) | |
763 | { | |
14454a1b | 764 | int vector, mask = 1, err; |
1da177e4 LT |
765 | unsigned int dest; |
766 | unsigned long flags; | |
24eeb568 KK |
767 | struct iosapic_rte_info *rte; |
768 | u32 low32; | |
769 | again: | |
1da177e4 LT |
770 | /* |
771 | * If this GSI has already been registered (i.e., it's a | |
772 | * shared interrupt, or we lost a race to register it), | |
773 | * don't touch the RTE. | |
774 | */ | |
775 | spin_lock_irqsave(&iosapic_lock, flags); | |
776 | { | |
777 | vector = gsi_to_vector(gsi); | |
778 | if (vector > 0) { | |
24eeb568 KK |
779 | rte = gsi_vector_to_rte(gsi, vector); |
780 | rte->refcnt++; | |
1da177e4 LT |
781 | spin_unlock_irqrestore(&iosapic_lock, flags); |
782 | return vector; | |
783 | } | |
24eeb568 KK |
784 | } |
785 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
786 | ||
787 | /* If vector is running out, we try to find a sharable vector */ | |
3b5cc090 KK |
788 | vector = assign_irq_vector(AUTO_ASSIGN); |
789 | if (vector < 0) { | |
24eeb568 | 790 | vector = iosapic_find_sharable_vector(trigger, polarity); |
14454a1b | 791 | if (vector < 0) |
702c7e76 | 792 | return -ENOSPC; |
3b5cc090 | 793 | } |
24eeb568 | 794 | |
a8553acd | 795 | spin_lock_irqsave(&irq_desc[vector].lock, flags); |
24eeb568 KK |
796 | spin_lock(&iosapic_lock); |
797 | { | |
798 | if (gsi_to_vector(gsi) > 0) { | |
799 | if (list_empty(&iosapic_intr_info[vector].rtes)) | |
800 | free_irq_vector(vector); | |
801 | spin_unlock(&iosapic_lock); | |
a8553acd | 802 | spin_unlock_irqrestore(&irq_desc[vector].lock, |
46cba3dc | 803 | flags); |
24eeb568 KK |
804 | goto again; |
805 | } | |
1da177e4 | 806 | |
1da177e4 | 807 | dest = get_target_cpu(gsi, vector); |
14454a1b | 808 | err = register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY, |
24eeb568 | 809 | polarity, trigger); |
14454a1b KK |
810 | if (err < 0) { |
811 | spin_unlock(&iosapic_lock); | |
a8553acd | 812 | spin_unlock_irqrestore(&irq_desc[vector].lock, |
46cba3dc | 813 | flags); |
14454a1b KK |
814 | return err; |
815 | } | |
1da177e4 | 816 | |
24eeb568 KK |
817 | /* |
818 | * If the vector is shared and already unmasked for | |
819 | * other interrupt sources, don't mask it. | |
820 | */ | |
821 | low32 = iosapic_intr_info[vector].low32; | |
822 | if (vector_is_shared(vector) && !(low32 & IOSAPIC_MASK)) | |
823 | mask = 0; | |
824 | set_rte(gsi, vector, dest, mask); | |
1da177e4 | 825 | } |
b9e41d7f | 826 | spin_unlock(&iosapic_lock); |
a8553acd | 827 | spin_unlock_irqrestore(&irq_desc[vector].lock, flags); |
1da177e4 LT |
828 | |
829 | printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n", | |
830 | gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), | |
831 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | |
832 | cpu_logical_id(dest), dest, vector); | |
833 | ||
834 | return vector; | |
835 | } | |
836 | ||
1da177e4 LT |
837 | void |
838 | iosapic_unregister_intr (unsigned int gsi) | |
839 | { | |
840 | unsigned long flags; | |
0e888adc | 841 | int irq, vector, index; |
1da177e4 | 842 | irq_desc_t *idesc; |
24eeb568 | 843 | u32 low32; |
1da177e4 | 844 | unsigned long trigger, polarity; |
24eeb568 KK |
845 | unsigned int dest; |
846 | struct iosapic_rte_info *rte; | |
1da177e4 LT |
847 | |
848 | /* | |
849 | * If the irq associated with the gsi is not found, | |
850 | * iosapic_unregister_intr() is unbalanced. We need to check | |
851 | * this again after getting locks. | |
852 | */ | |
853 | irq = gsi_to_irq(gsi); | |
854 | if (irq < 0) { | |
46cba3dc ST |
855 | printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n", |
856 | gsi); | |
1da177e4 LT |
857 | WARN_ON(1); |
858 | return; | |
859 | } | |
860 | vector = irq_to_vector(irq); | |
861 | ||
a8553acd | 862 | idesc = irq_desc + irq; |
1da177e4 LT |
863 | spin_lock_irqsave(&idesc->lock, flags); |
864 | spin_lock(&iosapic_lock); | |
865 | { | |
24eeb568 | 866 | if ((rte = gsi_vector_to_rte(gsi, vector)) == NULL) { |
46cba3dc ST |
867 | printk(KERN_ERR |
868 | "iosapic_unregister_intr(%u) unbalanced\n", | |
869 | gsi); | |
1da177e4 | 870 | WARN_ON(1); |
24eeb568 | 871 | goto out; |
1da177e4 LT |
872 | } |
873 | ||
24eeb568 KK |
874 | if (--rte->refcnt > 0) |
875 | goto out; | |
1da177e4 | 876 | |
24eeb568 KK |
877 | /* Mask the interrupt */ |
878 | low32 = iosapic_intr_info[vector].low32 | IOSAPIC_MASK; | |
46cba3dc ST |
879 | iosapic_write(rte->addr, IOSAPIC_RTE_LOW(rte->rte_index), |
880 | low32); | |
1da177e4 | 881 | |
24eeb568 KK |
882 | /* Remove the rte entry from the list */ |
883 | list_del(&rte->rte_list); | |
884 | iosapic_intr_info[vector].count--; | |
885 | iosapic_free_rte(rte); | |
0e888adc KK |
886 | index = find_iosapic(gsi); |
887 | iosapic_lists[index].rtes_inuse--; | |
888 | WARN_ON(iosapic_lists[index].rtes_inuse < 0); | |
1da177e4 | 889 | |
24eeb568 | 890 | trigger = iosapic_intr_info[vector].trigger; |
1da177e4 | 891 | polarity = iosapic_intr_info[vector].polarity; |
24eeb568 | 892 | dest = iosapic_intr_info[vector].dest; |
46cba3dc ST |
893 | printk(KERN_INFO |
894 | "GSI %u (%s, %s) -> CPU %d (0x%04x)" | |
895 | " vector %d unregistered\n", | |
24eeb568 KK |
896 | gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), |
897 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | |
898 | cpu_logical_id(dest), dest, vector); | |
899 | ||
900 | if (list_empty(&iosapic_intr_info[vector].rtes)) { | |
901 | /* Sanity check */ | |
902 | BUG_ON(iosapic_intr_info[vector].count); | |
903 | ||
904 | /* Clear the interrupt controller descriptor */ | |
d1bef4ed | 905 | idesc->chip = &no_irq_type; |
24eeb568 KK |
906 | |
907 | /* Clear the interrupt information */ | |
46cba3dc ST |
908 | memset(&iosapic_intr_info[vector], 0, |
909 | sizeof(struct iosapic_intr_info)); | |
24eeb568 KK |
910 | iosapic_intr_info[vector].low32 |= IOSAPIC_MASK; |
911 | INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes); | |
912 | ||
913 | if (idesc->action) { | |
46cba3dc ST |
914 | printk(KERN_ERR |
915 | "interrupt handlers still exist on" | |
916 | "IRQ %u\n", irq); | |
24eeb568 KK |
917 | WARN_ON(1); |
918 | } | |
1da177e4 | 919 | |
24eeb568 KK |
920 | /* Free the interrupt vector */ |
921 | free_irq_vector(vector); | |
922 | } | |
1da177e4 | 923 | } |
24eeb568 | 924 | out: |
1da177e4 LT |
925 | spin_unlock(&iosapic_lock); |
926 | spin_unlock_irqrestore(&idesc->lock, flags); | |
1da177e4 | 927 | } |
1da177e4 LT |
928 | |
929 | /* | |
930 | * ACPI calls this when it finds an entry for a platform interrupt. | |
1da177e4 LT |
931 | */ |
932 | int __init | |
933 | iosapic_register_platform_intr (u32 int_type, unsigned int gsi, | |
934 | int iosapic_vector, u16 eid, u16 id, | |
935 | unsigned long polarity, unsigned long trigger) | |
936 | { | |
937 | static const char * const name[] = {"unknown", "PMI", "INIT", "CPEI"}; | |
938 | unsigned char delivery; | |
939 | int vector, mask = 0; | |
940 | unsigned int dest = ((id << 8) | eid) & 0xffff; | |
941 | ||
942 | switch (int_type) { | |
943 | case ACPI_INTERRUPT_PMI: | |
944 | vector = iosapic_vector; | |
945 | /* | |
946 | * since PMI vector is alloc'd by FW(ACPI) not by kernel, | |
947 | * we need to make sure the vector is available | |
948 | */ | |
949 | iosapic_reassign_vector(vector); | |
950 | delivery = IOSAPIC_PMI; | |
951 | break; | |
952 | case ACPI_INTERRUPT_INIT: | |
953 | vector = assign_irq_vector(AUTO_ASSIGN); | |
3b5cc090 KK |
954 | if (vector < 0) |
955 | panic("%s: out of interrupt vectors!\n", __FUNCTION__); | |
1da177e4 LT |
956 | delivery = IOSAPIC_INIT; |
957 | break; | |
958 | case ACPI_INTERRUPT_CPEI: | |
959 | vector = IA64_CPE_VECTOR; | |
960 | delivery = IOSAPIC_LOWEST_PRIORITY; | |
961 | mask = 1; | |
962 | break; | |
963 | default: | |
46cba3dc ST |
964 | printk(KERN_ERR "%s: invalid int type 0x%x\n", __FUNCTION__, |
965 | int_type); | |
1da177e4 LT |
966 | return -1; |
967 | } | |
968 | ||
969 | register_intr(gsi, vector, delivery, polarity, trigger); | |
970 | ||
46cba3dc ST |
971 | printk(KERN_INFO |
972 | "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x)" | |
973 | " vector %d\n", | |
1da177e4 LT |
974 | int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown", |
975 | int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), | |
976 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | |
977 | cpu_logical_id(dest), dest, vector); | |
978 | ||
24eeb568 | 979 | set_rte(gsi, vector, dest, mask); |
1da177e4 LT |
980 | return vector; |
981 | } | |
982 | ||
1da177e4 LT |
983 | /* |
984 | * ACPI calls this when it finds an entry for a legacy ISA IRQ override. | |
1da177e4 LT |
985 | */ |
986 | void __init | |
987 | iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi, | |
988 | unsigned long polarity, | |
989 | unsigned long trigger) | |
990 | { | |
991 | int vector; | |
992 | unsigned int dest = cpu_physical_id(smp_processor_id()); | |
993 | ||
994 | vector = isa_irq_to_vector(isa_irq); | |
995 | ||
996 | register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY, polarity, trigger); | |
997 | ||
998 | DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n", | |
999 | isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level", | |
1000 | polarity == IOSAPIC_POL_HIGH ? "high" : "low", | |
1001 | cpu_logical_id(dest), dest, vector); | |
1002 | ||
24eeb568 | 1003 | set_rte(gsi, vector, dest, 1); |
1da177e4 LT |
1004 | } |
1005 | ||
1006 | void __init | |
1007 | iosapic_system_init (int system_pcat_compat) | |
1008 | { | |
1009 | int vector; | |
1010 | ||
24eeb568 KK |
1011 | for (vector = 0; vector < IA64_NUM_VECTORS; ++vector) { |
1012 | iosapic_intr_info[vector].low32 = IOSAPIC_MASK; | |
46cba3dc ST |
1013 | /* mark as unused */ |
1014 | INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes); | |
24eeb568 | 1015 | } |
1da177e4 LT |
1016 | |
1017 | pcat_compat = system_pcat_compat; | |
1018 | if (pcat_compat) { | |
1019 | /* | |
46cba3dc ST |
1020 | * Disable the compatibility mode interrupts (8259 style), |
1021 | * needs IN/OUT support enabled. | |
1da177e4 | 1022 | */ |
46cba3dc ST |
1023 | printk(KERN_INFO |
1024 | "%s: Disabling PC-AT compatible 8259 interrupts\n", | |
1025 | __FUNCTION__); | |
1da177e4 LT |
1026 | outb(0xff, 0xA1); |
1027 | outb(0xff, 0x21); | |
1028 | } | |
1029 | } | |
1030 | ||
0e888adc KK |
1031 | static inline int |
1032 | iosapic_alloc (void) | |
1033 | { | |
1034 | int index; | |
1035 | ||
1036 | for (index = 0; index < NR_IOSAPICS; index++) | |
1037 | if (!iosapic_lists[index].addr) | |
1038 | return index; | |
1039 | ||
1040 | printk(KERN_WARNING "%s: failed to allocate iosapic\n", __FUNCTION__); | |
1041 | return -1; | |
1042 | } | |
1043 | ||
1044 | static inline void | |
1045 | iosapic_free (int index) | |
1046 | { | |
1047 | memset(&iosapic_lists[index], 0, sizeof(iosapic_lists[0])); | |
1048 | } | |
1049 | ||
1050 | static inline int | |
1051 | iosapic_check_gsi_range (unsigned int gsi_base, unsigned int ver) | |
1052 | { | |
1053 | int index; | |
1054 | unsigned int gsi_end, base, end; | |
1055 | ||
1056 | /* check gsi range */ | |
1057 | gsi_end = gsi_base + ((ver >> 16) & 0xff); | |
1058 | for (index = 0; index < NR_IOSAPICS; index++) { | |
1059 | if (!iosapic_lists[index].addr) | |
1060 | continue; | |
1061 | ||
1062 | base = iosapic_lists[index].gsi_base; | |
1063 | end = base + iosapic_lists[index].num_rte - 1; | |
1064 | ||
e6d1ba5c | 1065 | if (gsi_end < base || end < gsi_base) |
0e888adc KK |
1066 | continue; /* OK */ |
1067 | ||
1068 | return -EBUSY; | |
1069 | } | |
1070 | return 0; | |
1071 | } | |
1072 | ||
1073 | int __devinit | |
1da177e4 LT |
1074 | iosapic_init (unsigned long phys_addr, unsigned int gsi_base) |
1075 | { | |
0e888adc | 1076 | int num_rte, err, index; |
1da177e4 LT |
1077 | unsigned int isa_irq, ver; |
1078 | char __iomem *addr; | |
0e888adc KK |
1079 | unsigned long flags; |
1080 | ||
1081 | spin_lock_irqsave(&iosapic_lock, flags); | |
1082 | { | |
1083 | addr = ioremap(phys_addr, 0); | |
1084 | ver = iosapic_version(addr); | |
1da177e4 | 1085 | |
0e888adc KK |
1086 | if ((err = iosapic_check_gsi_range(gsi_base, ver))) { |
1087 | iounmap(addr); | |
1088 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1089 | return err; | |
1090 | } | |
1da177e4 | 1091 | |
0e888adc KK |
1092 | /* |
1093 | * The MAX_REDIR register holds the highest input pin | |
1094 | * number (starting from 0). | |
1095 | * We add 1 so that we can use it for number of pins (= RTEs) | |
1096 | */ | |
1097 | num_rte = ((ver >> 16) & 0xff) + 1; | |
1da177e4 | 1098 | |
0e888adc KK |
1099 | index = iosapic_alloc(); |
1100 | iosapic_lists[index].addr = addr; | |
1101 | iosapic_lists[index].gsi_base = gsi_base; | |
1102 | iosapic_lists[index].num_rte = num_rte; | |
1da177e4 | 1103 | #ifdef CONFIG_NUMA |
0e888adc | 1104 | iosapic_lists[index].node = MAX_NUMNODES; |
1da177e4 | 1105 | #endif |
0e888adc KK |
1106 | } |
1107 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1da177e4 LT |
1108 | |
1109 | if ((gsi_base == 0) && pcat_compat) { | |
1110 | /* | |
46cba3dc ST |
1111 | * Map the legacy ISA devices into the IOSAPIC data. Some of |
1112 | * these may get reprogrammed later on with data from the ACPI | |
1113 | * Interrupt Source Override table. | |
1da177e4 LT |
1114 | */ |
1115 | for (isa_irq = 0; isa_irq < 16; ++isa_irq) | |
46cba3dc ST |
1116 | iosapic_override_isa_irq(isa_irq, isa_irq, |
1117 | IOSAPIC_POL_HIGH, | |
1118 | IOSAPIC_EDGE); | |
1da177e4 | 1119 | } |
0e888adc KK |
1120 | return 0; |
1121 | } | |
1122 | ||
1123 | #ifdef CONFIG_HOTPLUG | |
1124 | int | |
1125 | iosapic_remove (unsigned int gsi_base) | |
1126 | { | |
1127 | int index, err = 0; | |
1128 | unsigned long flags; | |
1129 | ||
1130 | spin_lock_irqsave(&iosapic_lock, flags); | |
1131 | { | |
1132 | index = find_iosapic(gsi_base); | |
1133 | if (index < 0) { | |
1134 | printk(KERN_WARNING "%s: No IOSAPIC for GSI base %u\n", | |
1135 | __FUNCTION__, gsi_base); | |
1136 | goto out; | |
1137 | } | |
1138 | ||
1139 | if (iosapic_lists[index].rtes_inuse) { | |
1140 | err = -EBUSY; | |
46cba3dc ST |
1141 | printk(KERN_WARNING |
1142 | "%s: IOSAPIC for GSI base %u is busy\n", | |
0e888adc KK |
1143 | __FUNCTION__, gsi_base); |
1144 | goto out; | |
1145 | } | |
1146 | ||
1147 | iounmap(iosapic_lists[index].addr); | |
1148 | iosapic_free(index); | |
1149 | } | |
1150 | out: | |
1151 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1152 | return err; | |
1da177e4 | 1153 | } |
0e888adc | 1154 | #endif /* CONFIG_HOTPLUG */ |
1da177e4 LT |
1155 | |
1156 | #ifdef CONFIG_NUMA | |
0e888adc | 1157 | void __devinit |
1da177e4 LT |
1158 | map_iosapic_to_node(unsigned int gsi_base, int node) |
1159 | { | |
1160 | int index; | |
1161 | ||
1162 | index = find_iosapic(gsi_base); | |
1163 | if (index < 0) { | |
1164 | printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n", | |
1165 | __FUNCTION__, gsi_base); | |
1166 | return; | |
1167 | } | |
1168 | iosapic_lists[index].node = node; | |
1169 | return; | |
1170 | } | |
1171 | #endif | |
24eeb568 KK |
1172 | |
1173 | static int __init iosapic_enable_kmalloc (void) | |
1174 | { | |
1175 | iosapic_kmalloc_ok = 1; | |
1176 | return 0; | |
1177 | } | |
1178 | core_initcall (iosapic_enable_kmalloc); |