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License cleanup: add SPDX GPL-2.0 license identifier to files with no license
[linux-2.6-block.git] / arch / cris / include / arch-v32 / mach-a3 / mach / hwregs / iop / iop_sw_cpu_defs.h
CommitLineData
b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
58d08319
JN		 2#ifndef __iop_sw_cpu_defs_h
3#define __iop_sw_cpu_defs_h
4
5/*
6 * This file is autogenerated from
7 * file: iop_sw_cpu.r
8 *
9 * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cpu_defs.h iop_sw_cpu.r
10 * Any changes here will be lost.
11 *
12 * -*- buffer-read-only: t -*-
13 */
14/* Main access macros */
15#ifndef REG_RD
16#define REG_RD( scope, inst, reg ) \
17 REG_READ( reg_##scope##_##reg, \
18 (inst) + REG_RD_ADDR_##scope##_##reg )
19#endif
20
21#ifndef REG_WR
22#define REG_WR( scope, inst, reg, val ) \
23 REG_WRITE( reg_##scope##_##reg, \
24 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
25#endif
26
27#ifndef REG_RD_VECT
28#define REG_RD_VECT( scope, inst, reg, index ) \
29 REG_READ( reg_##scope##_##reg, \
30 (inst) + REG_RD_ADDR_##scope##_##reg + \
31 (index) * STRIDE_##scope##_##reg )
32#endif
33
34#ifndef REG_WR_VECT
35#define REG_WR_VECT( scope, inst, reg, index, val ) \
36 REG_WRITE( reg_##scope##_##reg, \
37 (inst) + REG_WR_ADDR_##scope##_##reg + \
38 (index) * STRIDE_##scope##_##reg, (val) )
39#endif
40
41#ifndef REG_RD_INT
42#define REG_RD_INT( scope, inst, reg ) \
43 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
44#endif
45
46#ifndef REG_WR_INT
47#define REG_WR_INT( scope, inst, reg, val ) \
48 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
49#endif
50
51#ifndef REG_RD_INT_VECT
52#define REG_RD_INT_VECT( scope, inst, reg, index ) \
53 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
54 (index) * STRIDE_##scope##_##reg )
55#endif
56
57#ifndef REG_WR_INT_VECT
58#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
59 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
60 (index) * STRIDE_##scope##_##reg, (val) )
61#endif
62
63#ifndef REG_TYPE_CONV
64#define REG_TYPE_CONV( type, orgtype, val ) \
65 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
66#endif
67
68#ifndef reg_page_size
69#define reg_page_size 8192
70#endif
71
72#ifndef REG_ADDR
73#define REG_ADDR( scope, inst, reg ) \
74 ( (inst) + REG_RD_ADDR_##scope##_##reg )
75#endif
76
77#ifndef REG_ADDR_VECT
78#define REG_ADDR_VECT( scope, inst, reg, index ) \
79 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
80 (index) * STRIDE_##scope##_##reg )
81#endif
82
83/* C-code for register scope iop_sw_cpu */
84
85/* Register r_mpu_trace, scope iop_sw_cpu, type r */
86typedef unsigned int reg_iop_sw_cpu_r_mpu_trace;
87#define REG_RD_ADDR_iop_sw_cpu_r_mpu_trace 0
88
89/* Register r_spu_trace, scope iop_sw_cpu, type r */
90typedef unsigned int reg_iop_sw_cpu_r_spu_trace;
91#define REG_RD_ADDR_iop_sw_cpu_r_spu_trace 4
92
93/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */
94typedef unsigned int reg_iop_sw_cpu_r_spu_fsm_trace;
95#define REG_RD_ADDR_iop_sw_cpu_r_spu_fsm_trace 8
96
97/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
98typedef struct {
99 unsigned int keep_owner : 1;
100 unsigned int cmd : 2;
101 unsigned int size : 3;
102 unsigned int wr_spu_mem : 1;
103 unsigned int dummy1 : 25;
104} reg_iop_sw_cpu_rw_mc_ctrl;
105#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 12
106#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 12
107
108/* Register rw_mc_data, scope iop_sw_cpu, type rw */
109typedef struct {
110 unsigned int val : 32;
111} reg_iop_sw_cpu_rw_mc_data;
112#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 16
113#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 16
114
115/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
116typedef unsigned int reg_iop_sw_cpu_rw_mc_addr;
117#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 20
118#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 20
119
120/* Register rs_mc_data, scope iop_sw_cpu, type rs */
121typedef unsigned int reg_iop_sw_cpu_rs_mc_data;
122#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 24
123
124/* Register r_mc_data, scope iop_sw_cpu, type r */
125typedef unsigned int reg_iop_sw_cpu_r_mc_data;
126#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 28
127
128/* Register r_mc_stat, scope iop_sw_cpu, type r */
129typedef struct {
130 unsigned int busy_cpu : 1;
131 unsigned int busy_mpu : 1;
132 unsigned int busy_spu : 1;
133 unsigned int owned_by_cpu : 1;
134 unsigned int owned_by_mpu : 1;
135 unsigned int owned_by_spu : 1;
136 unsigned int dummy1 : 26;
137} reg_iop_sw_cpu_r_mc_stat;
138#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 32
139
140/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */
141typedef struct {
142 unsigned int byte0 : 8;
143 unsigned int byte1 : 8;
144 unsigned int byte2 : 8;
145 unsigned int byte3 : 8;
146} reg_iop_sw_cpu_rw_bus_clr_mask;
147#define REG_RD_ADDR_iop_sw_cpu_rw_bus_clr_mask 36
148#define REG_WR_ADDR_iop_sw_cpu_rw_bus_clr_mask 36
149
150/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */
151typedef struct {
152 unsigned int byte0 : 8;
153 unsigned int byte1 : 8;
154 unsigned int byte2 : 8;
155 unsigned int byte3 : 8;
156} reg_iop_sw_cpu_rw_bus_set_mask;
157#define REG_RD_ADDR_iop_sw_cpu_rw_bus_set_mask 40
158#define REG_WR_ADDR_iop_sw_cpu_rw_bus_set_mask 40
159
160/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */
161typedef struct {
162 unsigned int byte0 : 1;
163 unsigned int byte1 : 1;
164 unsigned int byte2 : 1;
165 unsigned int byte3 : 1;
166 unsigned int dummy1 : 28;
167} reg_iop_sw_cpu_rw_bus_oe_clr_mask;
168#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44
169#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44
170
171/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */
172typedef struct {
173 unsigned int byte0 : 1;
174 unsigned int byte1 : 1;
175 unsigned int byte2 : 1;
176 unsigned int byte3 : 1;
177 unsigned int dummy1 : 28;
178} reg_iop_sw_cpu_rw_bus_oe_set_mask;
179#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48
180#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48
181
182/* Register r_bus_in, scope iop_sw_cpu, type r */
183typedef unsigned int reg_iop_sw_cpu_r_bus_in;
184#define REG_RD_ADDR_iop_sw_cpu_r_bus_in 52
185
186/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
187typedef struct {
188 unsigned int val : 32;
189} reg_iop_sw_cpu_rw_gio_clr_mask;
190#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 56
191#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 56
192
193/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
194typedef struct {
195 unsigned int val : 32;
196} reg_iop_sw_cpu_rw_gio_set_mask;
197#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 60
198#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 60
199
200/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
201typedef struct {
202 unsigned int val : 32;
203} reg_iop_sw_cpu_rw_gio_oe_clr_mask;
204#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64
205#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64
206
207/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
208typedef struct {
209 unsigned int val : 32;
210} reg_iop_sw_cpu_rw_gio_oe_set_mask;
211#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68
212#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68
213
214/* Register r_gio_in, scope iop_sw_cpu, type r */
215typedef unsigned int reg_iop_sw_cpu_r_gio_in;
216#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 72
217
218/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
219typedef struct {
220 unsigned int mpu_0 : 1;
221 unsigned int mpu_1 : 1;
222 unsigned int mpu_2 : 1;
223 unsigned int mpu_3 : 1;
224 unsigned int mpu_4 : 1;
225 unsigned int mpu_5 : 1;
226 unsigned int mpu_6 : 1;
227 unsigned int mpu_7 : 1;
228 unsigned int mpu_8 : 1;
229 unsigned int mpu_9 : 1;
230 unsigned int mpu_10 : 1;
231 unsigned int mpu_11 : 1;
232 unsigned int mpu_12 : 1;
233 unsigned int mpu_13 : 1;
234 unsigned int mpu_14 : 1;
235 unsigned int mpu_15 : 1;
236 unsigned int spu_0 : 1;
237 unsigned int spu_1 : 1;
238 unsigned int spu_2 : 1;
239 unsigned int spu_3 : 1;
240 unsigned int spu_4 : 1;
241 unsigned int spu_5 : 1;
242 unsigned int spu_6 : 1;
243 unsigned int spu_7 : 1;
244 unsigned int spu_8 : 1;
245 unsigned int spu_9 : 1;
246 unsigned int spu_10 : 1;
247 unsigned int spu_11 : 1;
248 unsigned int spu_12 : 1;
249 unsigned int spu_13 : 1;
250 unsigned int spu_14 : 1;
251 unsigned int spu_15 : 1;
252} reg_iop_sw_cpu_rw_intr0_mask;
253#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 76
254#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 76
255
256/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
257typedef struct {
258 unsigned int mpu_0 : 1;
259 unsigned int mpu_1 : 1;
260 unsigned int mpu_2 : 1;
261 unsigned int mpu_3 : 1;
262 unsigned int mpu_4 : 1;
263 unsigned int mpu_5 : 1;
264 unsigned int mpu_6 : 1;
265 unsigned int mpu_7 : 1;
266 unsigned int mpu_8 : 1;
267 unsigned int mpu_9 : 1;
268 unsigned int mpu_10 : 1;
269 unsigned int mpu_11 : 1;
270 unsigned int mpu_12 : 1;
271 unsigned int mpu_13 : 1;
272 unsigned int mpu_14 : 1;
273 unsigned int mpu_15 : 1;
274 unsigned int spu_0 : 1;
275 unsigned int spu_1 : 1;
276 unsigned int spu_2 : 1;
277 unsigned int spu_3 : 1;
278 unsigned int spu_4 : 1;
279 unsigned int spu_5 : 1;
280 unsigned int spu_6 : 1;
281 unsigned int spu_7 : 1;
282 unsigned int spu_8 : 1;
283 unsigned int spu_9 : 1;
284 unsigned int spu_10 : 1;
285 unsigned int spu_11 : 1;
286 unsigned int spu_12 : 1;
287 unsigned int spu_13 : 1;
288 unsigned int spu_14 : 1;
289 unsigned int spu_15 : 1;
290} reg_iop_sw_cpu_rw_ack_intr0;
291#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 80
292#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 80
293
294/* Register r_intr0, scope iop_sw_cpu, type r */
295typedef struct {
296 unsigned int mpu_0 : 1;
297 unsigned int mpu_1 : 1;
298 unsigned int mpu_2 : 1;
299 unsigned int mpu_3 : 1;
300 unsigned int mpu_4 : 1;
301 unsigned int mpu_5 : 1;
302 unsigned int mpu_6 : 1;
303 unsigned int mpu_7 : 1;
304 unsigned int mpu_8 : 1;
305 unsigned int mpu_9 : 1;
306 unsigned int mpu_10 : 1;
307 unsigned int mpu_11 : 1;
308 unsigned int mpu_12 : 1;
309 unsigned int mpu_13 : 1;
310 unsigned int mpu_14 : 1;
311 unsigned int mpu_15 : 1;
312 unsigned int spu_0 : 1;
313 unsigned int spu_1 : 1;
314 unsigned int spu_2 : 1;
315 unsigned int spu_3 : 1;
316 unsigned int spu_4 : 1;
317 unsigned int spu_5 : 1;
318 unsigned int spu_6 : 1;
319 unsigned int spu_7 : 1;
320 unsigned int spu_8 : 1;
321 unsigned int spu_9 : 1;
322 unsigned int spu_10 : 1;
323 unsigned int spu_11 : 1;
324 unsigned int spu_12 : 1;
325 unsigned int spu_13 : 1;
326 unsigned int spu_14 : 1;
327 unsigned int spu_15 : 1;
328} reg_iop_sw_cpu_r_intr0;
329#define REG_RD_ADDR_iop_sw_cpu_r_intr0 84
330
331/* Register r_masked_intr0, scope iop_sw_cpu, type r */
332typedef struct {
333 unsigned int mpu_0 : 1;
334 unsigned int mpu_1 : 1;
335 unsigned int mpu_2 : 1;
336 unsigned int mpu_3 : 1;
337 unsigned int mpu_4 : 1;
338 unsigned int mpu_5 : 1;
339 unsigned int mpu_6 : 1;
340 unsigned int mpu_7 : 1;
341 unsigned int mpu_8 : 1;
342 unsigned int mpu_9 : 1;
343 unsigned int mpu_10 : 1;
344 unsigned int mpu_11 : 1;
345 unsigned int mpu_12 : 1;
346 unsigned int mpu_13 : 1;
347 unsigned int mpu_14 : 1;
348 unsigned int mpu_15 : 1;
349 unsigned int spu_0 : 1;
350 unsigned int spu_1 : 1;
351 unsigned int spu_2 : 1;
352 unsigned int spu_3 : 1;
353 unsigned int spu_4 : 1;
354 unsigned int spu_5 : 1;
355 unsigned int spu_6 : 1;
356 unsigned int spu_7 : 1;
357 unsigned int spu_8 : 1;
358 unsigned int spu_9 : 1;
359 unsigned int spu_10 : 1;
360 unsigned int spu_11 : 1;
361 unsigned int spu_12 : 1;
362 unsigned int spu_13 : 1;
363 unsigned int spu_14 : 1;
364 unsigned int spu_15 : 1;
365} reg_iop_sw_cpu_r_masked_intr0;
366#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 88
367
368/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
369typedef struct {
370 unsigned int mpu_16 : 1;
371 unsigned int mpu_17 : 1;
372 unsigned int mpu_18 : 1;
373 unsigned int mpu_19 : 1;
374 unsigned int mpu_20 : 1;
375 unsigned int mpu_21 : 1;
376 unsigned int mpu_22 : 1;
377 unsigned int mpu_23 : 1;
378 unsigned int mpu_24 : 1;
379 unsigned int mpu_25 : 1;
380 unsigned int mpu_26 : 1;
381 unsigned int mpu_27 : 1;
382 unsigned int mpu_28 : 1;
383 unsigned int mpu_29 : 1;
384 unsigned int mpu_30 : 1;
385 unsigned int mpu_31 : 1;
386 unsigned int dmc_in : 1;
387 unsigned int dmc_out : 1;
388 unsigned int fifo_in : 1;
389 unsigned int fifo_out : 1;
390 unsigned int fifo_in_extra : 1;
391 unsigned int fifo_out_extra : 1;
392 unsigned int trigger_grp0 : 1;
393 unsigned int trigger_grp1 : 1;
394 unsigned int trigger_grp2 : 1;
395 unsigned int trigger_grp3 : 1;
396 unsigned int trigger_grp4 : 1;
397 unsigned int trigger_grp5 : 1;
398 unsigned int trigger_grp6 : 1;
399 unsigned int trigger_grp7 : 1;
400 unsigned int timer_grp0 : 1;
401 unsigned int timer_grp1 : 1;
402} reg_iop_sw_cpu_rw_intr1_mask;
403#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 92
404#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 92
405
406/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
407typedef struct {
408 unsigned int mpu_16 : 1;
409 unsigned int mpu_17 : 1;
410 unsigned int mpu_18 : 1;
411 unsigned int mpu_19 : 1;
412 unsigned int mpu_20 : 1;
413 unsigned int mpu_21 : 1;
414 unsigned int mpu_22 : 1;
415 unsigned int mpu_23 : 1;
416 unsigned int mpu_24 : 1;
417 unsigned int mpu_25 : 1;
418 unsigned int mpu_26 : 1;
419 unsigned int mpu_27 : 1;
420 unsigned int mpu_28 : 1;
421 unsigned int mpu_29 : 1;
422 unsigned int mpu_30 : 1;
423 unsigned int mpu_31 : 1;
424 unsigned int dummy1 : 16;
425} reg_iop_sw_cpu_rw_ack_intr1;
426#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 96
427#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 96
428
429/* Register r_intr1, scope iop_sw_cpu, type r */
430typedef struct {
431 unsigned int mpu_16 : 1;
432 unsigned int mpu_17 : 1;
433 unsigned int mpu_18 : 1;
434 unsigned int mpu_19 : 1;
435 unsigned int mpu_20 : 1;
436 unsigned int mpu_21 : 1;
437 unsigned int mpu_22 : 1;
438 unsigned int mpu_23 : 1;
439 unsigned int mpu_24 : 1;
440 unsigned int mpu_25 : 1;
441 unsigned int mpu_26 : 1;
442 unsigned int mpu_27 : 1;
443 unsigned int mpu_28 : 1;
444 unsigned int mpu_29 : 1;
445 unsigned int mpu_30 : 1;
446 unsigned int mpu_31 : 1;
447 unsigned int dmc_in : 1;
448 unsigned int dmc_out : 1;
449 unsigned int fifo_in : 1;
450 unsigned int fifo_out : 1;
451 unsigned int fifo_in_extra : 1;
452 unsigned int fifo_out_extra : 1;
453 unsigned int trigger_grp0 : 1;
454 unsigned int trigger_grp1 : 1;
455 unsigned int trigger_grp2 : 1;
456 unsigned int trigger_grp3 : 1;
457 unsigned int trigger_grp4 : 1;
458 unsigned int trigger_grp5 : 1;
459 unsigned int trigger_grp6 : 1;
460 unsigned int trigger_grp7 : 1;
461 unsigned int timer_grp0 : 1;
462 unsigned int timer_grp1 : 1;
463} reg_iop_sw_cpu_r_intr1;
464#define REG_RD_ADDR_iop_sw_cpu_r_intr1 100
465
466/* Register r_masked_intr1, scope iop_sw_cpu, type r */
467typedef struct {
468 unsigned int mpu_16 : 1;
469 unsigned int mpu_17 : 1;
470 unsigned int mpu_18 : 1;
471 unsigned int mpu_19 : 1;
472 unsigned int mpu_20 : 1;
473 unsigned int mpu_21 : 1;
474 unsigned int mpu_22 : 1;
475 unsigned int mpu_23 : 1;
476 unsigned int mpu_24 : 1;
477 unsigned int mpu_25 : 1;
478 unsigned int mpu_26 : 1;
479 unsigned int mpu_27 : 1;
480 unsigned int mpu_28 : 1;
481 unsigned int mpu_29 : 1;
482 unsigned int mpu_30 : 1;
483 unsigned int mpu_31 : 1;
484 unsigned int dmc_in : 1;
485 unsigned int dmc_out : 1;
486 unsigned int fifo_in : 1;
487 unsigned int fifo_out : 1;
488 unsigned int fifo_in_extra : 1;
489 unsigned int fifo_out_extra : 1;
490 unsigned int trigger_grp0 : 1;
491 unsigned int trigger_grp1 : 1;
492 unsigned int trigger_grp2 : 1;
493 unsigned int trigger_grp3 : 1;
494 unsigned int trigger_grp4 : 1;
495 unsigned int trigger_grp5 : 1;
496 unsigned int trigger_grp6 : 1;
497 unsigned int trigger_grp7 : 1;
498 unsigned int timer_grp0 : 1;
499 unsigned int timer_grp1 : 1;
500} reg_iop_sw_cpu_r_masked_intr1;
501#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 104
502
503
504/* Constants */
505enum {
506 regk_iop_sw_cpu_copy = 0x00000000,
507 regk_iop_sw_cpu_no = 0x00000000,
508 regk_iop_sw_cpu_rd = 0x00000002,
509 regk_iop_sw_cpu_reg_copy = 0x00000001,
510 regk_iop_sw_cpu_rw_bus_clr_mask_default = 0x00000000,
511 regk_iop_sw_cpu_rw_bus_oe_clr_mask_default = 0x00000000,
512 regk_iop_sw_cpu_rw_bus_oe_set_mask_default = 0x00000000,
513 regk_iop_sw_cpu_rw_bus_set_mask_default = 0x00000000,
514 regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000,
515 regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000,
516 regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000,
517 regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000,
518 regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000,
519 regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000,
520 regk_iop_sw_cpu_wr = 0x00000003,
521 regk_iop_sw_cpu_yes = 0x00000001
522};
523#endif /* __iop_sw_cpu_defs_h */
Linux 6.x block layer and io_uring tree(s)