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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
51533b61 MS |
2 | #ifndef __iop_mpu_defs_h |
3 | #define __iop_mpu_defs_h | |
4 | ||
5 | /* | |
6 | * This file is autogenerated from | |
7 | * file: ../../inst/io_proc/rtl/iop_mpu.r | |
8 | * id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp | |
9 | * last modfied: Mon Apr 11 16:08:45 2005 | |
10 | * | |
11 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_mpu_defs.h ../../inst/io_proc/rtl/iop_mpu.r | |
12 | * id: $Id: iop_mpu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ | |
13 | * Any changes here will be lost. | |
14 | * | |
15 | * -*- buffer-read-only: t -*- | |
16 | */ | |
17 | /* Main access macros */ | |
18 | #ifndef REG_RD | |
19 | #define REG_RD( scope, inst, reg ) \ | |
20 | REG_READ( reg_##scope##_##reg, \ | |
21 | (inst) + REG_RD_ADDR_##scope##_##reg ) | |
22 | #endif | |
23 | ||
24 | #ifndef REG_WR | |
25 | #define REG_WR( scope, inst, reg, val ) \ | |
26 | REG_WRITE( reg_##scope##_##reg, \ | |
27 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
28 | #endif | |
29 | ||
30 | #ifndef REG_RD_VECT | |
31 | #define REG_RD_VECT( scope, inst, reg, index ) \ | |
32 | REG_READ( reg_##scope##_##reg, \ | |
33 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
34 | (index) * STRIDE_##scope##_##reg ) | |
35 | #endif | |
36 | ||
37 | #ifndef REG_WR_VECT | |
38 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | |
39 | REG_WRITE( reg_##scope##_##reg, \ | |
40 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
41 | (index) * STRIDE_##scope##_##reg, (val) ) | |
42 | #endif | |
43 | ||
44 | #ifndef REG_RD_INT | |
45 | #define REG_RD_INT( scope, inst, reg ) \ | |
46 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | |
47 | #endif | |
48 | ||
49 | #ifndef REG_WR_INT | |
50 | #define REG_WR_INT( scope, inst, reg, val ) \ | |
51 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
52 | #endif | |
53 | ||
54 | #ifndef REG_RD_INT_VECT | |
55 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | |
56 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
57 | (index) * STRIDE_##scope##_##reg ) | |
58 | #endif | |
59 | ||
60 | #ifndef REG_WR_INT_VECT | |
61 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | |
62 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
63 | (index) * STRIDE_##scope##_##reg, (val) ) | |
64 | #endif | |
65 | ||
66 | #ifndef REG_TYPE_CONV | |
67 | #define REG_TYPE_CONV( type, orgtype, val ) \ | |
68 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | |
69 | #endif | |
70 | ||
71 | #ifndef reg_page_size | |
72 | #define reg_page_size 8192 | |
73 | #endif | |
74 | ||
75 | #ifndef REG_ADDR | |
76 | #define REG_ADDR( scope, inst, reg ) \ | |
77 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | |
78 | #endif | |
79 | ||
80 | #ifndef REG_ADDR_VECT | |
81 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
82 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
83 | (index) * STRIDE_##scope##_##reg ) | |
84 | #endif | |
85 | ||
86 | /* C-code for register scope iop_mpu */ | |
87 | ||
88 | #define STRIDE_iop_mpu_rw_r 4 | |
89 | /* Register rw_r, scope iop_mpu, type rw */ | |
90 | typedef unsigned int reg_iop_mpu_rw_r; | |
91 | #define REG_RD_ADDR_iop_mpu_rw_r 0 | |
92 | #define REG_WR_ADDR_iop_mpu_rw_r 0 | |
93 | ||
94 | /* Register rw_ctrl, scope iop_mpu, type rw */ | |
95 | typedef struct { | |
96 | unsigned int en : 1; | |
97 | unsigned int dummy1 : 31; | |
98 | } reg_iop_mpu_rw_ctrl; | |
99 | #define REG_RD_ADDR_iop_mpu_rw_ctrl 128 | |
100 | #define REG_WR_ADDR_iop_mpu_rw_ctrl 128 | |
101 | ||
102 | /* Register r_pc, scope iop_mpu, type r */ | |
103 | typedef struct { | |
104 | unsigned int addr : 12; | |
105 | unsigned int dummy1 : 20; | |
106 | } reg_iop_mpu_r_pc; | |
107 | #define REG_RD_ADDR_iop_mpu_r_pc 132 | |
108 | ||
109 | /* Register r_stat, scope iop_mpu, type r */ | |
110 | typedef struct { | |
111 | unsigned int instr_reg_busy : 1; | |
112 | unsigned int intr_busy : 1; | |
113 | unsigned int intr_vect : 16; | |
114 | unsigned int dummy1 : 14; | |
115 | } reg_iop_mpu_r_stat; | |
116 | #define REG_RD_ADDR_iop_mpu_r_stat 136 | |
117 | ||
118 | /* Register rw_instr, scope iop_mpu, type rw */ | |
119 | typedef unsigned int reg_iop_mpu_rw_instr; | |
120 | #define REG_RD_ADDR_iop_mpu_rw_instr 140 | |
121 | #define REG_WR_ADDR_iop_mpu_rw_instr 140 | |
122 | ||
123 | /* Register rw_immediate, scope iop_mpu, type rw */ | |
124 | typedef unsigned int reg_iop_mpu_rw_immediate; | |
125 | #define REG_RD_ADDR_iop_mpu_rw_immediate 144 | |
126 | #define REG_WR_ADDR_iop_mpu_rw_immediate 144 | |
127 | ||
128 | /* Register r_trace, scope iop_mpu, type r */ | |
129 | typedef struct { | |
130 | unsigned int intr_vect : 16; | |
131 | unsigned int pc : 12; | |
132 | unsigned int en : 1; | |
133 | unsigned int instr_reg_busy : 1; | |
134 | unsigned int intr_busy : 1; | |
135 | unsigned int dummy1 : 1; | |
136 | } reg_iop_mpu_r_trace; | |
137 | #define REG_RD_ADDR_iop_mpu_r_trace 148 | |
138 | ||
139 | /* Register r_wr_stat, scope iop_mpu, type r */ | |
140 | typedef struct { | |
141 | unsigned int r0 : 1; | |
142 | unsigned int r1 : 1; | |
143 | unsigned int r2 : 1; | |
144 | unsigned int r3 : 1; | |
145 | unsigned int r4 : 1; | |
146 | unsigned int r5 : 1; | |
147 | unsigned int r6 : 1; | |
148 | unsigned int r7 : 1; | |
149 | unsigned int r8 : 1; | |
150 | unsigned int r9 : 1; | |
151 | unsigned int r10 : 1; | |
152 | unsigned int r11 : 1; | |
153 | unsigned int r12 : 1; | |
154 | unsigned int r13 : 1; | |
155 | unsigned int r14 : 1; | |
156 | unsigned int r15 : 1; | |
157 | unsigned int dummy1 : 16; | |
158 | } reg_iop_mpu_r_wr_stat; | |
159 | #define REG_RD_ADDR_iop_mpu_r_wr_stat 152 | |
160 | ||
161 | #define STRIDE_iop_mpu_rw_thread 4 | |
162 | /* Register rw_thread, scope iop_mpu, type rw */ | |
163 | typedef struct { | |
164 | unsigned int addr : 12; | |
165 | unsigned int dummy1 : 20; | |
166 | } reg_iop_mpu_rw_thread; | |
167 | #define REG_RD_ADDR_iop_mpu_rw_thread 156 | |
168 | #define REG_WR_ADDR_iop_mpu_rw_thread 156 | |
169 | ||
170 | #define STRIDE_iop_mpu_rw_intr 4 | |
171 | /* Register rw_intr, scope iop_mpu, type rw */ | |
172 | typedef struct { | |
173 | unsigned int addr : 12; | |
174 | unsigned int dummy1 : 20; | |
175 | } reg_iop_mpu_rw_intr; | |
176 | #define REG_RD_ADDR_iop_mpu_rw_intr 196 | |
177 | #define REG_WR_ADDR_iop_mpu_rw_intr 196 | |
178 | ||
179 | ||
180 | /* Constants */ | |
181 | enum { | |
182 | regk_iop_mpu_no = 0x00000000, | |
183 | regk_iop_mpu_r_pc_default = 0x00000000, | |
184 | regk_iop_mpu_rw_ctrl_default = 0x00000000, | |
185 | regk_iop_mpu_rw_intr_size = 0x00000010, | |
186 | regk_iop_mpu_rw_r_size = 0x00000010, | |
187 | regk_iop_mpu_rw_thread_default = 0x00000000, | |
188 | regk_iop_mpu_rw_thread_size = 0x00000004, | |
189 | regk_iop_mpu_yes = 0x00000001 | |
190 | }; | |
191 | #endif /* __iop_mpu_defs_h */ |