[linux-2.6-block.git] / arch / blackfin / mach-common / smp.c

/*
 * IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
 *
 * Copyright 2007-2009 Analog Devices Inc.
 *                         Philippe Gerum <rpm@xenomai.org>
 *
 * Licensed under the GPL-2.
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/cache.h>
#include <linux/clockchips.h>
#include <linux/profile.h>
#include <linux/errno.h>
#include <linux/mm.h>
#include <linux/cpu.h>
#include <linux/smp.h>
#include <linux/cpumask.h>
#include <linux/seq_file.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/atomic.h>
#include <asm/cacheflush.h>
#include <asm/irq_handler.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/pgalloc.h>
#include <asm/processor.h>
#include <asm/ptrace.h>
#include <asm/cpu.h>
#include <asm/time.h>
#include <linux/err.h>

/*
 * Anomaly notes:
 * 05000120 - we always define corelock as 32-bit integer in L2
 */
struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));

#ifdef CONFIG_ICACHE_FLUSH_L1
unsigned long blackfin_iflush_l1_entry[NR_CPUS];
#endif

struct blackfin_initial_pda initial_pda_coreb;

enum ipi_message_type {
	BFIN_IPI_NONE,
	BFIN_IPI_TIMER,
	BFIN_IPI_RESCHEDULE,
	BFIN_IPI_CALL_FUNC,
	BFIN_IPI_CPU_STOP,
};

struct blackfin_flush_data {
	unsigned long start;
	unsigned long end;
};

void *secondary_stack;

static struct blackfin_flush_data smp_flush_data;

static DEFINE_SPINLOCK(stop_lock);

/* A magic number - stress test shows this is safe for common cases */
#define BFIN_IPI_MSGQ_LEN 5

/* Simple FIFO buffer, overflow leads to panic */
struct ipi_data {
	atomic_t count;
	atomic_t bits;
};

static DEFINE_PER_CPU(struct ipi_data, bfin_ipi);

static void ipi_cpu_stop(unsigned int cpu)
{
	spin_lock(&stop_lock);
	printk(KERN_CRIT "CPU%u: stopping\n", cpu);
	dump_stack();
	spin_unlock(&stop_lock);

	set_cpu_online(cpu, false);

	local_irq_disable();

	while (1)
		SSYNC();
}

static void ipi_flush_icache(void *info)
{
	struct blackfin_flush_data *fdata = info;

	/* Invalidate the memory holding the bounds of the flushed region. */
	blackfin_dcache_invalidate_range((unsigned long)fdata,
					 (unsigned long)fdata + sizeof(*fdata));

	/* Make sure all write buffers in the data side of the core
	 * are flushed before trying to invalidate the icache.  This
	 * needs to be after the data flush and before the icache
	 * flush so that the SSYNC does the right thing in preventing
	 * the instruction prefetcher from hitting things in cached
	 * memory at the wrong time -- it runs much further ahead than
	 * the pipeline.
	 */
	SSYNC();

	/* ipi_flaush_icache is invoked by generic flush_icache_range,
	 * so call blackfin arch icache flush directly here.
	 */
	blackfin_icache_flush_range(fdata->start, fdata->end);
}

/* Use IRQ_SUPPLE_0 to request reschedule.
 * When returning from interrupt to user space,
 * there is chance to reschedule */
static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
{
	unsigned int cpu = smp_processor_id();

	platform_clear_ipi(cpu, IRQ_SUPPLE_0);
	return IRQ_HANDLED;
}

DECLARE_PER_CPU(struct clock_event_device, coretmr_events);
void ipi_timer(void)
{
	int cpu = smp_processor_id();
	struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
	evt->event_handler(evt);
}

static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
{
	struct ipi_data *bfin_ipi_data;
	unsigned int cpu = smp_processor_id();
	unsigned long pending;
	unsigned long msg;

	platform_clear_ipi(cpu, IRQ_SUPPLE_1);

	smp_rmb();
	bfin_ipi_data = this_cpu_ptr(&bfin_ipi);
	while ((pending = atomic_xchg(&bfin_ipi_data->bits, 0)) != 0) {
		msg = 0;
		do {
			msg = find_next_bit(&pending, BITS_PER_LONG, msg + 1);
			switch (msg) {
			case BFIN_IPI_TIMER:
				ipi_timer();
				break;
			case BFIN_IPI_RESCHEDULE:
				scheduler_ipi();
				break;
			case BFIN_IPI_CALL_FUNC:
				generic_smp_call_function_interrupt();
				break;
			case BFIN_IPI_CPU_STOP:
				ipi_cpu_stop(cpu);
				break;
			default:
				goto out;
			}
			atomic_dec(&bfin_ipi_data->count);
		} while (msg < BITS_PER_LONG);

	}
out:
	return IRQ_HANDLED;
}

static void bfin_ipi_init(void)
{
	unsigned int cpu;
	struct ipi_data *bfin_ipi_data;
	for_each_possible_cpu(cpu) {
		bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
		atomic_set(&bfin_ipi_data->bits, 0);
		atomic_set(&bfin_ipi_data->count, 0);
	}
}

void send_ipi(const struct cpumask *cpumask, enum ipi_message_type msg)
{
	unsigned int cpu;
	struct ipi_data *bfin_ipi_data;
	unsigned long flags;

	local_irq_save(flags);
	for_each_cpu(cpu, cpumask) {
		bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
		atomic_or((1 << msg), &bfin_ipi_data->bits);
		atomic_inc(&bfin_ipi_data->count);
	}
	local_irq_restore(flags);
	smp_wmb();
	for_each_cpu(cpu, cpumask)
		platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
}

void arch_send_call_function_single_ipi(int cpu)
{
	send_ipi(cpumask_of(cpu), BFIN_IPI_CALL_FUNC);
}

void arch_send_call_function_ipi_mask(const struct cpumask *mask)
{
	send_ipi(mask, BFIN_IPI_CALL_FUNC);
}

void smp_send_reschedule(int cpu)
{
	send_ipi(cpumask_of(cpu), BFIN_IPI_RESCHEDULE);

	return;
}

void smp_send_msg(const struct cpumask *mask, unsigned long type)
{
	send_ipi(mask, type);
}

void smp_timer_broadcast(const struct cpumask *mask)
{
	smp_send_msg(mask, BFIN_IPI_TIMER);
}

void smp_send_stop(void)
{
	cpumask_t callmap;

	preempt_disable();
	cpumask_copy(&callmap, cpu_online_mask);
	cpumask_clear_cpu(smp_processor_id(), &callmap);
	if (!cpumask_empty(&callmap))
		send_ipi(&callmap, BFIN_IPI_CPU_STOP);

	preempt_enable();

	return;
}

int __cpu_up(unsigned int cpu, struct task_struct *idle)
{
	int ret;

	secondary_stack = task_stack_page(idle) + THREAD_SIZE;

	ret = platform_boot_secondary(cpu, idle);

	secondary_stack = NULL;

	return ret;
}

static void setup_secondary(unsigned int cpu)
{
	unsigned long ilat;

	bfin_write_IMASK(0);
	CSYNC();
	ilat = bfin_read_ILAT();
	CSYNC();
	bfin_write_ILAT(ilat);
	CSYNC();

	/* Enable interrupt levels IVG7-15. IARs have been already
	 * programmed by the boot CPU.  */
	bfin_irq_flags |= IMASK_IVG15 |
	    IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
	    IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
}

void secondary_start_kernel(void)
{
	unsigned int cpu = smp_processor_id();
	struct mm_struct *mm = &init_mm;

	if (_bfin_swrst & SWRST_DBL_FAULT_B) {
		printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
#ifdef CONFIG_DEBUG_DOUBLEFAULT
		printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n",
			initial_pda_coreb.seqstat_doublefault & SEQSTAT_EXCAUSE,
			initial_pda_coreb.retx_doublefault);
		printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n",
			initial_pda_coreb.dcplb_doublefault_addr);
		printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n",
			initial_pda_coreb.icplb_doublefault_addr);
#endif
		printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
			initial_pda_coreb.retx);
	}

	/*
	 * We want the D-cache to be enabled early, in case the atomic
	 * support code emulates cache coherence (see
	 * __ARCH_SYNC_CORE_DCACHE).
	 */
	init_exception_vectors();

	local_irq_disable();

	/* Attach the new idle task to the global mm. */
	atomic_inc(&mm->mm_users);
	atomic_inc(&mm->mm_count);
	current->active_mm = mm;

	preempt_disable();

	setup_secondary(cpu);

	platform_secondary_init(cpu);
	/* setup local core timer */
	bfin_local_timer_setup();

	local_irq_enable();

	bfin_setup_caches(cpu);

	notify_cpu_starting(cpu);
	/*
	 * Calibrate loops per jiffy value.
	 * IRQs need to be enabled here - D-cache can be invalidated
	 * in timer irq handler, so core B can read correct jiffies.
	 */
	calibrate_delay();

	/* We are done with local CPU inits, unblock the boot CPU. */
	set_cpu_online(cpu, true);
	cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
}

void __init smp_prepare_boot_cpu(void)
{
}

void __init smp_prepare_cpus(unsigned int max_cpus)
{
	platform_prepare_cpus(max_cpus);
	bfin_ipi_init();
	platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
	platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
}

void __init smp_cpus_done(unsigned int max_cpus)
{
	unsigned long bogosum = 0;
	unsigned int cpu;

	for_each_online_cpu(cpu)
		bogosum += loops_per_jiffy;

	printk(KERN_INFO "SMP: Total of %d processors activated "
	       "(%lu.%02lu BogoMIPS).\n",
	       num_online_cpus(),
	       bogosum / (500000/HZ),
	       (bogosum / (5000/HZ)) % 100);
}

void smp_icache_flush_range_others(unsigned long start, unsigned long end)
{
	smp_flush_data.start = start;
	smp_flush_data.end = end;

	preempt_disable();
	if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 1))
		printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
	preempt_enable();
}
EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);

#ifdef __ARCH_SYNC_CORE_ICACHE
unsigned long icache_invld_count[NR_CPUS];
void resync_core_icache(void)
{
	unsigned int cpu = get_cpu();
	blackfin_invalidate_entire_icache();
	icache_invld_count[cpu]++;
	put_cpu();
}
EXPORT_SYMBOL(resync_core_icache);
#endif

#ifdef __ARCH_SYNC_CORE_DCACHE
unsigned long dcache_invld_count[NR_CPUS];
unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));

void resync_core_dcache(void)
{
	unsigned int cpu = get_cpu();
	blackfin_invalidate_entire_dcache();
	dcache_invld_count[cpu]++;
	put_cpu();
}
EXPORT_SYMBOL(resync_core_dcache);
#endif

#ifdef CONFIG_HOTPLUG_CPU
int __cpu_disable(void)
{
	unsigned int cpu = smp_processor_id();

	if (cpu == 0)
		return -EPERM;

	set_cpu_online(cpu, false);
	return 0;
}

int __cpu_die(unsigned int cpu)
{
	return cpu_wait_death(cpu, 5);
}

void cpu_die(void)
{
	(void)cpu_report_death();

	atomic_dec(&init_mm.mm_users);
	atomic_dec(&init_mm.mm_count);

	local_irq_disable();
	platform_cpu_die();
}
#endif
Commit	Line	Data
6b3087c6	1	/*
96f1050d	2	* IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
6b3087c6	3	*
96f1050d RG	4	* Copyright 2007-2009 Analog Devices Inc.
96f1050d RG	5	* Philippe Gerum <rpm@xenomai.org>
6b3087c6	6	*
96f1050d	7	* Licensed under the GPL-2.
6b3087c6 GY	8	*/
	9
	10	#include <linux/module.h>
	11	#include <linux/delay.h>
	12	#include <linux/init.h>
	13	#include <linux/spinlock.h>
	14	#include <linux/sched.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/cache.h>
d0014be4	17	#include <linux/clockchips.h>
6b3087c6 GY	18	#include <linux/profile.h>
	19	#include <linux/errno.h>
	20	#include <linux/mm.h>
	21	#include <linux/cpu.h>
	22	#include <linux/smp.h>
9c199b59	23	#include <linux/cpumask.h>
6b3087c6 GY	24	#include <linux/seq_file.h>
6b3087c6 GY	25	#include <linux/irq.h>
5a0e3ad6	26	#include <linux/slab.h>
60063497	27	#include <linux/atomic.h>
6b3087c6	28	#include <asm/cacheflush.h>
6327a574	29	#include <asm/irq_handler.h>
6b3087c6 GY	30	#include <asm/mmu_context.h>
	31	#include <asm/pgtable.h>
	32	#include <asm/pgalloc.h>
	33	#include <asm/processor.h>
	34	#include <asm/ptrace.h>
	35	#include <asm/cpu.h>
1fa9be72	36	#include <asm/time.h>
6b3087c6 GY	37	#include <linux/err.h>
6b3087c6 GY	38
555487bb GY	39	/*
	40	* Anomaly notes:
	41	* 05000120 - we always define corelock as 32-bit integer in L2
	42	*/
6b3087c6 GY	43	struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
6b3087c6 GY	44
c6345ab1 SZ	45	#ifdef CONFIG_ICACHE_FLUSH_L1
	46	unsigned long blackfin_iflush_l1_entry[NR_CPUS];
	47	#endif
	48
13dff62d	49	struct blackfin_initial_pda initial_pda_coreb;
6b3087c6	50
50888469	51	enum ipi_message_type {
150382a5	52	BFIN_IPI_NONE,
50888469 SM	53	BFIN_IPI_TIMER,
	54	BFIN_IPI_RESCHEDULE,
	55	BFIN_IPI_CALL_FUNC,
50888469 SM	56	BFIN_IPI_CPU_STOP,
50888469 SM	57	};
6b3087c6 GY	58
	59	struct blackfin_flush_data {
	60	unsigned long start;
	61	unsigned long end;
	62	};
	63
	64	void *secondary_stack;
	65
6b3087c6 GY	66	static struct blackfin_flush_data smp_flush_data;
	67
	68	static DEFINE_SPINLOCK(stop_lock);
	69
73a40064 YL	70	/* A magic number - stress test shows this is safe for common cases */
	71	#define BFIN_IPI_MSGQ_LEN 5
	72
	73	/* Simple FIFO buffer, overflow leads to panic */
50888469	74	struct ipi_data {
150382a5 SM	75	atomic_t count;
150382a5 SM	76	atomic_t bits;
6b3087c6 GY	77	};
6b3087c6 GY	78
50888469	79	static DEFINE_PER_CPU(struct ipi_data, bfin_ipi);
6b3087c6 GY	80
	81	static void ipi_cpu_stop(unsigned int cpu)
	82	{
	83	spin_lock(&stop_lock);
	84	printk(KERN_CRIT "CPU%u: stopping\n", cpu);
	85	dump_stack();
	86	spin_unlock(&stop_lock);
	87
fecedc80	88	set_cpu_online(cpu, false);
6b3087c6 GY	89
	90	local_irq_disable();
	91
	92	while (1)
	93	SSYNC();
	94	}
	95
	96	static void ipi_flush_icache(void *info)
	97	{
	98	struct blackfin_flush_data *fdata = info;
	99
	100	/* Invalidate the memory holding the bounds of the flushed region. */
8d50de9e SZ	101	blackfin_dcache_invalidate_range((unsigned long)fdata,
	102	(unsigned long)fdata + sizeof(*fdata));
	103
	104	/* Make sure all write buffers in the data side of the core
	105	* are flushed before trying to invalidate the icache. This
	106	* needs to be after the data flush and before the icache
	107	* flush so that the SSYNC does the right thing in preventing
	108	* the instruction prefetcher from hitting things in cached
	109	* memory at the wrong time -- it runs much further ahead than
	110	* the pipeline.
	111	*/
	112	SSYNC();
	113
	114	/* ipi_flaush_icache is invoked by generic flush_icache_range,
	115	* so call blackfin arch icache flush directly here.
	116	*/
	117	blackfin_icache_flush_range(fdata->start, fdata->end);
6b3087c6 GY	118	}
6b3087c6 GY	119
73a40064 YL	120	/* Use IRQ_SUPPLE_0 to request reschedule.
	121	* When returning from interrupt to user space,
	122	* there is chance to reschedule */
	123	static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
	124	{
	125	unsigned int cpu = smp_processor_id();
	126
	127	platform_clear_ipi(cpu, IRQ_SUPPLE_0);
	128	return IRQ_HANDLED;
	129	}
	130
d0014be4 BL	131	DECLARE_PER_CPU(struct clock_event_device, coretmr_events);
	132	void ipi_timer(void)
	133	{
	134	int cpu = smp_processor_id();
	135	struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
	136	evt->event_handler(evt);
	137	}
	138
73a40064	139	static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
6b3087c6	140	{
50888469	141	struct ipi_data *bfin_ipi_data;
6b3087c6	142	unsigned int cpu = smp_processor_id();
50888469 SM	143	unsigned long pending;
50888469 SM	144	unsigned long msg;
6b3087c6	145
73a40064	146	platform_clear_ipi(cpu, IRQ_SUPPLE_1);
6b3087c6	147
177a48fd	148	smp_rmb();
7e788ab1	149	bfin_ipi_data = this_cpu_ptr(&bfin_ipi);
16fc5bc4	150	while ((pending = atomic_xchg(&bfin_ipi_data->bits, 0)) != 0) {
50888469 SM	151	msg = 0;
	152	do {
	153	msg = find_next_bit(&pending, BITS_PER_LONG, msg + 1);
	154	switch (msg) {
	155	case BFIN_IPI_TIMER:
	156	ipi_timer();
	157	break;
	158	case BFIN_IPI_RESCHEDULE:
	159	scheduler_ipi();
	160	break;
	161	case BFIN_IPI_CALL_FUNC:
	162	generic_smp_call_function_interrupt();
	163	break;
50888469 SM	164	case BFIN_IPI_CPU_STOP:
	165	ipi_cpu_stop(cpu);
	166	break;
177a48fd SM	167	default:
177a48fd SM	168	goto out;
50888469	169	}
150382a5	170	atomic_dec(&bfin_ipi_data->count);
50888469	171	} while (msg < BITS_PER_LONG);
177a48fd	172
6b3087c6	173	}
177a48fd	174	out:
6b3087c6 GY	175	return IRQ_HANDLED;
	176	}
	177
50888469	178	static void bfin_ipi_init(void)
6b3087c6 GY	179	{
6b3087c6 GY	180	unsigned int cpu;
50888469	181	struct ipi_data *bfin_ipi_data;
6b3087c6	182	for_each_possible_cpu(cpu) {
50888469	183	bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
16fc5bc4 SM	184	atomic_set(&bfin_ipi_data->bits, 0);
16fc5bc4 SM	185	atomic_set(&bfin_ipi_data->count, 0);
6b3087c6 GY	186	}
	187	}
	188
50888469	189	void send_ipi(const struct cpumask *cpumask, enum ipi_message_type msg)
6b3087c6 GY	190	{
6b3087c6 GY	191	unsigned int cpu;
50888469 SM	192	struct ipi_data *bfin_ipi_data;
	193	unsigned long flags;
	194
	195	local_irq_save(flags);
50888469 SM	196	for_each_cpu(cpu, cpumask) {
50888469 SM	197	bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
805de8f4	198	atomic_or((1 << msg), &bfin_ipi_data->bits);
150382a5	199	atomic_inc(&bfin_ipi_data->count);
6b3087c6	200	}
50888469	201	local_irq_restore(flags);
177a48fd SM	202	smp_wmb();
	203	for_each_cpu(cpu, cpumask)
	204	platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
73a40064 YL	205	}
73a40064 YL	206
50888469	207	void arch_send_call_function_single_ipi(int cpu)
73a40064	208	{
5e98c099	209	send_ipi(cpumask_of(cpu), BFIN_IPI_CALL_FUNC);
6b3087c6	210	}
6b3087c6	211
50888469	212	void arch_send_call_function_ipi_mask(const struct cpumask *mask)
6b3087c6	213	{
50888469	214	send_ipi(mask, BFIN_IPI_CALL_FUNC);
6b3087c6	215	}
6b3087c6 GY	216
	217	void smp_send_reschedule(int cpu)
	218	{
50888469	219	send_ipi(cpumask_of(cpu), BFIN_IPI_RESCHEDULE);
6b3087c6 GY	220
	221	return;
	222	}
	223
d0014be4 BL	224	void smp_send_msg(const struct cpumask *mask, unsigned long type)
d0014be4 BL	225	{
50888469	226	send_ipi(mask, type);
d0014be4 BL	227	}
	228
	229	void smp_timer_broadcast(const struct cpumask *mask)
	230	{
	231	smp_send_msg(mask, BFIN_IPI_TIMER);
	232	}
	233
6b3087c6 GY	234	void smp_send_stop(void)
6b3087c6 GY	235	{
6b3087c6	236	cpumask_t callmap;
6b3087c6	237
567ebfc9	238	preempt_disable();
fecedc80 KM	239	cpumask_copy(&callmap, cpu_online_mask);
	240	cpumask_clear_cpu(smp_processor_id(), &callmap);
	241	if (!cpumask_empty(&callmap))
50888469	242	send_ipi(&callmap, BFIN_IPI_CPU_STOP);
6b3087c6	243
567ebfc9	244	preempt_enable();
6b3087c6	245
6b3087c6 GY	246	return;
	247	}
	248
13dff62d	249	int __cpu_up(unsigned int cpu, struct task_struct *idle)
6b3087c6	250	{
6b3087c6	251	int ret;
0b39db28	252
6b3087c6	253	secondary_stack = task_stack_page(idle) + THREAD_SIZE;
6b3087c6 GY	254
	255	ret = platform_boot_secondary(cpu, idle);
	256
6b3087c6 GY	257	secondary_stack = NULL;
	258
	259	return ret;
	260	}
	261
13dff62d	262	static void setup_secondary(unsigned int cpu)
6b3087c6	263	{
6b3087c6 GY	264	unsigned long ilat;
	265
	266	bfin_write_IMASK(0);
	267	CSYNC();
	268	ilat = bfin_read_ILAT();
	269	CSYNC();
	270	bfin_write_ILAT(ilat);
	271	CSYNC();
	272
6b3087c6 GY	273	/* Enable interrupt levels IVG7-15. IARs have been already
6b3087c6 GY	274	* programmed by the boot CPU. */
40059784	275	bfin_irq_flags \|= IMASK_IVG15 \|
6b3087c6 GY	276	IMASK_IVG14 \| IMASK_IVG13 \| IMASK_IVG12 \| IMASK_IVG11 \|
6b3087c6 GY	277	IMASK_IVG10 \| IMASK_IVG9 \| IMASK_IVG8 \| IMASK_IVG7 \| IMASK_IVGHW;
6b3087c6 GY	278	}
6b3087c6 GY	279
13dff62d	280	void secondary_start_kernel(void)
6b3087c6 GY	281	{
	282	unsigned int cpu = smp_processor_id();
	283	struct mm_struct *mm = &init_mm;
	284
	285	if (_bfin_swrst & SWRST_DBL_FAULT_B) {
	286	printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
	287	#ifdef CONFIG_DEBUG_DOUBLEFAULT
fb1d9be5 MF	288	printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n",
	289	initial_pda_coreb.seqstat_doublefault & SEQSTAT_EXCAUSE,
	290	initial_pda_coreb.retx_doublefault);
	291	printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n",
	292	initial_pda_coreb.dcplb_doublefault_addr);
	293	printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n",
	294	initial_pda_coreb.icplb_doublefault_addr);
6b3087c6 GY	295	#endif
6b3087c6 GY	296	printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
fb1d9be5	297	initial_pda_coreb.retx);
6b3087c6 GY	298	}
	299
	300	/*
	301	* We want the D-cache to be enabled early, in case the atomic
	302	* support code emulates cache coherence (see
	303	* __ARCH_SYNC_CORE_DCACHE).
	304	*/
	305	init_exception_vectors();
	306
6b3087c6 GY	307	local_irq_disable();
	308
	309	/* Attach the new idle task to the global mm. */
	310	atomic_inc(&mm->mm_users);
	311	atomic_inc(&mm->mm_count);
	312	current->active_mm = mm;
6b3087c6 GY	313
	314	preempt_disable();
	315
	316	setup_secondary(cpu);
	317
578d36f5	318	platform_secondary_init(cpu);
0d152c27 YL	319	/* setup local core timer */
	320	bfin_local_timer_setup();
	321
6b3087c6 GY	322	local_irq_enable();
6b3087c6 GY	323
ab61d2ac	324	bfin_setup_caches(cpu);
ab61d2ac	325
d0014be4	326	notify_cpu_starting(cpu);
578d36f5 YL	327	/*
	328	* Calibrate loops per jiffy value.
	329	* IRQs need to be enabled here - D-cache can be invalidated
	330	* in timer irq handler, so core B can read correct jiffies.
	331	*/
	332	calibrate_delay();
6b3087c6	333
150382a5 SM	334	/* We are done with local CPU inits, unblock the boot CPU. */
150382a5 SM	335	set_cpu_online(cpu, true);
fc6d73d6	336	cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
6b3087c6 GY	337	}
	338
	339	void __init smp_prepare_boot_cpu(void)
	340	{
	341	}
	342
	343	void __init smp_prepare_cpus(unsigned int max_cpus)
	344	{
	345	platform_prepare_cpus(max_cpus);
50888469	346	bfin_ipi_init();
73a40064 YL	347	platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
73a40064 YL	348	platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
6b3087c6 GY	349	}
	350
	351	void __init smp_cpus_done(unsigned int max_cpus)
	352	{
	353	unsigned long bogosum = 0;
	354	unsigned int cpu;
	355
	356	for_each_online_cpu(cpu)
c70c754f	357	bogosum += loops_per_jiffy;
6b3087c6 GY	358
	359	printk(KERN_INFO "SMP: Total of %d processors activated "
	360	"(%lu.%02lu BogoMIPS).\n",
	361	num_online_cpus(),
	362	bogosum / (500000/HZ),
	363	(bogosum / (5000/HZ)) % 100);
	364	}
	365
	366	void smp_icache_flush_range_others(unsigned long start, unsigned long end)
	367	{
	368	smp_flush_data.start = start;
	369	smp_flush_data.end = end;
	370
a2eff9dd SM	371	preempt_disable();
a2eff9dd SM	372	if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 1))
6b3087c6	373	printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
a2eff9dd	374	preempt_enable();
6b3087c6 GY	375	}
	376	EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
	377
47e9dedb	378	#ifdef __ARCH_SYNC_CORE_ICACHE
718340f6	379	unsigned long icache_invld_count[NR_CPUS];
47e9dedb SZ	380	void resync_core_icache(void)
	381	{
	382	unsigned int cpu = get_cpu();
	383	blackfin_invalidate_entire_icache();
718340f6	384	icache_invld_count[cpu]++;
47e9dedb SZ	385	put_cpu();
	386	}
	387	EXPORT_SYMBOL(resync_core_icache);
	388	#endif
	389
6b3087c6	390	#ifdef __ARCH_SYNC_CORE_DCACHE
718340f6	391	unsigned long dcache_invld_count[NR_CPUS];
6b3087c6 GY	392	unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
	393
	394	void resync_core_dcache(void)
	395	{
	396	unsigned int cpu = get_cpu();
	397	blackfin_invalidate_entire_dcache();
718340f6	398	dcache_invld_count[cpu]++;
6b3087c6 GY	399	put_cpu();
	400	}
	401	EXPORT_SYMBOL(resync_core_dcache);
	402	#endif
0b39db28 GY	403
0b39db28 GY	404	#ifdef CONFIG_HOTPLUG_CPU
13dff62d	405	int __cpu_disable(void)
0b39db28 GY	406	{
	407	unsigned int cpu = smp_processor_id();
	408
	409	if (cpu == 0)
	410	return -EPERM;
	411
	412	set_cpu_online(cpu, false);
	413	return 0;
	414	}
	415
13dff62d	416	int __cpu_die(unsigned int cpu)
0b39db28	417	{
a17b4b74	418	return cpu_wait_death(cpu, 5);
0b39db28 GY	419	}
	420
	421	void cpu_die(void)
	422	{
a17b4b74	423	(void)cpu_report_death();
0b39db28 GY	424
	425	atomic_dec(&init_mm.mm_users);
	426	atomic_dec(&init_mm.mm_count);
	427
	428	local_irq_disable();
	429	platform_cpu_die();
	430	}
	431	#endif