projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 920e526f | 1 | /* |
| 96f1050d | 2 | * Copyright 2008 Analog Devices Inc. |
| 920e526f | 3 | * |
| 96f1050d | 4 | * Licensed under the ADI BSD license or the GPL-2 (or later) |
| 920e526f MF |
5 | */ |
| 6 | ||
| 4ed250a5 MF |
7 | #ifndef _DEF_BF547_H |
| 8 | #define _DEF_BF547_H | |
| 920e526f MF |
9 | |
| 10 | /* Include all Core registers and bit definitions */ | |
| 639f6571 | 11 | #include <asm/def_LPBlackfin.h> |
| 920e526f | 12 | |
| 4ed250a5 | 13 | /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */ |
| 920e526f MF |
14 | |
| 15 | /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ | |
| 16 | #include "defBF54x_base.h" | |
| 17 | ||
| 4ed250a5 | 18 | /* The following are the #defines needed by ADSP-BF547 that are not in the common header */ |
| 920e526f MF |
19 | |
| 20 | /* Timer Registers */ | |
| 21 | ||
| 22 | #define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */ | |
| 23 | #define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */ | |
| 24 | #define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */ | |
| 25 | #define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */ | |
| 26 | #define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */ | |
| 27 | #define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */ | |
| 28 | #define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */ | |
| 29 | #define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */ | |
| 30 | #define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */ | |
| 31 | #define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */ | |
| 32 | #define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */ | |
| 33 | #define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */ | |
| 34 | ||
| 35 | /* Timer Group of 3 Registers */ | |
| 36 | ||
| 37 | #define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */ | |
| 38 | #define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */ | |
| 39 | #define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */ | |
| 40 | ||
| 41 | /* SPORT0 Registers */ | |
| 42 | ||
| 43 | #define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */ | |
| 44 | #define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */ | |
| 45 | #define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */ | |
| 46 | #define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */ | |
| 47 | #define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */ | |
| 48 | #define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */ | |
| 49 | #define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */ | |
| 50 | #define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */ | |
| 51 | #define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */ | |
| 52 | #define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */ | |
| 53 | #define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */ | |
| 54 | #define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */ | |
| 55 | #define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */ | |
| 56 | #define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */ | |
| 57 | #define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */ | |
| 58 | #define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */ | |
| 59 | #define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */ | |
| 60 | #define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */ | |
| 61 | #define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */ | |
| 62 | #define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */ | |
| 63 | #define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */ | |
| 64 | #define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */ | |
| 65 | ||
| 66 | /* EPPI0 Registers */ | |
| 67 | ||
| 68 | #define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */ | |
| 69 | #define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */ | |
| 70 | #define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */ | |
| 71 | #define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */ | |
| 72 | #define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */ | |
| 73 | #define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */ | |
| 74 | #define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */ | |
| 75 | #define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */ | |
| 76 | #define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */ | |
| 77 | #define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ | |
| 78 | #define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ | |
| 79 | #define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ | |
| 80 | #define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ | |
| 81 | #define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */ | |
| 82 | ||
| 83 | /* UART2 Registers */ | |
| 84 | ||
| 85 | #define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */ | |
| 86 | #define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */ | |
| 87 | #define UART2_GCTL 0xffc02108 /* Global Control Register */ | |
| 88 | #define UART2_LCR 0xffc0210c /* Line Control Register */ | |
| 89 | #define UART2_MCR 0xffc02110 /* Modem Control Register */ | |
| 90 | #define UART2_LSR 0xffc02114 /* Line Status Register */ | |
| 91 | #define UART2_MSR 0xffc02118 /* Modem Status Register */ | |
| 92 | #define UART2_SCR 0xffc0211c /* Scratch Register */ | |
| 93 | #define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */ | |
| 94 | #define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */ | |
| 95 | #define UART2_RBR 0xffc0212c /* Receive Buffer Register */ | |
| 96 | ||
| 97 | /* Two Wire Interface Registers (TWI1) */ | |
| 98 | ||
| 99 | #define TWI1_REGBASE 0xffc02200 | |
| 100 | #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ | |
| 101 | #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ | |
| 102 | #define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ | |
| 103 | #define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ | |
| 104 | #define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ | |
| 105 | #define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */ | |
| 106 | #define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ | |
| 107 | #define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ | |
| 108 | #define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ | |
| 109 | #define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ | |
| 110 | #define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */ | |
| 111 | #define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ | |
| 112 | #define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ | |
| 113 | #define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ | |
| 114 | #define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */ | |
| 115 | #define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */ | |
| 116 | ||
| 117 | /* SPI2 Registers */ | |
| 118 | ||
| 119 | #define SPI2_REGBASE 0xffc02400 | |
| 120 | #define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ | |
| 121 | #define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ | |
| 122 | #define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ | |
| 123 | #define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */ | |
| 124 | #define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */ | |
| 125 | #define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */ | |
| 126 | #define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */ | |
| 127 | ||
| 128 | /* ATAPI Registers */ | |
| 129 | ||
| 130 | #define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */ | |
| 131 | #define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */ | |
| 132 | #define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */ | |
| 133 | #define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */ | |
| 134 | #define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */ | |
| 135 | #define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */ | |
| 136 | #define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */ | |
| 137 | #define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */ | |
| 138 | #define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */ | |
| 139 | #define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */ | |
| 140 | #define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */ | |
| 141 | #define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */ | |
| 142 | #define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */ | |
| 143 | #define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */ | |
| 144 | #define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */ | |
| 145 | #define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */ | |
| 146 | #define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */ | |
| 147 | #define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */ | |
| 148 | #define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */ | |
| 149 | #define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */ | |
| 150 | #define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */ | |
| 151 | #define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */ | |
| 152 | #define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */ | |
| 153 | #define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */ | |
| 154 | #define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */ | |
| 155 | ||
| 156 | /* SDH Registers */ | |
| 157 | ||
| 158 | #define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */ | |
| 159 | #define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */ | |
| 160 | #define SDH_ARGUMENT 0xffc03908 /* SDH Argument */ | |
| 161 | #define SDH_COMMAND 0xffc0390c /* SDH Command */ | |
| 162 | #define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */ | |
| 163 | #define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */ | |
| 164 | #define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */ | |
| 165 | #define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */ | |
| 166 | #define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */ | |
| 167 | #define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */ | |
| 168 | #define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */ | |
| 169 | #define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */ | |
| 170 | #define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */ | |
| 171 | #define SDH_STATUS 0xffc03934 /* SDH Status */ | |
| 172 | #define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */ | |
| 173 | #define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */ | |
| 174 | #define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */ | |
| 175 | #define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */ | |
| 176 | #define SDH_FIFO 0xffc03980 /* SDH Data FIFO */ | |
| 177 | #define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */ | |
| 178 | #define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */ | |
| 179 | #define SDH_CFG 0xffc039c8 /* SDH Configuration */ | |
| 180 | #define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */ | |
| 181 | #define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */ | |
| 182 | #define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */ | |
| 183 | #define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */ | |
| 184 | #define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */ | |
| 185 | #define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */ | |
| 186 | #define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */ | |
| 187 | #define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */ | |
| 188 | #define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */ | |
| 189 | ||
| 190 | /* HOST Port Registers */ | |
| 191 | ||
| 192 | #define HOST_CONTROL 0xffc03a00 /* HOST Control Register */ | |
| 193 | #define HOST_STATUS 0xffc03a04 /* HOST Status Register */ | |
| 194 | #define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */ | |
| 195 | ||
| 196 | /* USB Control Registers */ | |
| 197 | ||
| 198 | #define USB_FADDR 0xffc03c00 /* Function address register */ | |
| 199 | #define USB_POWER 0xffc03c04 /* Power management register */ | |
| 200 | #define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ | |
| 201 | #define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */ | |
| 202 | #define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */ | |
| 203 | #define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */ | |
| 204 | #define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */ | |
| 205 | #define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */ | |
| 206 | #define USB_FRAME 0xffc03c20 /* USB frame number */ | |
| 207 | #define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */ | |
| 208 | #define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */ | |
| 209 | #define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ | |
| 210 | #define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */ | |
| 211 | ||
| 212 | /* USB Packet Control Registers */ | |
| 213 | ||
| 214 | #define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */ | |
| 215 | #define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ | |
| 216 | #define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ | |
| 217 | #define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */ | |
| 218 | #define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */ | |
| 219 | #define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ | |
| 220 | #define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ | |
| 221 | #define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ | |
| 222 | #define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ | |
| 223 | #define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ | |
| 224 | #define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ | |
| 225 | #define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ | |
| 226 | #define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */ | |
| 227 | ||
| 228 | /* USB Endpoint FIFO Registers */ | |
| 229 | ||
| 230 | #define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */ | |
| 231 | #define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */ | |
| 232 | #define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */ | |
| 233 | #define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */ | |
| 234 | #define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */ | |
| 235 | #define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */ | |
| 236 | #define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */ | |
| 237 | #define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */ | |
| 238 | ||
| 239 | /* USB OTG Control Registers */ | |
| 240 | ||
| 241 | #define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */ | |
| 242 | #define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */ | |
| 243 | #define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */ | |
| 244 | ||
| 245 | /* USB Phy Control Registers */ | |
| 246 | ||
| 247 | #define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */ | |
| 248 | #define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */ | |
| 249 | #define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */ | |
| 250 | #define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */ | |
| 251 | #define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */ | |
| 252 | ||
| 253 | /* (APHY_CNTRL is for ADI usage only) */ | |
| 254 | ||
| 255 | #define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */ | |
| 256 | ||
| 257 | /* (APHY_CALIB is for ADI usage only) */ | |
| 258 | ||
| 259 | #define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */ | |
| 260 | #define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ | |
| 261 | ||
| 262 | /* (PHY_TEST is for ADI usage only) */ | |
| 263 | ||
| 264 | #define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */ | |
| 265 | #define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */ | |
| 266 | #define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ | |
| 267 | ||
| 268 | /* USB Endpoint 0 Control Registers */ | |
| 269 | ||
| 270 | #define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */ | |
| 271 | #define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */ | |
| 272 | #define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */ | |
| 273 | #define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */ | |
| 274 | #define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */ | |
| 275 | #define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ | |
| 276 | #define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */ | |
| 277 | #define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ | |
| 278 | #define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ | |
| 279 | ||
| 280 | /* USB Endpoint 1 Control Registers */ | |
| 281 | ||
| 282 | #define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ | |
| 283 | #define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */ | |
| 284 | #define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */ | |
| 285 | #define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */ | |
| 286 | #define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */ | |
| 287 | #define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */ | |
| 288 | #define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ | |
| 289 | #define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */ | |
| 290 | #define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ | |
| 291 | #define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ | |
| 292 | ||
| 293 | /* USB Endpoint 2 Control Registers */ | |
| 294 | ||
| 295 | #define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ | |
| 296 | #define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */ | |
| 297 | #define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */ | |
| 298 | #define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */ | |
| 299 | #define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */ | |
| 300 | #define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */ | |
| 301 | #define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ | |
| 302 | #define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */ | |
| 303 | #define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ | |
| 304 | #define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ | |
| 305 | ||
| 306 | /* USB Endpoint 3 Control Registers */ | |
| 307 | ||
| 308 | #define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ | |
| 309 | #define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */ | |
| 310 | #define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */ | |
| 311 | #define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */ | |
| 312 | #define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */ | |
| 313 | #define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */ | |
| 314 | #define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ | |
| 315 | #define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */ | |
| 316 | #define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ | |
| 317 | #define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ | |
| 318 | ||
| 319 | /* USB Endpoint 4 Control Registers */ | |
| 320 | ||
| 321 | #define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ | |
| 322 | #define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */ | |
| 323 | #define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */ | |
| 324 | #define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */ | |
| 325 | #define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */ | |
| 326 | #define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */ | |
| 327 | #define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ | |
| 328 | #define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */ | |
| 329 | #define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ | |
| 330 | #define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ | |
| 331 | ||
| 332 | /* USB Endpoint 5 Control Registers */ | |
| 333 | ||
| 334 | #define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ | |
| 335 | #define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */ | |
| 336 | #define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */ | |
| 337 | #define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */ | |
| 338 | #define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */ | |
| 339 | #define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */ | |
| 340 | #define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ | |
| 341 | #define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */ | |
| 342 | #define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ | |
| 343 | #define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ | |
| 344 | ||
| 345 | /* USB Endpoint 6 Control Registers */ | |
| 346 | ||
| 347 | #define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */ | |
| 348 | #define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */ | |
| 349 | #define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */ | |
| 350 | #define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */ | |
| 351 | #define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */ | |
| 352 | #define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */ | |
| 353 | #define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ | |
| 354 | #define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */ | |
| 355 | #define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ | |
| 356 | #define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ | |
| 357 | ||
| 358 | /* USB Endpoint 7 Control Registers */ | |
| 359 | ||
| 360 | #define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ | |
| 361 | #define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */ | |
| 362 | #define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */ | |
| 363 | #define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */ | |
| 364 | #define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */ | |
| 365 | #define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */ | |
| 366 | #define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ | |
| 367 | #define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */ | |
| 368 | #define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ | |
| 369 | #define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ | |
| 370 | #define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ | |
| 371 | #define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */ | |
| 372 | ||
| 373 | /* USB Channel 0 Config Registers */ | |
| 374 | ||
| 375 | #define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */ | |
| 376 | #define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ | |
| 377 | #define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ | |
| 378 | #define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ | |
| 379 | #define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ | |
| 380 | ||
| 381 | /* USB Channel 1 Config Registers */ | |
| 382 | ||
| 383 | #define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */ | |
| 384 | #define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ | |
| 385 | #define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ | |
| 386 | #define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ | |
| 387 | #define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ | |
| 388 | ||
| 389 | /* USB Channel 2 Config Registers */ | |
| 390 | ||
| 391 | #define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */ | |
| 392 | #define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ | |
| 393 | #define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ | |
| 394 | #define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ | |
| 395 | #define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ | |
| 396 | ||
| 397 | /* USB Channel 3 Config Registers */ | |
| 398 | ||
| 399 | #define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */ | |
| 400 | #define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ | |
| 401 | #define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ | |
| 402 | #define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ | |
| 403 | #define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ | |
| 404 | ||
| 405 | /* USB Channel 4 Config Registers */ | |
| 406 | ||
| 407 | #define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */ | |
| 408 | #define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ | |
| 409 | #define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ | |
| 410 | #define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ | |
| 411 | #define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ | |
| 412 | ||
| 413 | /* USB Channel 5 Config Registers */ | |
| 414 | ||
| 415 | #define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */ | |
| 416 | #define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ | |
| 417 | #define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ | |
| 418 | #define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ | |
| 419 | #define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ | |
| 420 | ||
| 421 | /* USB Channel 6 Config Registers */ | |
| 422 | ||
| 423 | #define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */ | |
| 424 | #define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ | |
| 425 | #define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ | |
| 426 | #define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ | |
| 427 | #define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ | |
| 428 | ||
| 429 | /* USB Channel 7 Config Registers */ | |
| 430 | ||
| 431 | #define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */ | |
| 432 | #define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ | |
| 433 | #define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ | |
| 434 | #define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ | |
| 435 | #define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ | |
| 436 | ||
| 437 | /* Keypad Registers */ | |
| 438 | ||
| 439 | #define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */ | |
| 440 | #define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */ | |
| 441 | #define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */ | |
| 442 | #define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */ | |
| 443 | #define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */ | |
| 444 | #define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */ | |
| 445 | ||
| 446 | /* Pixel Compositor (PIXC) Registers */ | |
| 447 | ||
| 448 | #define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ | |
| 449 | #define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */ | |
| 450 | #define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */ | |
| 451 | #define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */ | |
| 452 | #define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */ | |
| 453 | #define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */ | |
| 454 | #define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */ | |
| 455 | #define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */ | |
| 456 | #define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */ | |
| 457 | #define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */ | |
| 458 | #define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */ | |
| 459 | #define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */ | |
| 460 | #define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */ | |
| 461 | #define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */ | |
| 462 | #define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ | |
| 463 | #define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */ | |
| 464 | #define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */ | |
| 465 | #define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */ | |
| 466 | #define PIXC_TC 0xffc04450 /* Holds the transparent color value */ | |
| 467 | ||
| 468 | /* Handshake MDMA 0 Registers */ | |
| 469 | ||
| 470 | #define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */ | |
| 471 | #define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */ | |
| 472 | #define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */ | |
| af901ca1 | 473 | #define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */ |
| 920e526f MF |
474 | #define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ |
| 475 | #define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */ | |
| 476 | #define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */ | |
| 477 | ||
| 478 | /* Handshake MDMA 1 Registers */ | |
| 479 | ||
| 480 | #define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */ | |
| 481 | #define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */ | |
| 482 | #define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */ | |
| af901ca1 | 483 | #define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */ |
| 920e526f MF |
484 | #define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ |
| 485 | #define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */ | |
| 486 | #define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */ | |
| 487 | ||
| 488 | ||
| 489 | /* ********************************************************** */ | |
| 490 | /* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ | |
| 491 | /* and MULTI BIT READ MACROS */ | |
| 492 | /* ********************************************************** */ | |
| 493 | ||
| 494 | /* Bit masks for PIXC_CTL */ | |
| 495 | ||
| 496 | #define PIXC_EN 0x1 /* Pixel Compositor Enable */ | |
| 497 | #define OVR_A_EN 0x2 /* Overlay A Enable */ | |
| 498 | #define OVR_B_EN 0x4 /* Overlay B Enable */ | |
| 499 | #define IMG_FORM 0x8 /* Image Data Format */ | |
| 500 | #define OVR_FORM 0x10 /* Overlay Data Format */ | |
| 501 | #define OUT_FORM 0x20 /* Output Data Format */ | |
| 502 | #define UDS_MOD 0x40 /* Resampling Mode */ | |
| 503 | #define TC_EN 0x80 /* Transparent Color Enable */ | |
| 504 | #define IMG_STAT 0x300 /* Image FIFO Status */ | |
| 505 | #define OVR_STAT 0xc00 /* Overlay FIFO Status */ | |
| 506 | #define WM_LVL 0x3000 /* FIFO Watermark Level */ | |
| 507 | ||
| 508 | /* Bit masks for PIXC_AHSTART */ | |
| 509 | ||
| 510 | #define A_HSTART 0xfff /* Horizontal Start Coordinates */ | |
| 511 | ||
| 512 | /* Bit masks for PIXC_AHEND */ | |
| 513 | ||
| 514 | #define A_HEND 0xfff /* Horizontal End Coordinates */ | |
| 515 | ||
| 516 | /* Bit masks for PIXC_AVSTART */ | |
| 517 | ||
| 518 | #define A_VSTART 0x3ff /* Vertical Start Coordinates */ | |
| 519 | ||
| 520 | /* Bit masks for PIXC_AVEND */ | |
| 521 | ||
| 522 | #define A_VEND 0x3ff /* Vertical End Coordinates */ | |
| 523 | ||
| 524 | /* Bit masks for PIXC_ATRANSP */ | |
| 525 | ||
| 526 | #define A_TRANSP 0xf /* Transparency Value */ | |
| 527 | ||
| 528 | /* Bit masks for PIXC_BHSTART */ | |
| 529 | ||
| 530 | #define B_HSTART 0xfff /* Horizontal Start Coordinates */ | |
| 531 | ||
| 532 | /* Bit masks for PIXC_BHEND */ | |
| 533 | ||
| 534 | #define B_HEND 0xfff /* Horizontal End Coordinates */ | |
| 535 | ||
| 536 | /* Bit masks for PIXC_BVSTART */ | |
| 537 | ||
| 538 | #define B_VSTART 0x3ff /* Vertical Start Coordinates */ | |
| 539 | ||
| 540 | /* Bit masks for PIXC_BVEND */ | |
| 541 | ||
| 542 | #define B_VEND 0x3ff /* Vertical End Coordinates */ | |
| 543 | ||
| 544 | /* Bit masks for PIXC_BTRANSP */ | |
| 545 | ||
| 546 | #define B_TRANSP 0xf /* Transparency Value */ | |
| 547 | ||
| 548 | /* Bit masks for PIXC_INTRSTAT */ | |
| 549 | ||
| 550 | #define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ | |
| 551 | #define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ | |
| 552 | #define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ | |
| 553 | #define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ | |
| 554 | ||
| 555 | /* Bit masks for PIXC_RYCON */ | |
| 556 | ||
| 557 | #define A11 0x3ff /* A11 in the Coefficient Matrix */ | |
| 558 | #define A12 0xffc00 /* A12 in the Coefficient Matrix */ | |
| 559 | #define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ | |
| 560 | #define RY_MULT4 0x40000000 /* Multiply Row by 4 */ | |
| 561 | ||
| 562 | /* Bit masks for PIXC_GUCON */ | |
| 563 | ||
| 564 | #define A21 0x3ff /* A21 in the Coefficient Matrix */ | |
| 565 | #define A22 0xffc00 /* A22 in the Coefficient Matrix */ | |
| 566 | #define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ | |
| 567 | #define GU_MULT4 0x40000000 /* Multiply Row by 4 */ | |
| 568 | ||
| 569 | /* Bit masks for PIXC_BVCON */ | |
| 570 | ||
| 571 | #define A31 0x3ff /* A31 in the Coefficient Matrix */ | |
| 572 | #define A32 0xffc00 /* A32 in the Coefficient Matrix */ | |
| 573 | #define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ | |
| 574 | #define BV_MULT4 0x40000000 /* Multiply Row by 4 */ | |
| 575 | ||
| 576 | /* Bit masks for PIXC_CCBIAS */ | |
| 577 | ||
| 578 | #define A14 0x3ff /* A14 in the Bias Vector */ | |
| 579 | #define A24 0xffc00 /* A24 in the Bias Vector */ | |
| 580 | #define A34 0x3ff00000 /* A34 in the Bias Vector */ | |
| 581 | ||
| 582 | /* Bit masks for PIXC_TC */ | |
| 583 | ||
| 584 | #define RY_TRANS 0xff /* Transparent Color - R/Y Component */ | |
| 585 | #define GU_TRANS 0xff00 /* Transparent Color - G/U Component */ | |
| 586 | #define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */ | |
| 587 | ||
| 588 | /* Bit masks for HOST_CONTROL */ | |
| 589 | ||
| 590 | #define HOST_EN 0x1 /* Host Enable */ | |
| 591 | #define HOST_END 0x2 /* Host Endianess */ | |
| 592 | #define DATA_SIZE 0x4 /* Data Size */ | |
| 593 | #define HOST_RST 0x8 /* Host Reset */ | |
| 594 | #define HRDY_OVR 0x20 /* Host Ready Override */ | |
| 595 | #define INT_MODE 0x40 /* Interrupt Mode */ | |
| 596 | #define BT_EN 0x80 /* Bus Timeout Enable */ | |
| 597 | #define EHW 0x100 /* Enable Host Write */ | |
| 598 | #define EHR 0x200 /* Enable Host Read */ | |
| 599 | #define BDR 0x400 /* Burst DMA Requests */ | |
| 600 | ||
| 601 | /* Bit masks for HOST_STATUS */ | |
| 602 | ||
| 603 | #define DMA_READY 0x1 /* DMA Ready */ | |
| 604 | #define FIFOFULL 0x2 /* FIFO Full */ | |
| 605 | #define FIFOEMPTY 0x4 /* FIFO Empty */ | |
| 606 | #define DMA_COMPLETE 0x8 /* DMA Complete */ | |
| 607 | #define HSHK 0x10 /* Host Handshake */ | |
| 608 | #define HSTIMEOUT 0x20 /* Host Timeout */ | |
| 609 | #define HIRQ 0x40 /* Host Interrupt Request */ | |
| 610 | #define ALLOW_CNFG 0x80 /* Allow New Configuration */ | |
| 611 | #define DMA_DIR 0x100 /* DMA Direction */ | |
| 612 | #define BTE 0x200 /* Bus Timeout Enabled */ | |
| 613 | ||
| 614 | /* Bit masks for HOST_TIMEOUT */ | |
| 615 | ||
| 616 | #define COUNT_TIMEOUT 0x7ff /* Host Timeout count */ | |
| 617 | ||
| 618 | /* Bit masks for KPAD_CTL */ | |
| 619 | ||
| 620 | #define KPAD_EN 0x1 /* Keypad Enable */ | |
| 621 | #define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ | |
| 622 | #define KPAD_ROWEN 0x1c00 /* Row Enable Width */ | |
| 623 | #define KPAD_COLEN 0xe000 /* Column Enable Width */ | |
| 624 | ||
| 625 | /* Bit masks for KPAD_PRESCALE */ | |
| 626 | ||
| 627 | #define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */ | |
| 628 | ||
| 629 | /* Bit masks for KPAD_MSEL */ | |
| 630 | ||
| 631 | #define DBON_SCALE 0xff /* Debounce Scale Value */ | |
| 632 | #define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */ | |
| 633 | ||
| 634 | /* Bit masks for KPAD_ROWCOL */ | |
| 635 | ||
| 636 | #define KPAD_ROW 0xff /* Rows Pressed */ | |
| 637 | #define KPAD_COL 0xff00 /* Columns Pressed */ | |
| 638 | ||
| 639 | /* Bit masks for KPAD_STAT */ | |
| 640 | ||
| 641 | #define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ | |
| 642 | #define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ | |
| 643 | #define KPAD_PRESSED 0x8 /* Key press current status */ | |
| 644 | ||
| 645 | /* Bit masks for KPAD_SOFTEVAL */ | |
| 646 | ||
| 647 | #define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ | |
| 648 | ||
| 649 | /* Bit masks for SDH_COMMAND */ | |
| 650 | ||
| 651 | #define CMD_IDX 0x3f /* Command Index */ | |
| 652 | #define CMD_RSP 0x40 /* Response */ | |
| 653 | #define CMD_L_RSP 0x80 /* Long Response */ | |
| 654 | #define CMD_INT_E 0x100 /* Command Interrupt */ | |
| 655 | #define CMD_PEND_E 0x200 /* Command Pending */ | |
| 656 | #define CMD_E 0x400 /* Command Enable */ | |
| 657 | ||
| 658 | /* Bit masks for SDH_PWR_CTL */ | |
| 659 | ||
| 660 | #define PWR_ON 0x3 /* Power On */ | |
| 661 | #if 0 | |
| 662 | #define TBD 0x3c /* TBD */ | |
| 663 | #endif | |
| 664 | #define SD_CMD_OD 0x40 /* Open Drain Output */ | |
| 665 | #define ROD_CTL 0x80 /* Rod Control */ | |
| 666 | ||
| 667 | /* Bit masks for SDH_CLK_CTL */ | |
| 668 | ||
| 669 | #define CLKDIV 0xff /* MC_CLK Divisor */ | |
| 670 | #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ | |
| 671 | #define PWR_SV_E 0x200 /* Power Save Enable */ | |
| 672 | #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ | |
| 673 | #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ | |
| 674 | ||
| 675 | /* Bit masks for SDH_RESP_CMD */ | |
| 676 | ||
| 677 | #define RESP_CMD 0x3f /* Response Command */ | |
| 678 | ||
| 679 | /* Bit masks for SDH_DATA_CTL */ | |
| 680 | ||
| 681 | #define DTX_E 0x1 /* Data Transfer Enable */ | |
| 682 | #define DTX_DIR 0x2 /* Data Transfer Direction */ | |
| 683 | #define DTX_MODE 0x4 /* Data Transfer Mode */ | |
| 684 | #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ | |
| 685 | #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ | |
| 686 | ||
| 687 | /* Bit masks for SDH_STATUS */ | |
| 688 | ||
| 689 | #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ | |
| 690 | #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ | |
| 691 | #define CMD_TIME_OUT 0x4 /* CMD Time Out */ | |
| 692 | #define DAT_TIME_OUT 0x8 /* Data Time Out */ | |
| 693 | #define TX_UNDERRUN 0x10 /* Transmit Underrun */ | |
| 694 | #define RX_OVERRUN 0x20 /* Receive Overrun */ | |
| 695 | #define CMD_RESP_END 0x40 /* CMD Response End */ | |
| 696 | #define CMD_SENT 0x80 /* CMD Sent */ | |
| 697 | #define DAT_END 0x100 /* Data End */ | |
| 698 | #define START_BIT_ERR 0x200 /* Start Bit Error */ | |
| 699 | #define DAT_BLK_END 0x400 /* Data Block End */ | |
| 700 | #define CMD_ACT 0x800 /* CMD Active */ | |
| 701 | #define TX_ACT 0x1000 /* Transmit Active */ | |
| 702 | #define RX_ACT 0x2000 /* Receive Active */ | |
| 703 | #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ | |
| 704 | #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ | |
| 705 | #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ | |
| 706 | #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ | |
| 707 | #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ | |
| 708 | #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ | |
| 709 | #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ | |
| 710 | #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ | |
| 711 | ||
| 712 | /* Bit masks for SDH_STATUS_CLR */ | |
| 713 | ||
| 714 | #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ | |
| 715 | #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ | |
| 716 | #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ | |
| 717 | #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ | |
| 718 | #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ | |
| 719 | #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ | |
| 720 | #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ | |
| 721 | #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ | |
| 722 | #define DAT_END_STAT 0x100 /* Data End Status */ | |
| 723 | #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ | |
| 724 | #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ | |
| 725 | ||
| 726 | /* Bit masks for SDH_MASK0 */ | |
| 727 | ||
| 728 | #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ | |
| 729 | #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ | |
| 730 | #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ | |
| 731 | #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ | |
| 732 | #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ | |
| 733 | #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ | |
| 734 | #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ | |
| 735 | #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ | |
| 736 | #define DAT_END_MASK 0x100 /* Data End Mask */ | |
| 737 | #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ | |
| 738 | #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ | |
| 739 | #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ | |
| 740 | #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ | |
| 741 | #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ | |
| 742 | #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ | |
| 743 | #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ | |
| 744 | #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ | |
| 745 | #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ | |
| 746 | #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ | |
| 747 | #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ | |
| 748 | #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ | |
| 749 | #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ | |
| 750 | ||
| 751 | /* Bit masks for SDH_FIFO_CNT */ | |
| 752 | ||
| 753 | #define FIFO_COUNT 0x7fff /* FIFO Count */ | |
| 754 | ||
| 755 | /* Bit masks for SDH_E_STATUS */ | |
| 756 | ||
| 757 | #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ | |
| 758 | #define SD_CARD_DET 0x10 /* SD Card Detect */ | |
| 759 | ||
| 760 | /* Bit masks for SDH_E_MASK */ | |
| 761 | ||
| 762 | #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ | |
| 763 | #define SCD_MSK 0x40 /* Mask Card Detect */ | |
| 764 | ||
| 765 | /* Bit masks for SDH_CFG */ | |
| 766 | ||
| 767 | #define CLKS_EN 0x1 /* Clocks Enable */ | |
| 768 | #define SD4E 0x4 /* SDIO 4-Bit Enable */ | |
| 769 | #define MWE 0x8 /* Moving Window Enable */ | |
| 770 | #define SD_RST 0x10 /* SDMMC Reset */ | |
| 771 | #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ | |
| 772 | #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ | |
| 773 | #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ | |
| 774 | ||
| 775 | /* Bit masks for SDH_RD_WAIT_EN */ | |
| 776 | ||
| 777 | #define RWR 0x1 /* Read Wait Request */ | |
| 778 | ||
| 779 | /* Bit masks for ATAPI_CONTROL */ | |
| 780 | ||
| 781 | #define PIO_START 0x1 /* Start PIO/Reg Op */ | |
| 782 | #define MULTI_START 0x2 /* Start Multi-DMA Op */ | |
| 783 | #define ULTRA_START 0x4 /* Start Ultra-DMA Op */ | |
| 784 | #define XFER_DIR 0x8 /* Transfer Direction */ | |
| 785 | #define IORDY_EN 0x10 /* IORDY Enable */ | |
| 786 | #define FIFO_FLUSH 0x20 /* Flush FIFOs */ | |
| 787 | #define SOFT_RST 0x40 /* Soft Reset */ | |
| 788 | #define DEV_RST 0x80 /* Device Reset */ | |
| 789 | #define TFRCNT_RST 0x100 /* Trans Count Reset */ | |
| 790 | #define END_ON_TERM 0x200 /* End/Terminate Select */ | |
| 791 | #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ | |
| 792 | #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ | |
| 793 | ||
| 794 | /* Bit masks for ATAPI_STATUS */ | |
| 795 | ||
| 796 | #define PIO_XFER_ON 0x1 /* PIO transfer in progress */ | |
| 797 | #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ | |
| 798 | #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ | |
| 799 | #define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ | |
| 800 | ||
| 801 | /* Bit masks for ATAPI_DEV_ADDR */ | |
| 802 | ||
| 803 | #define DEV_ADDR 0x1f /* Device Address */ | |
| 804 | ||
| 805 | /* Bit masks for ATAPI_INT_MASK */ | |
| 806 | ||
| 807 | #define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ | |
| 808 | #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ | |
| 809 | #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ | |
| 810 | #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ | |
| 811 | #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ | |
| 812 | #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ | |
| 813 | #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ | |
| 814 | #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ | |
| 815 | #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ | |
| 816 | ||
| 817 | /* Bit masks for ATAPI_INT_STATUS */ | |
| 818 | ||
| 819 | #define ATAPI_DEV_INT 0x1 /* Device interrupt status */ | |
| 820 | #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ | |
| 821 | #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ | |
| 822 | #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ | |
| 823 | #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ | |
| 824 | #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ | |
| 825 | #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ | |
| 826 | #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ | |
| 827 | #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ | |
| 828 | ||
| 829 | /* Bit masks for ATAPI_LINE_STATUS */ | |
| 830 | ||
| 831 | #define ATAPI_INTR 0x1 /* Device interrupt to host line status */ | |
| 832 | #define ATAPI_DASP 0x2 /* Device dasp to host line status */ | |
| 833 | #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ | |
| 834 | #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ | |
| 835 | #define ATAPI_ADDR 0x70 /* ATAPI address line status */ | |
| 836 | #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ | |
| 837 | #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ | |
| 838 | #define ATAPI_DIOWN 0x200 /* ATAPI write line status */ | |
| 839 | #define ATAPI_DIORN 0x400 /* ATAPI read line status */ | |
| 840 | #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ | |
| 841 | ||
| 842 | /* Bit masks for ATAPI_SM_STATE */ | |
| 843 | ||
| 844 | #define PIO_CSTATE 0xf /* PIO mode state machine current state */ | |
| 845 | #define DMA_CSTATE 0xf0 /* DMA mode state machine current state */ | |
| 846 | #define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */ | |
| 847 | #define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */ | |
| 848 | ||
| 849 | /* Bit masks for ATAPI_TERMINATE */ | |
| 850 | ||
| 851 | #define ATAPI_HOST_TERM 0x1 /* Host terminationation */ | |
| 852 | ||
| 853 | /* Bit masks for ATAPI_REG_TIM_0 */ | |
| 854 | ||
| 855 | #define T2_REG 0xff /* End of cycle time for register access transfers */ | |
| 856 | #define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */ | |
| 857 | ||
| 858 | /* Bit masks for ATAPI_PIO_TIM_0 */ | |
| 859 | ||
| 860 | #define T1_REG 0xf /* Time from address valid to DIOR/DIOW */ | |
| 861 | #define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */ | |
| 862 | #define T4_REG 0xf000 /* DIOW data hold */ | |
| 863 | ||
| 864 | /* Bit masks for ATAPI_PIO_TIM_1 */ | |
| 865 | ||
| 866 | #define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */ | |
| 867 | ||
| 868 | /* Bit masks for ATAPI_MULTI_TIM_0 */ | |
| 869 | ||
| 870 | #define TD 0xff /* DIOR/DIOW asserted pulsewidth */ | |
| 871 | #define TM 0xff00 /* Time from address valid to DIOR/DIOW */ | |
| 872 | ||
| 873 | /* Bit masks for ATAPI_MULTI_TIM_1 */ | |
| 874 | ||
| 875 | #define TKW 0xff /* Selects DIOW negated pulsewidth */ | |
| 876 | #define TKR 0xff00 /* Selects DIOR negated pulsewidth */ | |
| 877 | ||
| 878 | /* Bit masks for ATAPI_MULTI_TIM_2 */ | |
| 879 | ||
| 880 | #define TH 0xff /* Selects DIOW data hold */ | |
| 881 | #define TEOC 0xff00 /* Selects end of cycle for DMA */ | |
| 882 | ||
| 883 | /* Bit masks for ATAPI_ULTRA_TIM_0 */ | |
| 884 | ||
| 885 | #define TACK 0xff /* Selects setup and hold times for TACK */ | |
| 886 | #define TENV 0xff00 /* Selects envelope time */ | |
| 887 | ||
| 888 | /* Bit masks for ATAPI_ULTRA_TIM_1 */ | |
| 889 | ||
| 890 | #define TDVS 0xff /* Selects data valid setup time */ | |
| 891 | #define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */ | |
| 892 | ||
| 893 | /* Bit masks for ATAPI_ULTRA_TIM_2 */ | |
| 894 | ||
| 895 | #define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */ | |
| 896 | #define TMLI 0xff00 /* Selects interlock time */ | |
| 897 | ||
| 898 | /* Bit masks for ATAPI_ULTRA_TIM_3 */ | |
| 899 | ||
| 900 | #define TZAH 0xff /* Selects minimum delay required for output */ | |
| 901 | #define READY_PAUSE 0xff00 /* Selects ready to pause */ | |
| 902 | ||
| 903 | /* Bit masks for TIMER_ENABLE1 */ | |
| 904 | ||
| 905 | #define TIMEN8 0x1 /* Timer 8 Enable */ | |
| 906 | #define TIMEN9 0x2 /* Timer 9 Enable */ | |
| 907 | #define TIMEN10 0x4 /* Timer 10 Enable */ | |
| 908 | ||
| 909 | /* Bit masks for TIMER_DISABLE1 */ | |
| 910 | ||
| 911 | #define TIMDIS8 0x1 /* Timer 8 Disable */ | |
| 912 | #define TIMDIS9 0x2 /* Timer 9 Disable */ | |
| 913 | #define TIMDIS10 0x4 /* Timer 10 Disable */ | |
| 914 | ||
| 915 | /* Bit masks for TIMER_STATUS1 */ | |
| 916 | ||
| 917 | #define TIMIL8 0x1 /* Timer 8 Interrupt */ | |
| 918 | #define TIMIL9 0x2 /* Timer 9 Interrupt */ | |
| 919 | #define TIMIL10 0x4 /* Timer 10 Interrupt */ | |
| 920 | #define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ | |
| 921 | #define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ | |
| 922 | #define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ | |
| 923 | #define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ | |
| 924 | #define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ | |
| 925 | #define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ | |
| 926 | ||
| 927 | /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ | |
| 928 | ||
| 929 | /* Bit masks for USB_FADDR */ | |
| 930 | ||
| 931 | #define FUNCTION_ADDRESS 0x7f /* Function address */ | |
| 932 | ||
| 933 | /* Bit masks for USB_POWER */ | |
| 934 | ||
| 935 | #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ | |
| 936 | #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ | |
| 937 | #define RESUME_MODE 0x4 /* DMA Mode */ | |
| 938 | #define RESET 0x8 /* Reset indicator */ | |
| 939 | #define HS_MODE 0x10 /* High Speed mode indicator */ | |
| 940 | #define HS_ENABLE 0x20 /* high Speed Enable */ | |
| 941 | #define SOFT_CONN 0x40 /* Soft connect */ | |
| 942 | #define ISO_UPDATE 0x80 /* Isochronous update */ | |
| 943 | ||
| 944 | /* Bit masks for USB_INTRTX */ | |
| 945 | ||
| 946 | #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ | |
| 947 | #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ | |
| 948 | #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ | |
| 949 | #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ | |
| 950 | #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ | |
| 951 | #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ | |
| 952 | #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ | |
| 953 | #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ | |
| 954 | ||
| 955 | /* Bit masks for USB_INTRRX */ | |
| 956 | ||
| 957 | #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ | |
| 958 | #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ | |
| 959 | #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ | |
| 960 | #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ | |
| 961 | #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ | |
| 962 | #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ | |
| 963 | #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ | |
| 964 | ||
| 965 | /* Bit masks for USB_INTRTXE */ | |
| 966 | ||
| 967 | #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ | |
| 968 | #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ | |
| 969 | #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ | |
| 970 | #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ | |
| 971 | #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ | |
| 972 | #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ | |
| 973 | #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ | |
| 974 | #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ | |
| 975 | ||
| 976 | /* Bit masks for USB_INTRRXE */ | |
| 977 | ||
| 978 | #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ | |
| 979 | #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ | |
| 980 | #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ | |
| 981 | #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ | |
| 982 | #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ | |
| 983 | #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ | |
| 984 | #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ | |
| 985 | ||
| 986 | /* Bit masks for USB_INTRUSB */ | |
| 987 | ||
| 988 | #define SUSPEND_B 0x1 /* Suspend indicator */ | |
| 989 | #define RESUME_B 0x2 /* Resume indicator */ | |
| 990 | #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ | |
| 991 | #define SOF_B 0x8 /* Start of frame */ | |
| 992 | #define CONN_B 0x10 /* Connection indicator */ | |
| 993 | #define DISCON_B 0x20 /* Disconnect indicator */ | |
| 994 | #define SESSION_REQ_B 0x40 /* Session Request */ | |
| 995 | #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ | |
| 996 | ||
| 997 | /* Bit masks for USB_INTRUSBE */ | |
| 998 | ||
| 999 | #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ | |
| 1000 | #define RESUME_BE 0x2 /* Resume indicator int enable */ | |
| 1001 | #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ | |
| 1002 | #define SOF_BE 0x8 /* Start of frame int enable */ | |
| 1003 | #define CONN_BE 0x10 /* Connection indicator int enable */ | |
| 1004 | #define DISCON_BE 0x20 /* Disconnect indicator int enable */ | |
| 1005 | #define SESSION_REQ_BE 0x40 /* Session Request int enable */ | |
| 1006 | #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ | |
| 1007 | ||
| 1008 | /* Bit masks for USB_FRAME */ | |
| 1009 | ||
| 1010 | #define FRAME_NUMBER 0x7ff /* Frame number */ | |
| 1011 | ||
| 1012 | /* Bit masks for USB_INDEX */ | |
| 1013 | ||
| 1014 | #define SELECTED_ENDPOINT 0xf /* selected endpoint */ | |
| 1015 | ||
| 1016 | /* Bit masks for USB_GLOBAL_CTL */ | |
| 1017 | ||
| 1018 | #define GLOBAL_ENA 0x1 /* enables USB module */ | |
| 1019 | #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ | |
| 1020 | #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ | |
| 1021 | #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ | |
| 1022 | #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ | |
| 1023 | #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ | |
| 1024 | #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ | |
| 1025 | #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ | |
| 1026 | #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ | |
| 1027 | #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ | |
| 1028 | #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ | |
| 1029 | #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ | |
| 1030 | #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ | |
| 1031 | #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ | |
| 1032 | #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ | |
| 1033 | ||
| 1034 | /* Bit masks for USB_OTG_DEV_CTL */ | |
| 1035 | ||
| 1036 | #define SESSION 0x1 /* session indicator */ | |
| 1037 | #define HOST_REQ 0x2 /* Host negotiation request */ | |
| 1038 | #define HOST_MODE 0x4 /* indicates USBDRC is a host */ | |
| 1039 | #define VBUS0 0x8 /* Vbus level indicator[0] */ | |
| 1040 | #define VBUS1 0x10 /* Vbus level indicator[1] */ | |
| 1041 | #define LSDEV 0x20 /* Low-speed indicator */ | |
| 1042 | #define FSDEV 0x40 /* Full or High-speed indicator */ | |
| 1043 | #define B_DEVICE 0x80 /* A' or 'B' device indicator */ | |
| 1044 | ||
| 1045 | /* Bit masks for USB_OTG_VBUS_IRQ */ | |
| 1046 | ||
| 1047 | #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ | |
| 1048 | #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ | |
| 1049 | #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ | |
| 1050 | #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ | |
| 1051 | #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ | |
| 1052 | #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ | |
| 1053 | ||
| 1054 | /* Bit masks for USB_OTG_VBUS_MASK */ | |
| 1055 | ||
| 1056 | #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ | |
| 1057 | #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ | |
| 1058 | #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ | |
| 1059 | #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ | |
| 1060 | #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ | |
| 1061 | #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ | |
| 1062 | ||
| 1063 | /* Bit masks for USB_CSR0 */ | |
| 1064 | ||
| 1065 | #define RXPKTRDY 0x1 /* data packet receive indicator */ | |
| 1066 | #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ | |
| 1067 | #define STALL_SENT 0x4 /* STALL handshake sent */ | |
| 1068 | #define DATAEND 0x8 /* Data end indicator */ | |
| 1069 | #define SETUPEND 0x10 /* Setup end */ | |
| 1070 | #define SENDSTALL 0x20 /* Send STALL handshake */ | |
| 1071 | #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ | |
| 1072 | #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ | |
| 1073 | #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ | |
| 1074 | #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ | |
| 1075 | #define SETUPPKT_H 0x8 /* send Setup token host mode */ | |
| 1076 | #define ERROR_H 0x10 /* timeout error indicator host mode */ | |
| 1077 | #define REQPKT_H 0x20 /* Request an IN transaction host mode */ | |
| 1078 | #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ | |
| 1079 | #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ | |
| 1080 | ||
| 1081 | /* Bit masks for USB_COUNT0 */ | |
| 1082 | ||
| 1083 | #define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ | |
| 1084 | ||
| 1085 | /* Bit masks for USB_NAKLIMIT0 */ | |
| 1086 | ||
| 1087 | #define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ | |
| 1088 | ||
| 1089 | /* Bit masks for USB_TX_MAX_PACKET */ | |
| 1090 | ||
| 1091 | #define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ | |
| 1092 | ||
| 1093 | /* Bit masks for USB_RX_MAX_PACKET */ | |
| 1094 | ||
| 1095 | #define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ | |
| 1096 | ||
| 1097 | /* Bit masks for USB_TXCSR */ | |
| 1098 | ||
| 1099 | #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ | |
| 1100 | #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ | |
| 1101 | #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ | |
| 1102 | #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ | |
| 1103 | #define STALL_SEND_T 0x10 /* issue a Stall handshake */ | |
| 1104 | #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ | |
| 1105 | #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ | |
| 1106 | #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ | |
| 1107 | #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ | |
| 1108 | #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ | |
| 1109 | #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ | |
| 1110 | #define ISO_T 0x4000 /* enable Isochronous transfers */ | |
| 1111 | #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ | |
| 1112 | #define ERROR_TH 0x4 /* error condition host mode */ | |
| 1113 | #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ | |
| 1114 | #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ | |
| 1115 | ||
| 1116 | /* Bit masks for USB_TXCOUNT */ | |
| 1117 | ||
| 1118 | #define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ | |
| 1119 | ||
| 1120 | /* Bit masks for USB_RXCSR */ | |
| 1121 | ||
| 1122 | #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ | |
| 1123 | #define FIFO_FULL_R 0x2 /* FIFO not empty */ | |
| 1124 | #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ | |
| 1125 | #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ | |
| 1126 | #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ | |
| 1127 | #define STALL_SEND_R 0x20 /* issue a Stall handshake */ | |
| 1128 | #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ | |
| 1129 | #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ | |
| 1130 | #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ | |
| 1131 | #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ | |
| 1132 | #define DISNYET_R 0x1000 /* disable Nyet handshakes */ | |
| 1133 | #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ | |
| 1134 | #define ISO_R 0x4000 /* enable Isochronous transfers */ | |
| 1135 | #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ | |
| 1136 | #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ | |
| 1137 | #define REQPKT_RH 0x20 /* request an IN transaction host mode */ | |
| 1138 | #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ | |
| 1139 | #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ | |
| 1140 | #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ | |
| 1141 | #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ | |
| 1142 | ||
| 1143 | /* Bit masks for USB_RXCOUNT */ | |
| 1144 | ||
| 1145 | #define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ | |
| 1146 | ||
| 1147 | /* Bit masks for USB_TXTYPE */ | |
| 1148 | ||
| 1149 | #define TARGET_EP_NO_T 0xf /* EP number */ | |
| 1150 | #define PROTOCOL_T 0xc /* transfer type */ | |
| 1151 | ||
| 1152 | /* Bit masks for USB_TXINTERVAL */ | |
| 1153 | ||
| 1154 | #define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ | |
| 1155 | ||
| 1156 | /* Bit masks for USB_RXTYPE */ | |
| 1157 | ||
| 1158 | #define TARGET_EP_NO_R 0xf /* EP number */ | |
| 1159 | #define PROTOCOL_R 0xc /* transfer type */ | |
| 1160 | ||
| 1161 | /* Bit masks for USB_RXINTERVAL */ | |
| 1162 | ||
| 1163 | #define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ | |
| 1164 | ||
| 1165 | /* Bit masks for USB_DMA_INTERRUPT */ | |
| 1166 | ||
| 1167 | #define DMA0_INT 0x1 /* DMA0 pending interrupt */ | |
| 1168 | #define DMA1_INT 0x2 /* DMA1 pending interrupt */ | |
| 1169 | #define DMA2_INT 0x4 /* DMA2 pending interrupt */ | |
| 1170 | #define DMA3_INT 0x8 /* DMA3 pending interrupt */ | |
| 1171 | #define DMA4_INT 0x10 /* DMA4 pending interrupt */ | |
| 1172 | #define DMA5_INT 0x20 /* DMA5 pending interrupt */ | |
| 1173 | #define DMA6_INT 0x40 /* DMA6 pending interrupt */ | |
| 1174 | #define DMA7_INT 0x80 /* DMA7 pending interrupt */ | |
| 1175 | ||
| 1176 | /* Bit masks for USB_DMAxCONTROL */ | |
| 1177 | ||
| 1178 | #define DMA_ENA 0x1 /* DMA enable */ | |
| 1179 | #define DIRECTION 0x2 /* direction of DMA transfer */ | |
| 1180 | #define MODE 0x4 /* DMA Bus error */ | |
| 1181 | #define INT_ENA 0x8 /* Interrupt enable */ | |
| 1182 | #define EPNUM 0xf0 /* EP number */ | |
| 1183 | #define BUSERROR 0x100 /* DMA Bus error */ | |
| 1184 | ||
| 1185 | /* Bit masks for USB_DMAxADDRHIGH */ | |
| 1186 | ||
| 1187 | #define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ | |
| 1188 | ||
| 1189 | /* Bit masks for USB_DMAxADDRLOW */ | |
| 1190 | ||
| 1191 | #define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ | |
| 1192 | ||
| 1193 | /* Bit masks for USB_DMAxCOUNTHIGH */ | |
| 1194 | ||
| 1195 | #define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ | |
| 1196 | ||
| 1197 | /* Bit masks for USB_DMAxCOUNTLOW */ | |
| 1198 | ||
| 1199 | #define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ | |
| 1200 | ||
| 1201 | /* Bit masks for HMDMAx_CONTROL */ | |
| 1202 | ||
| 1203 | #define HMDMAEN 0x1 /* Handshake MDMA Enable */ | |
| 1204 | #define REP 0x2 /* Handshake MDMA Request Polarity */ | |
| 1205 | #define UTE 0x8 /* Urgency Threshold Enable */ | |
| 1206 | #define OIE 0x10 /* Overflow Interrupt Enable */ | |
| 1207 | #define BDIE 0x20 /* Block Done Interrupt Enable */ | |
| 1208 | #define MBDI 0x40 /* Mask Block Done Interrupt */ | |
| 1209 | #define DRQ 0x300 /* Handshake MDMA Request Type */ | |
| 1210 | #define RBC 0x1000 /* Force Reload of BCOUNT */ | |
| 1211 | #define PS 0x2000 /* Pin Status */ | |
| 1212 | #define OI 0x4000 /* Overflow Interrupt Generated */ | |
| 1213 | #define BDI 0x8000 /* Block Done Interrupt Generated */ | |
| 1214 | ||
| 1215 | /* ******************************************* */ | |
| 1216 | /* MULTI BIT MACRO ENUMERATIONS */ | |
| 1217 | /* ******************************************* */ | |
| 1218 | ||
| 1219 | ||
| 4ed250a5 | 1220 | #endif /* _DEF_BF547_H */ |