Commit | Line | Data |
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2f6f4bcd | 1 | /* |
fa48f84a | 2 | * BF51x memory map |
2f6f4bcd | 3 | * |
fa48f84a MF |
4 | * Copyright 2004-2009 Analog Devices Inc. |
5 | * Licensed under the GPL-2 or later. | |
2f6f4bcd BW |
6 | */ |
7 | ||
fa48f84a MF |
8 | #ifndef __BFIN_MACH_MEM_MAP_H__ |
9 | #define __BFIN_MACH_MEM_MAP_H__ | |
2f6f4bcd | 10 | |
fa48f84a MF |
11 | #ifndef __BFIN_MEM_MAP_H__ |
12 | # error "do not include mach/mem_map.h directly -- use asm/mem_map.h" | |
13 | #endif | |
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14 | |
15 | /* Async Memory Banks */ | |
16 | #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ | |
17 | #define ASYNC_BANK3_SIZE 0x00100000 /* 1M */ | |
18 | #define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */ | |
19 | #define ASYNC_BANK2_SIZE 0x00100000 /* 1M */ | |
20 | #define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */ | |
21 | #define ASYNC_BANK1_SIZE 0x00100000 /* 1M */ | |
22 | #define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ | |
23 | #define ASYNC_BANK0_SIZE 0x00100000 /* 1M */ | |
24 | ||
25 | /* Boot ROM Memory */ | |
26 | ||
27 | #define BOOT_ROM_START 0xEF000000 | |
28 | #define BOOT_ROM_LENGTH 0x8000 | |
29 | ||
30 | /* Level 1 Memory */ | |
31 | ||
32 | /* Memory Map for ADSP-BF518/6/4/2 processors */ | |
33 | ||
34 | #ifdef CONFIG_BFIN_ICACHE | |
35 | #define BFIN_ICACHESIZE (16 * 1024) | |
36 | #else | |
37 | #define BFIN_ICACHESIZE (0) | |
38 | #endif | |
39 | ||
40 | #define L1_CODE_START 0xFFA00000 | |
41 | #define L1_DATA_A_START 0xFF800000 | |
42 | #define L1_DATA_B_START 0xFF900000 | |
43 | ||
1dafdc51 | 44 | #define L1_CODE_LENGTH 0x8000 |
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45 | |
46 | #ifdef CONFIG_BFIN_DCACHE | |
47 | ||
48 | #ifdef CONFIG_BFIN_DCACHE_BANKA | |
49 | #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) | |
50 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) | |
51 | #define L1_DATA_B_LENGTH 0x8000 | |
52 | #define BFIN_DCACHESIZE (16 * 1024) | |
53 | #define BFIN_DSUPBANKS 1 | |
54 | #else | |
55 | #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) | |
56 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) | |
57 | #define L1_DATA_B_LENGTH (0x8000 - 0x4000) | |
58 | #define BFIN_DCACHESIZE (32 * 1024) | |
59 | #define BFIN_DSUPBANKS 2 | |
60 | #endif | |
61 | ||
62 | #else | |
63 | #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) | |
64 | #define L1_DATA_A_LENGTH 0x8000 | |
65 | #define L1_DATA_B_LENGTH 0x8000 | |
66 | #define BFIN_DCACHESIZE 0 | |
67 | #define BFIN_DSUPBANKS 0 | |
68 | #endif /*CONFIG_BFIN_DCACHE */ | |
69 | ||
fa48f84a | 70 | #endif |