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[linux-block.git] / arch / blackfin / mach-bf518 / boards / ezbrd.c
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2f6f4bcd
BW		 1/*
2 * File: arch/blackfin/mach-bf518/boards/ezbrd.c
3 * Based on: arch/blackfin/mach-bf527/boards/ezbrd.c
4 * Author: Bryan Wu <cooloney@kernel.org>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2008 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <linux/mtd/mtd.h>
34#include <linux/mtd/partitions.h>
35#include <linux/mtd/physmap.h>
36#include <linux/spi/spi.h>
37#include <linux/spi/flash.h>
38
39#include <linux/i2c.h>
40#include <linux/irq.h>
41#include <linux/interrupt.h>
42#include <asm/dma.h>
43#include <asm/bfin5xx_spi.h>
44#include <asm/reboot.h>
45#include <asm/portmux.h>
46#include <asm/dpmc.h>
501674a5 47#include <asm/bfin_sdh.h>
2f6f4bcd 48#include <linux/spi/ad7877.h>
65319628 49#include <net/dsa.h>
2f6f4bcd
BW		 50
51/*
52 * Name the Board for the /proc/cpuinfo
53 */
fe85cad2 54const char bfin_board_name[] = "ADI BF518F-EZBRD";
2f6f4bcd
BW		 55
56/*
57 * Driver needs to know address, irq and flag pin.
58 */
59
60#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
61static struct mtd_partition ezbrd_partitions[] = {
62 {
63 .name = "bootloader(nor)",
64 .size = 0x40000,
65 .offset = 0,
66 }, {
67 .name = "linux kernel(nor)",
68 .size = 0x1C0000,
69 .offset = MTDPART_OFS_APPEND,
70 }, {
71 .name = "file system(nor)",
72 .size = MTDPART_SIZ_FULL,
73 .offset = MTDPART_OFS_APPEND,
74 }
75};
76
77static struct physmap_flash_data ezbrd_flash_data = {
78 .width = 2,
79 .parts = ezbrd_partitions,
80 .nr_parts = ARRAY_SIZE(ezbrd_partitions),
81};
82
83static struct resource ezbrd_flash_resource = {
84 .start = 0x20000000,
85 .end = 0x203fffff,
86 .flags = IORESOURCE_MEM,
87};
88
89static struct platform_device ezbrd_flash_device = {
90 .name = "physmap-flash",
91 .id = 0,
92 .dev = {
93 .platform_data = &ezbrd_flash_data,
94 },
95 .num_resources = 1,
96 .resource = &ezbrd_flash_resource,
97};
98#endif
99
100#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
101static struct platform_device rtc_device = {
102 .name = "rtc-bfin",
103 .id = -1,
104};
105#endif
106
107#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628
GY		 108static struct platform_device bfin_mii_bus = {
109 .name = "bfin_mii_bus",
110};
111
2f6f4bcd
BW		 112static struct platform_device bfin_mac_device = {
113 .name = "bfin_mac",
65319628
GY		 114 .dev.platform_data = &bfin_mii_bus,
115};
65319628
GY		 116
117#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
118static struct dsa_platform_data ksz8893m_switch_data = {
119 .mii_bus = &bfin_mii_bus.dev,
120 .netdev = &bfin_mac_device.dev,
121 .port_names[0] = NULL,
122 .port_names[1] = "eth%d",
123 .port_names[2] = "eth%d",
124 .port_names[3] = "cpu",
125};
126
127static struct platform_device ksz8893m_switch_device = {
128 .name = "dsa",
129 .id = 0,
130 .num_resources = 0,
131 .dev.platform_data = &ksz8893m_switch_data,
2f6f4bcd
BW		 132};
133#endif
c19577e3 134#endif
2f6f4bcd
BW		 135
136#if defined(CONFIG_MTD_M25P80) \
137 || defined(CONFIG_MTD_M25P80_MODULE)
138static struct mtd_partition bfin_spi_flash_partitions[] = {
139 {
140 .name = "bootloader(spi)",
141 .size = 0x00040000,
142 .offset = 0,
143 .mask_flags = MTD_CAP_ROM
144 }, {
145 .name = "linux kernel(spi)",
146 .size = MTDPART_SIZ_FULL,
147 .offset = MTDPART_OFS_APPEND,
148 }
149};
150
151static struct flash_platform_data bfin_spi_flash_data = {
152 .name = "m25p80",
153 .parts = bfin_spi_flash_partitions,
154 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
155 .type = "m25p16",
156};
157
158/* SPI flash chip (m25p64) */
159static struct bfin5xx_spi_chip spi_flash_chip_info = {
160 .enable_dma = 0, /* use dma transfer with this chip*/
161 .bits_per_word = 8,
162};
163#endif
164
165#if defined(CONFIG_SPI_ADC_BF533) \
166 || defined(CONFIG_SPI_ADC_BF533_MODULE)
167/* SPI ADC chip */
168static struct bfin5xx_spi_chip spi_adc_chip_info = {
169 .enable_dma = 1, /* use dma transfer with this chip*/
170 .bits_per_word = 16,
171};
172#endif
173
c19577e3 174#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628
GY		 175#if defined(CONFIG_NET_DSA_KSZ8893M) \
176 || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
177/* SPI SWITCH CHIP */
178static struct bfin5xx_spi_chip spi_switch_info = {
179 .enable_dma = 0,
180 .bits_per_word = 8,
181};
182#endif
c19577e3 183#endif
65319628 184
f3f704d3
MH		 185#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
186static struct bfin5xx_spi_chip mmc_spi_chip_info = {
187 .enable_dma = 0,
2f6f4bcd
BW		 188 .bits_per_word = 8,
189};
190#endif
191
192#if defined(CONFIG_PBX)
193static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
194 .ctl_reg = 0x4, /* send zero */
195 .enable_dma = 0,
196 .bits_per_word = 8,
197 .cs_change_per_word = 1,
198};
199#endif
200
201#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
202static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
203 .enable_dma = 0,
204 .bits_per_word = 16,
205};
206
207static const struct ad7877_platform_data bfin_ad7877_ts_info = {
208 .model = 7877,
209 .vref_delay_usecs = 50, /* internal, no capacitor */
210 .x_plate_ohms = 419,
211 .y_plate_ohms = 486,
212 .pressure_max = 1000,
213 .pressure_min = 0,
214 .stopacq_polarity = 1,
215 .first_conversion_delay = 3,
216 .acquisition_time = 1,
217 .averaging = 1,
218 .pen_down_acc_interval = 1,
219};
220#endif
221
222#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
223 && defined(CONFIG_SND_SOC_WM8731_SPI)
224static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
225 .enable_dma = 0,
226 .bits_per_word = 16,
227};
228#endif
229
230#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
231static struct bfin5xx_spi_chip spidev_chip_info = {
232 .enable_dma = 0,
233 .bits_per_word = 8,
234};
235#endif
236
237static struct spi_board_info bfin_spi_board_info[] __initdata = {
238#if defined(CONFIG_MTD_M25P80) \
239 || defined(CONFIG_MTD_M25P80_MODULE)
240 {
241 /* the modalias must be the same as spi device driver name */
242 .modalias = "m25p80", /* Name of spi_driver for this device */
243 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
244 .bus_num = 0, /* Framework bus number */
245 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
246 .platform_data = &bfin_spi_flash_data,
247 .controller_data = &spi_flash_chip_info,
248 .mode = SPI_MODE_3,
249 },
250#endif
251
252#if defined(CONFIG_SPI_ADC_BF533) \
253 || defined(CONFIG_SPI_ADC_BF533_MODULE)
254 {
255 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
256 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
257 .bus_num = 0, /* Framework bus number */
258 .chip_select = 1, /* Framework chip select. */
259 .platform_data = NULL, /* No spi_driver specific config */
260 .controller_data = &spi_adc_chip_info,
261 },
262#endif
263
c19577e3 264#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628
GY		 265#if defined(CONFIG_NET_DSA_KSZ8893M) \
266 || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
267 {
268 .modalias = "ksz8893m",
269 .max_speed_hz = 5000000,
270 .bus_num = 0,
271 .chip_select = 1,
272 .platform_data = NULL,
273 .controller_data = &spi_switch_info,
274 .mode = SPI_MODE_3,
275 },
276#endif
c19577e3 277#endif
65319628 278
f3f704d3 279#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
2f6f4bcd 280 {
f3f704d3 281 .modalias = "mmc_spi",
2f6f4bcd
BW		 282 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
283 .bus_num = 0,
f3f704d3
MH		 284 .chip_select = 5,
285 .controller_data = &mmc_spi_chip_info,
2f6f4bcd
BW		 286 .mode = SPI_MODE_3,
287 },
288#endif
289#if defined(CONFIG_PBX)
290 {
291 .modalias = "fxs-spi",
292 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
293 .bus_num = 0,
294 .chip_select = 8 - CONFIG_J11_JUMPER,
295 .controller_data = &spi_si3xxx_chip_info,
296 .mode = SPI_MODE_3,
297 },
298 {
299 .modalias = "fxo-spi",
300 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
301 .bus_num = 0,
302 .chip_select = 8 - CONFIG_J19_JUMPER,
303 .controller_data = &spi_si3xxx_chip_info,
304 .mode = SPI_MODE_3,
305 },
306#endif
307#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
308 {
309 .modalias = "ad7877",
310 .platform_data = &bfin_ad7877_ts_info,
311 .irq = IRQ_PF8,
312 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
313 .bus_num = 0,
314 .chip_select = 2,
315 .controller_data = &spi_ad7877_chip_info,
316 },
317#endif
318#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
319 && defined(CONFIG_SND_SOC_WM8731_SPI)
320 {
321 .modalias = "wm8731",
322 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
323 .bus_num = 0,
324 .chip_select = 5,
325 .controller_data = &spi_wm8731_chip_info,
326 .mode = SPI_MODE_0,
327 },
328#endif
329#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
330 {
331 .modalias = "spidev",
332 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
333 .bus_num = 0,
334 .chip_select = 1,
335 .controller_data = &spidev_chip_info,
336 },
337#endif
338#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
339 {
340 .modalias = "bfin-lq035q1-spi",
341 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
342 .bus_num = 0,
343 .chip_select = 1,
344 .controller_data = &lq035q1_spi_chip_info,
345 .mode = SPI_CPHA | SPI_CPOL,
346 },
347#endif
348};
349
350/* SPI controller data */
351#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
352/* SPI (0) */
353static struct bfin5xx_spi_master bfin_spi0_info = {
354 .num_chipselect = 5,
355 .enable_dma = 1, /* master has the ability to do dma transfer */
356 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
357};
358
359static struct resource bfin_spi0_resource[] = {
360 [0] = {
361 .start = SPI0_REGBASE,
362 .end = SPI0_REGBASE + 0xFF,
363 .flags = IORESOURCE_MEM,
364 },
365 [1] = {
366 .start = CH_SPI0,
367 .end = CH_SPI0,
368 .flags = IORESOURCE_IRQ,
369 },
370};
371
372static struct platform_device bfin_spi0_device = {
373 .name = "bfin-spi",
374 .id = 0, /* Bus number */
375 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
376 .resource = bfin_spi0_resource,
377 .dev = {
378 .platform_data = &bfin_spi0_info, /* Passed to driver */
379 },
380};
381
382/* SPI (1) */
383static struct bfin5xx_spi_master bfin_spi1_info = {
384 .num_chipselect = 5,
385 .enable_dma = 1, /* master has the ability to do dma transfer */
386 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
387};
388
389static struct resource bfin_spi1_resource[] = {
390 [0] = {
391 .start = SPI1_REGBASE,
392 .end = SPI1_REGBASE + 0xFF,
393 .flags = IORESOURCE_MEM,
394 },
395 [1] = {
396 .start = CH_SPI1,
397 .end = CH_SPI1,
398 .flags = IORESOURCE_IRQ,
399 },
400};
401
402static struct platform_device bfin_spi1_device = {
403 .name = "bfin-spi",
404 .id = 1, /* Bus number */
405 .num_resources = ARRAY_SIZE(bfin_spi1_resource),
406 .resource = bfin_spi1_resource,
407 .dev = {
408 .platform_data = &bfin_spi1_info, /* Passed to driver */
409 },
410};
411#endif /* spi master and devices */
412
413#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
414static struct resource bfin_uart_resources[] = {
415#ifdef CONFIG_SERIAL_BFIN_UART0
416 {
417 .start = 0xFFC00400,
418 .end = 0xFFC004FF,
419 .flags = IORESOURCE_MEM,
420 },
421#endif
422#ifdef CONFIG_SERIAL_BFIN_UART1
423 {
424 .start = 0xFFC02000,
425 .end = 0xFFC020FF,
426 .flags = IORESOURCE_MEM,
427 },
428#endif
429};
430
431static struct platform_device bfin_uart_device = {
432 .name = "bfin-uart",
433 .id = 1,
434 .num_resources = ARRAY_SIZE(bfin_uart_resources),
435 .resource = bfin_uart_resources,
436};
437#endif
438
439#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
2f6f4bcd 440#ifdef CONFIG_BFIN_SIR0
42bd8bcb 441static struct resource bfin_sir0_resources[] = {
2f6f4bcd
BW		 442 {
443 .start = 0xFFC00400,
444 .end = 0xFFC004FF,
445 .flags = IORESOURCE_MEM,
446 },
42bd8bcb
GY		 447 {
448 .start = IRQ_UART0_RX,
449 .end = IRQ_UART0_RX+1,
450 .flags = IORESOURCE_IRQ,
451 },
452 {
453 .start = CH_UART0_RX,
454 .end = CH_UART0_RX+1,
455 .flags = IORESOURCE_DMA,
456 },
457};
458
459static struct platform_device bfin_sir0_device = {
460 .name = "bfin_sir",
461 .id = 0,
462 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
463 .resource = bfin_sir0_resources,
464};
2f6f4bcd
BW		 465#endif
466#ifdef CONFIG_BFIN_SIR1
42bd8bcb 467static struct resource bfin_sir1_resources[] = {
2f6f4bcd
BW		 468 {
469 .start = 0xFFC02000,
470 .end = 0xFFC020FF,
471 .flags = IORESOURCE_MEM,
472 },
42bd8bcb
GY		 473 {
474 .start = IRQ_UART1_RX,
475 .end = IRQ_UART1_RX+1,
476 .flags = IORESOURCE_IRQ,
477 },
478 {
479 .start = CH_UART1_RX,
480 .end = CH_UART1_RX+1,
481 .flags = IORESOURCE_DMA,
482 },
2f6f4bcd
BW		 483};
484
42bd8bcb 485static struct platform_device bfin_sir1_device = {
2f6f4bcd 486 .name = "bfin_sir",
42bd8bcb
GY		 487 .id = 1,
488 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
489 .resource = bfin_sir1_resources,
2f6f4bcd
BW		 490};
491#endif
42bd8bcb 492#endif
2f6f4bcd
BW		 493
494#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
495static struct resource bfin_twi0_resource[] = {
496 [0] = {
497 .start = TWI0_REGBASE,
498 .end = TWI0_REGBASE,
499 .flags = IORESOURCE_MEM,
500 },
501 [1] = {
502 .start = IRQ_TWI,
503 .end = IRQ_TWI,
504 .flags = IORESOURCE_IRQ,
505 },
506};
507
508static struct platform_device i2c_bfin_twi_device = {
509 .name = "i2c-bfin-twi",
510 .id = 0,
511 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
512 .resource = bfin_twi0_resource,
513};
514#endif
515
2f6f4bcd
BW		 516static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
517#if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
518 {
519 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
520 },
521#endif
522#if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE)
523 {
524 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
525 .irq = IRQ_PF8,
526 },
527#endif
528};
2f6f4bcd
BW		 529
530#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
531static struct platform_device bfin_sport0_uart_device = {
532 .name = "bfin-sport-uart",
533 .id = 0,
534};
535
536static struct platform_device bfin_sport1_uart_device = {
537 .name = "bfin-sport-uart",
538 .id = 1,
539};
540#endif
541
542#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
543#include <linux/input.h>
544#include <linux/gpio_keys.h>
545
546static struct gpio_keys_button bfin_gpio_keys_table[] = {
547 {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
548 {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
549};
550
551static struct gpio_keys_platform_data bfin_gpio_keys_data = {
552 .buttons = bfin_gpio_keys_table,
553 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
554};
555
556static struct platform_device bfin_device_gpiokeys = {
557 .name = "gpio-keys",
558 .dev = {
559 .platform_data = &bfin_gpio_keys_data,
560 },
561};
562#endif
563
501674a5
CC		 564#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
565
566static struct bfin_sd_host bfin_sdh_data = {
567 .dma_chan = CH_RSI,
568 .irq_int0 = IRQ_RSI_INT0,
569 .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
570};
571
572static struct platform_device bf51x_sdh_device = {
573 .name = "bfin-sdh",
574 .id = 0,
575 .dev = {
576 .platform_data = &bfin_sdh_data,
577 },
578};
579#endif
580
2f6f4bcd
BW		 581static struct resource bfin_gpios_resources = {
582 .start = 0,
583 .end = MAX_BLACKFIN_GPIOS - 1,
584 .flags = IORESOURCE_IRQ,
585};
586
587static struct platform_device bfin_gpios_device = {
588 .name = "simple-gpio",
589 .id = -1,
590 .num_resources = 1,
591 .resource = &bfin_gpios_resources,
592};
593
594static const unsigned int cclk_vlev_datasheet[] =
595{
596 VRPAIR(VLEV_100, 400000000),
597 VRPAIR(VLEV_105, 426000000),
598 VRPAIR(VLEV_110, 500000000),
599 VRPAIR(VLEV_115, 533000000),
600 VRPAIR(VLEV_120, 600000000),
601};
602
603static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
604 .tuple_tab = cclk_vlev_datasheet,
605 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
606 .vr_settling_time = 25 /* us */,
607};
608
609static struct platform_device bfin_dpmc = {
610 .name = "bfin dpmc",
611 .dev = {
612 .platform_data = &bfin_dmpc_vreg_data,
613 },
614};
615
616static struct platform_device *stamp_devices[] __initdata = {
617
618 &bfin_dpmc,
619
620#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
621 &rtc_device,
622#endif
623
624#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628 625 &bfin_mii_bus,
2f6f4bcd 626 &bfin_mac_device,
65319628
GY		 627#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
628 &ksz8893m_switch_device,
629#endif
c19577e3 630#endif
65319628 631
2f6f4bcd
BW		 632#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
633 &bfin_spi0_device,
634 &bfin_spi1_device,
635#endif
636
637#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
638 &bfin_uart_device,
639#endif
640
641#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 642#ifdef CONFIG_BFIN_SIR0
643 &bfin_sir0_device,
644#endif
645#ifdef CONFIG_BFIN_SIR1
646 &bfin_sir1_device,
647#endif
2f6f4bcd
BW		 648#endif
649
650#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
651 &i2c_bfin_twi_device,
652#endif
653
654#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
655 &bfin_sport0_uart_device,
656 &bfin_sport1_uart_device,
657#endif
658
659#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
660 &bfin_device_gpiokeys,
661#endif
662
501674a5
CC		 663#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
664 &bf51x_sdh_device,
665#endif
666
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BW		 667#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
668 &ezbrd_flash_device,
669#endif
670
671 &bfin_gpios_device,
672};
673
674static int __init ezbrd_init(void)
675{
676 printk(KERN_INFO "%s(): registering device resources\n", __func__);
2f6f4bcd
BW		 677 i2c_register_board_info(0, bfin_i2c_board_info,
678 ARRAY_SIZE(bfin_i2c_board_info));
2f6f4bcd
BW		 679 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
680 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
681 return 0;
682}
683
684arch_initcall(ezbrd_init);
685
686void native_machine_restart(char *cmd)
687{
688 /* workaround reboot hang when booting from SPI */
689 if ((bfin_read_SYSCR() & 0x7) == 0x3)
b52dae31 690 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
2f6f4bcd
BW		 691}
692
693void bfin_get_ether_addr(char *addr)
694{
695 /* the MAC is stored in OTP memory page 0xDF */
696 u32 ret;
697 u64 otp_mac;
698 u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
699
700 ret = otp_read(0xDF, 0x00, &otp_mac);
701 if (!(ret & 0x1)) {
702 char *otp_mac_p = (char *)&otp_mac;
703 for (ret = 0; ret < 6; ++ret)
704 addr[ret] = otp_mac_p[5 - ret];
705 }
706}
707EXPORT_SYMBOL(bfin_get_ether_addr);
Linux 6.x block layer and io_uring tree(s)