[linux-2.6-block.git] / arch / blackfin / kernel / time-ts.c

/*
 * Based on arm clockevents implementation and old bfin time tick.
 *
 * Copyright 2008-2009 Analog Devics Inc.
 *                2008 GeoTechnologies
 *                     Vitja Makarov
 *
 * Licensed under the GPL-2
 */

#include <linux/module.h>
#include <linux/profile.h>
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/timex.h>
#include <linux/irq.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/cpufreq.h>

#include <asm/blackfin.h>
#include <asm/time.h>
#include <asm/gptimers.h>
#include <asm/nmi.h>


#if defined(CONFIG_CYCLES_CLOCKSOURCE)

static notrace cycle_t bfin_read_cycles(struct clocksource *cs)
{
#ifdef CONFIG_CPU_FREQ
	return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod);
#else
	return get_cycles();
#endif
}

static struct clocksource bfin_cs_cycles = {
	.name		= "bfin_cs_cycles",
	.rating		= 400,
	.read		= bfin_read_cycles,
	.mask		= CLOCKSOURCE_MASK(64),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static inline unsigned long long bfin_cs_cycles_sched_clock(void)
{
	return clocksource_cyc2ns(bfin_read_cycles(&bfin_cs_cycles),
		bfin_cs_cycles.mult, bfin_cs_cycles.shift);
}

static int __init bfin_cs_cycles_init(void)
{
	if (clocksource_register_hz(&bfin_cs_cycles, get_cclk()))
		panic("failed to register clocksource");

	return 0;
}
#else
# define bfin_cs_cycles_init()
#endif

#ifdef CONFIG_GPTMR0_CLOCKSOURCE

void __init setup_gptimer0(void)
{
	disable_gptimers(TIMER0bit);

#ifdef CONFIG_BF60x
	bfin_write16(TIMER_DATA_IMSK, 0);
	set_gptimer_config(TIMER0_id,  TIMER_OUT_DIS
		| TIMER_MODE_PWM_CONT | TIMER_PULSE_HI | TIMER_IRQ_PER);
#else
	set_gptimer_config(TIMER0_id, \
		TIMER_OUT_DIS | TIMER_PERIOD_CNT | TIMER_MODE_PWM);
#endif
	set_gptimer_period(TIMER0_id, -1);
	set_gptimer_pwidth(TIMER0_id, -2);
	SSYNC();
	enable_gptimers(TIMER0bit);
}

static cycle_t bfin_read_gptimer0(struct clocksource *cs)
{
	return bfin_read_TIMER0_COUNTER();
}

static struct clocksource bfin_cs_gptimer0 = {
	.name		= "bfin_cs_gptimer0",
	.rating		= 350,
	.read		= bfin_read_gptimer0,
	.mask		= CLOCKSOURCE_MASK(32),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static inline unsigned long long bfin_cs_gptimer0_sched_clock(void)
{
	return clocksource_cyc2ns(bfin_read_TIMER0_COUNTER(),
		bfin_cs_gptimer0.mult, bfin_cs_gptimer0.shift);
}

static int __init bfin_cs_gptimer0_init(void)
{
	setup_gptimer0();

	if (clocksource_register_hz(&bfin_cs_gptimer0, get_sclk()))
		panic("failed to register clocksource");

	return 0;
}
#else
# define bfin_cs_gptimer0_init()
#endif

#if defined(CONFIG_GPTMR0_CLOCKSOURCE) || defined(CONFIG_CYCLES_CLOCKSOURCE)
/* prefer to use cycles since it has higher rating */
notrace unsigned long long sched_clock(void)
{
#if defined(CONFIG_CYCLES_CLOCKSOURCE)
	return bfin_cs_cycles_sched_clock();
#else
	return bfin_cs_gptimer0_sched_clock();
#endif
}
#endif

#if defined(CONFIG_TICKSOURCE_GPTMR0)
static int bfin_gptmr0_set_next_event(unsigned long cycles,
                                     struct clock_event_device *evt)
{
	disable_gptimers(TIMER0bit);

	/* it starts counting three SCLK cycles after the TIMENx bit is set */
	set_gptimer_pwidth(TIMER0_id, cycles - 3);
	enable_gptimers(TIMER0bit);
	return 0;
}

static int bfin_gptmr0_set_periodic(struct clock_event_device *evt)
{
#ifndef CONFIG_BF60x
	set_gptimer_config(TIMER0_id,
			   TIMER_OUT_DIS | TIMER_IRQ_ENA |
			   TIMER_PERIOD_CNT | TIMER_MODE_PWM);
#else
	set_gptimer_config(TIMER0_id,
			   TIMER_OUT_DIS | TIMER_MODE_PWM_CONT |
			   TIMER_PULSE_HI | TIMER_IRQ_PER);
#endif

	set_gptimer_period(TIMER0_id, get_sclk() / HZ);
	set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1);
	enable_gptimers(TIMER0bit);
	return 0;
}

static int bfin_gptmr0_set_oneshot(struct clock_event_device *evt)
{
	disable_gptimers(TIMER0bit);
#ifndef CONFIG_BF60x
	set_gptimer_config(TIMER0_id,
			   TIMER_OUT_DIS | TIMER_IRQ_ENA | TIMER_MODE_PWM);
#else
	set_gptimer_config(TIMER0_id,
			   TIMER_OUT_DIS | TIMER_MODE_PWM | TIMER_PULSE_HI |
			   TIMER_IRQ_WID_DLY);
#endif

	set_gptimer_period(TIMER0_id, 0);
	return 0;
}

static int bfin_gptmr0_shutdown(struct clock_event_device *evt)
{
	disable_gptimers(TIMER0bit);
	return 0;
}

static void bfin_gptmr0_ack(void)
{
	clear_gptimer_intr(TIMER0_id);
}

static void __init bfin_gptmr0_init(void)
{
	disable_gptimers(TIMER0bit);
}

#ifdef CONFIG_CORE_TIMER_IRQ_L1
__attribute__((l1_text))
#endif
irqreturn_t bfin_gptmr0_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;
	smp_mb();
	/*
	 * We want to ACK before we handle so that we can handle smaller timer
	 * intervals.  This way if the timer expires again while we're handling
	 * things, we're more likely to see that 2nd int rather than swallowing
	 * it by ACKing the int at the end of this handler.
	 */
	bfin_gptmr0_ack();
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static struct irqaction gptmr0_irq = {
	.name		= "Blackfin GPTimer0",
	.flags		= IRQF_TIMER | IRQF_IRQPOLL | IRQF_PERCPU,
	.handler	= bfin_gptmr0_interrupt,
};

static struct clock_event_device clockevent_gptmr0 = {
	.name			= "bfin_gptimer0",
	.rating			= 300,
	.irq			= IRQ_TIMER0,
	.shift			= 32,
	.features		= CLOCK_EVT_FEAT_PERIODIC |
				  CLOCK_EVT_FEAT_ONESHOT,
	.set_next_event		= bfin_gptmr0_set_next_event,
	.set_state_shutdown	= bfin_gptmr0_shutdown,
	.set_state_periodic	= bfin_gptmr0_set_periodic,
	.set_state_oneshot	= bfin_gptmr0_set_oneshot,
};

static void __init bfin_gptmr0_clockevent_init(struct clock_event_device *evt)
{
	unsigned long clock_tick;

	clock_tick = get_sclk();
	evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift);
	evt->max_delta_ns = clockevent_delta2ns(-1, evt);
	evt->min_delta_ns = clockevent_delta2ns(100, evt);

	evt->cpumask = cpumask_of(0);

	clockevents_register_device(evt);
}
#endif /* CONFIG_TICKSOURCE_GPTMR0 */

#if defined(CONFIG_TICKSOURCE_CORETMR)
/* per-cpu local core timer */
DEFINE_PER_CPU(struct clock_event_device, coretmr_events);

static int bfin_coretmr_set_next_event(unsigned long cycles,
				struct clock_event_device *evt)
{
	bfin_write_TCNTL(TMPWR);
	CSYNC();
	bfin_write_TCOUNT(cycles);
	CSYNC();
	bfin_write_TCNTL(TMPWR | TMREN);
	return 0;
}

static int bfin_coretmr_set_periodic(struct clock_event_device *evt)
{
	unsigned long tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1);

	bfin_write_TCNTL(TMPWR);
	CSYNC();
	bfin_write_TSCALE(TIME_SCALE - 1);
	bfin_write_TPERIOD(tcount);
	bfin_write_TCOUNT(tcount);
	CSYNC();
	bfin_write_TCNTL(TMPWR | TMREN | TAUTORLD);
	return 0;
}

static int bfin_coretmr_set_oneshot(struct clock_event_device *evt)
{
	bfin_write_TCNTL(TMPWR);
	CSYNC();
	bfin_write_TSCALE(TIME_SCALE - 1);
	bfin_write_TPERIOD(0);
	bfin_write_TCOUNT(0);
	return 0;
}

static int bfin_coretmr_shutdown(struct clock_event_device *evt)
{
	bfin_write_TCNTL(0);
	CSYNC();
	return 0;
}

void bfin_coretmr_init(void)
{
	/* power up the timer, but don't enable it just yet */
	bfin_write_TCNTL(TMPWR);
	CSYNC();

	/* the TSCALE prescaler counter. */
	bfin_write_TSCALE(TIME_SCALE - 1);
	bfin_write_TPERIOD(0);
	bfin_write_TCOUNT(0);

	CSYNC();
}

#ifdef CONFIG_CORE_TIMER_IRQ_L1
__attribute__((l1_text))
#endif

irqreturn_t bfin_coretmr_interrupt(int irq, void *dev_id)
{
	int cpu = smp_processor_id();
	struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);

	smp_mb();
	evt->event_handler(evt);

	touch_nmi_watchdog();

	return IRQ_HANDLED;
}

static struct irqaction coretmr_irq = {
	.name		= "Blackfin CoreTimer",
	.flags		= IRQF_TIMER | IRQF_IRQPOLL | IRQF_PERCPU,
	.handler	= bfin_coretmr_interrupt,
};

void bfin_coretmr_clockevent_init(void)
{
	unsigned long clock_tick;
	unsigned int cpu = smp_processor_id();
	struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);

#ifdef CONFIG_SMP
	evt->broadcast = smp_timer_broadcast;
#endif

	evt->name = "bfin_core_timer";
	evt->rating = 350;
	evt->irq = -1;
	evt->shift = 32;
	evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
	evt->set_next_event = bfin_coretmr_set_next_event;
	evt->set_state_shutdown = bfin_coretmr_shutdown;
	evt->set_state_periodic = bfin_coretmr_set_periodic;
	evt->set_state_oneshot = bfin_coretmr_set_oneshot;

	clock_tick = get_cclk() / TIME_SCALE;
	evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift);
	evt->max_delta_ns = clockevent_delta2ns(-1, evt);
	evt->min_delta_ns = clockevent_delta2ns(100, evt);

	evt->cpumask = cpumask_of(cpu);

	clockevents_register_device(evt);
}
#endif /* CONFIG_TICKSOURCE_CORETMR */


void read_persistent_clock(struct timespec *ts)
{
	time_t secs_since_1970 = (365 * 37 + 9) * 24 * 60 * 60;	/* 1 Jan 2007 */
	ts->tv_sec = secs_since_1970;
	ts->tv_nsec = 0;
}

void __init time_init(void)
{

#ifdef CONFIG_RTC_DRV_BFIN
	/* [#2663] hack to filter junk RTC values that would cause
	 * userspace to have to deal with time values greater than
	 * 2^31 seconds (which uClibc cannot cope with yet)
	 */
	if ((bfin_read_RTC_STAT() & 0xC0000000) == 0xC0000000) {
		printk(KERN_NOTICE "bfin-rtc: invalid date; resetting\n");
		bfin_write_RTC_STAT(0);
	}
#endif

	bfin_cs_cycles_init();
	bfin_cs_gptimer0_init();

#if defined(CONFIG_TICKSOURCE_CORETMR)
	bfin_coretmr_init();
	setup_irq(IRQ_CORETMR, &coretmr_irq);
	bfin_coretmr_clockevent_init();
#endif

#if defined(CONFIG_TICKSOURCE_GPTMR0)
	bfin_gptmr0_init();
	setup_irq(IRQ_TIMER0, &gptmr0_irq);
	gptmr0_irq.dev_id = &clockevent_gptmr0;
	bfin_gptmr0_clockevent_init(&clockevent_gptmr0);
#endif

#if !defined(CONFIG_TICKSOURCE_CORETMR) && !defined(CONFIG_TICKSOURCE_GPTMR0)
# error at least one clock event device is required
#endif
}
Commit	Line	Data
8b5f79f9	1	/*
8b5f79f9 VM	2	* Based on arm clockevents implementation and old bfin time tick.
8b5f79f9 VM	3	*
96f1050d RG	4	* Copyright 2008-2009 Analog Devics Inc.
	5	* 2008 GeoTechnologies
	6	* Vitja Makarov
8b5f79f9	7	*
96f1050d	8	* Licensed under the GPL-2
8b5f79f9	9	*/
96f1050d	10
8b5f79f9 VM	11	#include <linux/module.h>
	12	#include <linux/profile.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/time.h>
764cb81c	15	#include <linux/timex.h>
8b5f79f9 VM	16	#include <linux/irq.h>
	17	#include <linux/clocksource.h>
	18	#include <linux/clockchips.h>
e6c91b64	19	#include <linux/cpufreq.h>
8b5f79f9 VM	20
8b5f79f9 VM	21	#include <asm/blackfin.h>
e6c91b64	22	#include <asm/time.h>
1fa9be72	23	#include <asm/gptimers.h>
60ffdb36	24	#include <asm/nmi.h>
8b5f79f9	25
8b5f79f9	26
ceb33be9 YL	27	#if defined(CONFIG_CYCLES_CLOCKSOURCE)
ceb33be9 YL	28
ceb33be9	29	static notrace cycle_t bfin_read_cycles(struct clocksource *cs)
8b5f79f9	30	{
6c2b7072	31	#ifdef CONFIG_CPU_FREQ
1bfb4b21	32	return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod);
6c2b7072 GY	33	#else
	34	return get_cycles();
	35	#endif
8b5f79f9 VM	36	}
8b5f79f9 VM	37
1fa9be72 GY	38	static struct clocksource bfin_cs_cycles = {
1fa9be72 GY	39	.name = "bfin_cs_cycles",
e78feaae	40	.rating = 400,
1fa9be72	41	.read = bfin_read_cycles,
8b5f79f9	42	.mask = CLOCKSOURCE_MASK(64),
8b5f79f9 VM	43	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	44	};
	45
ceb33be9	46	static inline unsigned long long bfin_cs_cycles_sched_clock(void)
8e19608e	47	{
c768a943 MF	48	return clocksource_cyc2ns(bfin_read_cycles(&bfin_cs_cycles),
c768a943 MF	49	bfin_cs_cycles.mult, bfin_cs_cycles.shift);
8e19608e MD	50	}
8e19608e MD	51
1fa9be72	52	static int __init bfin_cs_cycles_init(void)
8b5f79f9	53	{
a1c57e0f	54	if (clocksource_register_hz(&bfin_cs_cycles, get_cclk()))
8b5f79f9 VM	55	panic("failed to register clocksource");
	56
	57	return 0;
	58	}
1fa9be72 GY	59	#else
	60	# define bfin_cs_cycles_init()
	61	#endif
	62
	63	#ifdef CONFIG_GPTMR0_CLOCKSOURCE
	64
	65	void __init setup_gptimer0(void)
	66	{
	67	disable_gptimers(TIMER0bit);
	68
2879bb30 SM	69	#ifdef CONFIG_BF60x
	70	bfin_write16(TIMER_DATA_IMSK, 0);
	71	set_gptimer_config(TIMER0_id, TIMER_OUT_DIS
	72	\| TIMER_MODE_PWM_CONT \| TIMER_PULSE_HI \| TIMER_IRQ_PER);
	73	#else
1fa9be72 GY	74	set_gptimer_config(TIMER0_id, \
1fa9be72 GY	75	TIMER_OUT_DIS \| TIMER_PERIOD_CNT \| TIMER_MODE_PWM);
2879bb30	76	#endif
1fa9be72 GY	77	set_gptimer_period(TIMER0_id, -1);
	78	set_gptimer_pwidth(TIMER0_id, -2);
	79	SSYNC();
	80	enable_gptimers(TIMER0bit);
	81	}
	82
f7036d64	83	static cycle_t bfin_read_gptimer0(struct clocksource *cs)
1fa9be72 GY	84	{
	85	return bfin_read_TIMER0_COUNTER();
	86	}
	87
	88	static struct clocksource bfin_cs_gptimer0 = {
	89	.name = "bfin_cs_gptimer0",
e78feaae	90	.rating = 350,
1fa9be72 GY	91	.read = bfin_read_gptimer0,
1fa9be72 GY	92	.mask = CLOCKSOURCE_MASK(32),
1fa9be72 GY	93	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	94	};
	95
ceb33be9 YL	96	static inline unsigned long long bfin_cs_gptimer0_sched_clock(void)
ceb33be9 YL	97	{
c768a943 MF	98	return clocksource_cyc2ns(bfin_read_TIMER0_COUNTER(),
c768a943 MF	99	bfin_cs_gptimer0.mult, bfin_cs_gptimer0.shift);
ceb33be9 YL	100	}
ceb33be9 YL	101
1fa9be72 GY	102	static int __init bfin_cs_gptimer0_init(void)
	103	{
	104	setup_gptimer0();
8b5f79f9	105
a1c57e0f	106	if (clocksource_register_hz(&bfin_cs_gptimer0, get_sclk()))
1fa9be72 GY	107	panic("failed to register clocksource");
	108
	109	return 0;
	110	}
8b5f79f9	111	#else
1fa9be72	112	# define bfin_cs_gptimer0_init()
8b5f79f9 VM	113	#endif
8b5f79f9 VM	114
ceb33be9 YL	115	#if defined(CONFIG_GPTMR0_CLOCKSOURCE) \|\| defined(CONFIG_CYCLES_CLOCKSOURCE)
	116	/* prefer to use cycles since it has higher rating */
	117	notrace unsigned long long sched_clock(void)
	118	{
	119	#if defined(CONFIG_CYCLES_CLOCKSOURCE)
	120	return bfin_cs_cycles_sched_clock();
	121	#else
	122	return bfin_cs_gptimer0_sched_clock();
	123	#endif
	124	}
	125	#endif
	126
1fa9be72	127	#if defined(CONFIG_TICKSOURCE_GPTMR0)
0d152c27	128	static int bfin_gptmr0_set_next_event(unsigned long cycles,
8b5f79f9 VM	129	struct clock_event_device *evt)
8b5f79f9 VM	130	{
1fa9be72 GY	131	disable_gptimers(TIMER0bit);
	132
	133	/* it starts counting three SCLK cycles after the TIMENx bit is set */
	134	set_gptimer_pwidth(TIMER0_id, cycles - 3);
	135	enable_gptimers(TIMER0bit);
	136	return 0;
	137	}
	138
067f9621	139	static int bfin_gptmr0_set_periodic(struct clock_event_device *evt)
1fa9be72	140	{
2879bb30	141	#ifndef CONFIG_BF60x
067f9621 VK	142	set_gptimer_config(TIMER0_id,
	143	TIMER_OUT_DIS \| TIMER_IRQ_ENA \|
	144	TIMER_PERIOD_CNT \| TIMER_MODE_PWM);
2879bb30	145	#else
067f9621 VK	146	set_gptimer_config(TIMER0_id,
	147	TIMER_OUT_DIS \| TIMER_MODE_PWM_CONT \|
	148	TIMER_PULSE_HI \| TIMER_IRQ_PER);
2879bb30 SM	149	#endif
2879bb30 SM	150
067f9621 VK	151	set_gptimer_period(TIMER0_id, get_sclk() / HZ);
	152	set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1);
	153	enable_gptimers(TIMER0bit);
	154	return 0;
	155	}
	156
	157	static int bfin_gptmr0_set_oneshot(struct clock_event_device *evt)
	158	{
	159	disable_gptimers(TIMER0bit);
2879bb30	160	#ifndef CONFIG_BF60x
067f9621 VK	161	set_gptimer_config(TIMER0_id,
067f9621 VK	162	TIMER_OUT_DIS \| TIMER_IRQ_ENA \| TIMER_MODE_PWM);
2879bb30	163	#else
067f9621 VK	164	set_gptimer_config(TIMER0_id,
	165	TIMER_OUT_DIS \| TIMER_MODE_PWM \| TIMER_PULSE_HI \|
	166	TIMER_IRQ_WID_DLY);
2879bb30 SM	167	#endif
2879bb30 SM	168
067f9621 VK	169	set_gptimer_period(TIMER0_id, 0);
	170	return 0;
	171	}
	172
	173	static int bfin_gptmr0_shutdown(struct clock_event_device *evt)
	174	{
	175	disable_gptimers(TIMER0bit);
	176	return 0;
1fa9be72 GY	177	}
1fa9be72 GY	178
0d152c27	179	static void bfin_gptmr0_ack(void)
1fa9be72	180	{
2879bb30	181	clear_gptimer_intr(TIMER0_id);
1fa9be72 GY	182	}
1fa9be72 GY	183
0d152c27	184	static void __init bfin_gptmr0_init(void)
1fa9be72 GY	185	{
	186	disable_gptimers(TIMER0bit);
	187	}
	188
0d152c27 YL	189	#ifdef CONFIG_CORE_TIMER_IRQ_L1
	190	__attribute__((l1_text))
	191	#endif
	192	irqreturn_t bfin_gptmr0_interrupt(int irq, void *dev_id)
1fa9be72	193	{
0d152c27 YL	194	struct clock_event_device *evt = dev_id;
0d152c27 YL	195	smp_mb();
0bf02ce6 MF	196	/*
	197	* We want to ACK before we handle so that we can handle smaller timer
	198	* intervals. This way if the timer expires again while we're handling
	199	* things, we're more likely to see that 2nd int rather than swallowing
	200	* it by ACKing the int at the end of this handler.
	201	*/
0d152c27	202	bfin_gptmr0_ack();
0bf02ce6	203	evt->event_handler(evt);
0d152c27	204	return IRQ_HANDLED;
1fa9be72 GY	205	}
1fa9be72 GY	206
0d152c27 YL	207	static struct irqaction gptmr0_irq = {
0d152c27 YL	208	.name = "Blackfin GPTimer0",
7832bb5d	209	.flags = IRQF_TIMER \| IRQF_IRQPOLL \| IRQF_PERCPU,
0d152c27 YL	210	.handler = bfin_gptmr0_interrupt,
0d152c27 YL	211	};
1fa9be72	212
0d152c27	213	static struct clock_event_device clockevent_gptmr0 = {
067f9621 VK	214	.name = "bfin_gptimer0",
	215	.rating = 300,
	216	.irq = IRQ_TIMER0,
	217	.shift = 32,
	218	.features = CLOCK_EVT_FEAT_PERIODIC \|
	219	CLOCK_EVT_FEAT_ONESHOT,
	220	.set_next_event = bfin_gptmr0_set_next_event,
	221	.set_state_shutdown = bfin_gptmr0_shutdown,
	222	.set_state_periodic = bfin_gptmr0_set_periodic,
	223	.set_state_oneshot = bfin_gptmr0_set_oneshot,
0d152c27 YL	224	};
	225
	226	static void __init bfin_gptmr0_clockevent_init(struct clock_event_device *evt)
	227	{
	228	unsigned long clock_tick;
	229
	230	clock_tick = get_sclk();
	231	evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift);
	232	evt->max_delta_ns = clockevent_delta2ns(-1, evt);
	233	evt->min_delta_ns = clockevent_delta2ns(100, evt);
	234
	235	evt->cpumask = cpumask_of(0);
	236
	237	clockevents_register_device(evt);
	238	}
	239	#endif /* CONFIG_TICKSOURCE_GPTMR0 */
	240
	241	#if defined(CONFIG_TICKSOURCE_CORETMR)
	242	/* per-cpu local core timer */
d0014be4	243	DEFINE_PER_CPU(struct clock_event_device, coretmr_events);
0d152c27 YL	244
0d152c27 YL	245	static int bfin_coretmr_set_next_event(unsigned long cycles,
1fa9be72 GY	246	struct clock_event_device *evt)
	247	{
	248	bfin_write_TCNTL(TMPWR);
	249	CSYNC();
8b5f79f9 VM	250	bfin_write_TCOUNT(cycles);
8b5f79f9 VM	251	CSYNC();
1fa9be72	252	bfin_write_TCNTL(TMPWR \| TMREN);
8b5f79f9 VM	253	return 0;
	254	}
	255
067f9621 VK	256	static int bfin_coretmr_set_periodic(struct clock_event_device *evt)
	257	{
	258	unsigned long tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1);
	259
	260	bfin_write_TCNTL(TMPWR);
	261	CSYNC();
	262	bfin_write_TSCALE(TIME_SCALE - 1);
	263	bfin_write_TPERIOD(tcount);
	264	bfin_write_TCOUNT(tcount);
	265	CSYNC();
	266	bfin_write_TCNTL(TMPWR \| TMREN \| TAUTORLD);
	267	return 0;
	268	}
	269
	270	static int bfin_coretmr_set_oneshot(struct clock_event_device *evt)
8b5f79f9	271	{
067f9621 VK	272	bfin_write_TCNTL(TMPWR);
	273	CSYNC();
	274	bfin_write_TSCALE(TIME_SCALE - 1);
	275	bfin_write_TPERIOD(0);
	276	bfin_write_TCOUNT(0);
	277	return 0;
	278	}
	279
	280	static int bfin_coretmr_shutdown(struct clock_event_device *evt)
	281	{
	282	bfin_write_TCNTL(0);
	283	CSYNC();
	284	return 0;
8b5f79f9 VM	285	}
8b5f79f9 VM	286
0d152c27	287	void bfin_coretmr_init(void)
8b5f79f9 VM	288	{
	289	/* power up the timer, but don't enable it just yet */
	290	bfin_write_TCNTL(TMPWR);
	291	CSYNC();
	292
0d152c27	293	/* the TSCALE prescaler counter. */
e6c91b64	294	bfin_write_TSCALE(TIME_SCALE - 1);
8b5f79f9 VM	295	bfin_write_TPERIOD(0);
	296	bfin_write_TCOUNT(0);
	297
8b5f79f9 VM	298	CSYNC();
	299	}
	300
0d152c27 YL	301	#ifdef CONFIG_CORE_TIMER_IRQ_L1
	302	__attribute__((l1_text))
	303	#endif
d0014be4	304
0d152c27	305	irqreturn_t bfin_coretmr_interrupt(int irq, void *dev_id)
1fa9be72	306	{
0d152c27 YL	307	int cpu = smp_processor_id();
0d152c27 YL	308	struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
1fa9be72	309
1fa9be72	310	smp_mb();
8b5f79f9	311	evt->event_handler(evt);
60ffdb36 GY	312
	313	touch_nmi_watchdog();
	314
8b5f79f9 VM	315	return IRQ_HANDLED;
	316	}
	317
0d152c27 YL	318	static struct irqaction coretmr_irq = {
0d152c27 YL	319	.name = "Blackfin CoreTimer",
7832bb5d	320	.flags = IRQF_TIMER \| IRQF_IRQPOLL \| IRQF_PERCPU,
0d152c27 YL	321	.handler = bfin_coretmr_interrupt,
0d152c27 YL	322	};
8b5f79f9	323
0d152c27 YL	324	void bfin_coretmr_clockevent_init(void)
	325	{
	326	unsigned long clock_tick;
	327	unsigned int cpu = smp_processor_id();
	328	struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
	329
2879bb30 SM	330	#ifdef CONFIG_SMP
	331	evt->broadcast = smp_timer_broadcast;
	332	#endif
	333
0d152c27 YL	334	evt->name = "bfin_core_timer";
	335	evt->rating = 350;
	336	evt->irq = -1;
	337	evt->shift = 32;
	338	evt->features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT;
	339	evt->set_next_event = bfin_coretmr_set_next_event;
067f9621 VK	340	evt->set_state_shutdown = bfin_coretmr_shutdown;
	341	evt->set_state_periodic = bfin_coretmr_set_periodic;
	342	evt->set_state_oneshot = bfin_coretmr_set_oneshot;
0d152c27 YL	343
	344	clock_tick = get_cclk() / TIME_SCALE;
	345	evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift);
	346	evt->max_delta_ns = clockevent_delta2ns(-1, evt);
	347	evt->min_delta_ns = clockevent_delta2ns(100, evt);
	348
	349	evt->cpumask = cpumask_of(cpu);
	350
	351	clockevents_register_device(evt);
8b5f79f9	352	}
0d152c27 YL	353	#endif /* CONFIG_TICKSOURCE_CORETMR */
0d152c27 YL	354
8b5f79f9	355
cb0e9963	356	void read_persistent_clock(struct timespec *ts)
8b5f79f9 VM	357	{
8b5f79f9 VM	358	time_t secs_since_1970 = (365 * 37 + 9) * 24 * 60 * 60; /* 1 Jan 2007 */
cb0e9963 JS	359	ts->tv_sec = secs_since_1970;
	360	ts->tv_nsec = 0;
	361	}
	362
	363	void __init time_init(void)
	364	{
8b5f79f9 VM	365
	366	#ifdef CONFIG_RTC_DRV_BFIN
	367	/* [#2663] hack to filter junk RTC values that would cause
	368	* userspace to have to deal with time values greater than
	369	* 2^31 seconds (which uClibc cannot cope with yet)
	370	*/
	371	if ((bfin_read_RTC_STAT() & 0xC0000000) == 0xC0000000) {
	372	printk(KERN_NOTICE "bfin-rtc: invalid date; resetting\n");
	373	bfin_write_RTC_STAT(0);
	374	}
	375	#endif
	376
1fa9be72 GY	377	bfin_cs_cycles_init();
1fa9be72 GY	378	bfin_cs_gptimer0_init();
0d152c27 YL	379
	380	#if defined(CONFIG_TICKSOURCE_CORETMR)
	381	bfin_coretmr_init();
	382	setup_irq(IRQ_CORETMR, &coretmr_irq);
	383	bfin_coretmr_clockevent_init();
	384	#endif
	385
	386	#if defined(CONFIG_TICKSOURCE_GPTMR0)
	387	bfin_gptmr0_init();
	388	setup_irq(IRQ_TIMER0, &gptmr0_irq);
	389	gptmr0_irq.dev_id = &clockevent_gptmr0;
	390	bfin_gptmr0_clockevent_init(&clockevent_gptmr0);
	391	#endif
	392
	393	#if !defined(CONFIG_TICKSOURCE_CORETMR) && !defined(CONFIG_TICKSOURCE_GPTMR0)
	394	# error at least one clock event device is required
	395	#endif
8b5f79f9	396	}