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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
b3901d54 CM |
2 | /* |
3 | * Based on arch/arm/kernel/process.c | |
4 | * | |
5 | * Original Copyright (C) 1995 Linus Torvalds | |
6 | * Copyright (C) 1996-2000 Russell King - Converted to ARM. | |
7 | * Copyright (C) 2012 ARM Ltd. | |
b3901d54 CM |
8 | */ |
9 | ||
10 | #include <stdarg.h> | |
11 | ||
fd92d4a5 | 12 | #include <linux/compat.h> |
60c0d45a | 13 | #include <linux/efi.h> |
ab7876a9 | 14 | #include <linux/elf.h> |
b3901d54 CM |
15 | #include <linux/export.h> |
16 | #include <linux/sched.h> | |
b17b0153 | 17 | #include <linux/sched/debug.h> |
29930025 | 18 | #include <linux/sched/task.h> |
68db0cf1 | 19 | #include <linux/sched/task_stack.h> |
b3901d54 | 20 | #include <linux/kernel.h> |
19c95f26 | 21 | #include <linux/lockdep.h> |
ab7876a9 | 22 | #include <linux/mman.h> |
b3901d54 | 23 | #include <linux/mm.h> |
780c083a | 24 | #include <linux/nospec.h> |
b3901d54 | 25 | #include <linux/stddef.h> |
63f0c603 | 26 | #include <linux/sysctl.h> |
b3901d54 CM |
27 | #include <linux/unistd.h> |
28 | #include <linux/user.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/reboot.h> | |
31 | #include <linux/interrupt.h> | |
b3901d54 CM |
32 | #include <linux/init.h> |
33 | #include <linux/cpu.h> | |
34 | #include <linux/elfcore.h> | |
35 | #include <linux/pm.h> | |
36 | #include <linux/tick.h> | |
37 | #include <linux/utsname.h> | |
38 | #include <linux/uaccess.h> | |
39 | #include <linux/random.h> | |
40 | #include <linux/hw_breakpoint.h> | |
41 | #include <linux/personality.h> | |
42 | #include <linux/notifier.h> | |
096b3224 | 43 | #include <trace/events/power.h> |
c02433dd | 44 | #include <linux/percpu.h> |
bc0ee476 | 45 | #include <linux/thread_info.h> |
63f0c603 | 46 | #include <linux/prctl.h> |
b3901d54 | 47 | |
57f4959b | 48 | #include <asm/alternative.h> |
a9806aa2 | 49 | #include <asm/arch_gicv3.h> |
b3901d54 | 50 | #include <asm/compat.h> |
19c95f26 | 51 | #include <asm/cpufeature.h> |
b3901d54 | 52 | #include <asm/cacheflush.h> |
d0854412 | 53 | #include <asm/exec.h> |
ec45d1cf WD |
54 | #include <asm/fpsimd.h> |
55 | #include <asm/mmu_context.h> | |
637ec831 | 56 | #include <asm/mte.h> |
b3901d54 | 57 | #include <asm/processor.h> |
75031975 | 58 | #include <asm/pointer_auth.h> |
b3901d54 | 59 | #include <asm/stacktrace.h> |
b3901d54 | 60 | |
0a1213fa | 61 | #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_STACKPROTECTOR_PER_TASK) |
c0c264ae LA |
62 | #include <linux/stackprotector.h> |
63 | unsigned long __stack_chk_guard __read_mostly; | |
64 | EXPORT_SYMBOL(__stack_chk_guard); | |
65 | #endif | |
66 | ||
b3901d54 CM |
67 | /* |
68 | * Function pointers to optional machine specific functions | |
69 | */ | |
70 | void (*pm_power_off)(void); | |
71 | EXPORT_SYMBOL_GPL(pm_power_off); | |
72 | ||
b0946fc8 | 73 | void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd); |
b3901d54 | 74 | |
114e0a68 | 75 | static void noinstr __cpu_do_idle(void) |
a9806aa2 JT |
76 | { |
77 | dsb(sy); | |
78 | wfi(); | |
79 | } | |
80 | ||
114e0a68 | 81 | static void noinstr __cpu_do_idle_irqprio(void) |
a9806aa2 JT |
82 | { |
83 | unsigned long pmr; | |
84 | unsigned long daif_bits; | |
85 | ||
86 | daif_bits = read_sysreg(daif); | |
87 | write_sysreg(daif_bits | PSR_I_BIT, daif); | |
88 | ||
89 | /* | |
90 | * Unmask PMR before going idle to make sure interrupts can | |
91 | * be raised. | |
92 | */ | |
93 | pmr = gic_read_pmr(); | |
bd82d4bd | 94 | gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET); |
a9806aa2 JT |
95 | |
96 | __cpu_do_idle(); | |
97 | ||
98 | gic_write_pmr(pmr); | |
99 | write_sysreg(daif_bits, daif); | |
100 | } | |
101 | ||
102 | /* | |
103 | * cpu_do_idle() | |
104 | * | |
105 | * Idle the processor (wait for interrupt). | |
106 | * | |
107 | * If the CPU supports priority masking we must do additional work to | |
108 | * ensure that interrupts are not masked at the PMR (because the core will | |
109 | * not wake up if we block the wake up signal in the interrupt controller). | |
110 | */ | |
114e0a68 | 111 | void noinstr cpu_do_idle(void) |
a9806aa2 JT |
112 | { |
113 | if (system_uses_irq_prio_masking()) | |
114 | __cpu_do_idle_irqprio(); | |
115 | else | |
116 | __cpu_do_idle(); | |
117 | } | |
118 | ||
b3901d54 CM |
119 | /* |
120 | * This is our default idle handler. | |
121 | */ | |
114e0a68 | 122 | void noinstr arch_cpu_idle(void) |
b3901d54 CM |
123 | { |
124 | /* | |
125 | * This should do all the clock switching and wait for interrupt | |
126 | * tricks | |
127 | */ | |
6990566b | 128 | cpu_do_idle(); |
58c644ba | 129 | raw_local_irq_enable(); |
b3901d54 CM |
130 | } |
131 | ||
9327e2c6 MR |
132 | #ifdef CONFIG_HOTPLUG_CPU |
133 | void arch_cpu_idle_dead(void) | |
134 | { | |
135 | cpu_die(); | |
136 | } | |
137 | #endif | |
138 | ||
90f51a09 AK |
139 | /* |
140 | * Called by kexec, immediately prior to machine_kexec(). | |
141 | * | |
142 | * This must completely disable all secondary CPUs; simply causing those CPUs | |
143 | * to execute e.g. a RAM-based pin loop is not sufficient. This allows the | |
144 | * kexec'd kernel to use any and all RAM as it sees fit, without having to | |
145 | * avoid any code or data used by any SW CPU pin loop. The CPU hotplug | |
d66b16f5 | 146 | * functionality embodied in smpt_shutdown_nonboot_cpus() to achieve this. |
90f51a09 | 147 | */ |
b3901d54 CM |
148 | void machine_shutdown(void) |
149 | { | |
5efbe6a6 | 150 | smp_shutdown_nonboot_cpus(reboot_cpu); |
b3901d54 CM |
151 | } |
152 | ||
90f51a09 AK |
153 | /* |
154 | * Halting simply requires that the secondary CPUs stop performing any | |
155 | * activity (executing tasks, handling interrupts). smp_send_stop() | |
156 | * achieves this. | |
157 | */ | |
b3901d54 CM |
158 | void machine_halt(void) |
159 | { | |
b9acc49e | 160 | local_irq_disable(); |
90f51a09 | 161 | smp_send_stop(); |
b3901d54 CM |
162 | while (1); |
163 | } | |
164 | ||
90f51a09 AK |
165 | /* |
166 | * Power-off simply requires that the secondary CPUs stop performing any | |
167 | * activity (executing tasks, handling interrupts). smp_send_stop() | |
168 | * achieves this. When the system power is turned off, it will take all CPUs | |
169 | * with it. | |
170 | */ | |
b3901d54 CM |
171 | void machine_power_off(void) |
172 | { | |
b9acc49e | 173 | local_irq_disable(); |
90f51a09 | 174 | smp_send_stop(); |
b3901d54 CM |
175 | if (pm_power_off) |
176 | pm_power_off(); | |
177 | } | |
178 | ||
90f51a09 AK |
179 | /* |
180 | * Restart requires that the secondary CPUs stop performing any activity | |
68234df4 | 181 | * while the primary CPU resets the system. Systems with multiple CPUs must |
90f51a09 AK |
182 | * provide a HW restart implementation, to ensure that all CPUs reset at once. |
183 | * This is required so that any code running after reset on the primary CPU | |
184 | * doesn't have to co-ordinate with other CPUs to ensure they aren't still | |
185 | * executing pre-reset code, and using RAM that the primary CPU's code wishes | |
186 | * to use. Implementing such co-ordination would be essentially impossible. | |
187 | */ | |
b3901d54 CM |
188 | void machine_restart(char *cmd) |
189 | { | |
b3901d54 CM |
190 | /* Disable interrupts first */ |
191 | local_irq_disable(); | |
b9acc49e | 192 | smp_send_stop(); |
b3901d54 | 193 | |
60c0d45a AB |
194 | /* |
195 | * UpdateCapsule() depends on the system being reset via | |
196 | * ResetSystem(). | |
197 | */ | |
198 | if (efi_enabled(EFI_RUNTIME_SERVICES)) | |
199 | efi_reboot(reboot_mode, NULL); | |
200 | ||
b3901d54 | 201 | /* Now call the architecture specific reboot code. */ |
aa1e8ec1 | 202 | if (arm_pm_restart) |
ff701306 | 203 | arm_pm_restart(reboot_mode, cmd); |
1c7ffc32 GR |
204 | else |
205 | do_kernel_restart(cmd); | |
b3901d54 CM |
206 | |
207 | /* | |
208 | * Whoops - the architecture was unable to reboot. | |
209 | */ | |
210 | printk("Reboot failed -- System halted\n"); | |
211 | while (1); | |
212 | } | |
213 | ||
ec94a46e DM |
214 | #define bstr(suffix, str) [PSR_BTYPE_ ## suffix >> PSR_BTYPE_SHIFT] = str |
215 | static const char *const btypes[] = { | |
216 | bstr(NONE, "--"), | |
217 | bstr( JC, "jc"), | |
218 | bstr( C, "-c"), | |
219 | bstr( J , "j-") | |
220 | }; | |
221 | #undef bstr | |
222 | ||
b7300d4c WD |
223 | static void print_pstate(struct pt_regs *regs) |
224 | { | |
225 | u64 pstate = regs->pstate; | |
226 | ||
227 | if (compat_user_mode(regs)) { | |
228 | printk("pstate: %08llx (%c%c%c%c %c %s %s %c%c%c)\n", | |
229 | pstate, | |
d64567f6 MR |
230 | pstate & PSR_AA32_N_BIT ? 'N' : 'n', |
231 | pstate & PSR_AA32_Z_BIT ? 'Z' : 'z', | |
232 | pstate & PSR_AA32_C_BIT ? 'C' : 'c', | |
233 | pstate & PSR_AA32_V_BIT ? 'V' : 'v', | |
234 | pstate & PSR_AA32_Q_BIT ? 'Q' : 'q', | |
235 | pstate & PSR_AA32_T_BIT ? "T32" : "A32", | |
236 | pstate & PSR_AA32_E_BIT ? "BE" : "LE", | |
237 | pstate & PSR_AA32_A_BIT ? 'A' : 'a', | |
238 | pstate & PSR_AA32_I_BIT ? 'I' : 'i', | |
239 | pstate & PSR_AA32_F_BIT ? 'F' : 'f'); | |
b7300d4c | 240 | } else { |
ec94a46e DM |
241 | const char *btype_str = btypes[(pstate & PSR_BTYPE_MASK) >> |
242 | PSR_BTYPE_SHIFT]; | |
243 | ||
637ec831 | 244 | printk("pstate: %08llx (%c%c%c%c %c%c%c%c %cPAN %cUAO %cTCO BTYPE=%s)\n", |
b7300d4c WD |
245 | pstate, |
246 | pstate & PSR_N_BIT ? 'N' : 'n', | |
247 | pstate & PSR_Z_BIT ? 'Z' : 'z', | |
248 | pstate & PSR_C_BIT ? 'C' : 'c', | |
249 | pstate & PSR_V_BIT ? 'V' : 'v', | |
250 | pstate & PSR_D_BIT ? 'D' : 'd', | |
251 | pstate & PSR_A_BIT ? 'A' : 'a', | |
252 | pstate & PSR_I_BIT ? 'I' : 'i', | |
253 | pstate & PSR_F_BIT ? 'F' : 'f', | |
254 | pstate & PSR_PAN_BIT ? '+' : '-', | |
ec94a46e | 255 | pstate & PSR_UAO_BIT ? '+' : '-', |
637ec831 | 256 | pstate & PSR_TCO_BIT ? '+' : '-', |
ec94a46e | 257 | btype_str); |
b7300d4c WD |
258 | } |
259 | } | |
260 | ||
b3901d54 CM |
261 | void __show_regs(struct pt_regs *regs) |
262 | { | |
6ca68e80 CM |
263 | int i, top_reg; |
264 | u64 lr, sp; | |
265 | ||
266 | if (compat_user_mode(regs)) { | |
267 | lr = regs->compat_lr; | |
268 | sp = regs->compat_sp; | |
269 | top_reg = 12; | |
270 | } else { | |
271 | lr = regs->regs[30]; | |
272 | sp = regs->sp; | |
273 | top_reg = 29; | |
274 | } | |
b3901d54 | 275 | |
a43cb95d | 276 | show_regs_print_info(KERN_DEFAULT); |
b7300d4c | 277 | print_pstate(regs); |
a06f818a WD |
278 | |
279 | if (!user_mode(regs)) { | |
280 | printk("pc : %pS\n", (void *)regs->pc); | |
cdcb61ae | 281 | printk("lr : %pS\n", (void *)ptrauth_strip_insn_pac(lr)); |
a06f818a WD |
282 | } else { |
283 | printk("pc : %016llx\n", regs->pc); | |
284 | printk("lr : %016llx\n", lr); | |
285 | } | |
286 | ||
b7300d4c | 287 | printk("sp : %016llx\n", sp); |
db4b0710 | 288 | |
133d0518 JT |
289 | if (system_uses_irq_prio_masking()) |
290 | printk("pmr_save: %08llx\n", regs->pmr_save); | |
291 | ||
db4b0710 MR |
292 | i = top_reg; |
293 | ||
294 | while (i >= 0) { | |
b3901d54 | 295 | printk("x%-2d: %016llx ", i, regs->regs[i]); |
db4b0710 MR |
296 | i--; |
297 | ||
298 | if (i % 2 == 0) { | |
299 | pr_cont("x%-2d: %016llx ", i, regs->regs[i]); | |
300 | i--; | |
301 | } | |
302 | ||
303 | pr_cont("\n"); | |
b3901d54 | 304 | } |
b3901d54 CM |
305 | } |
306 | ||
307 | void show_regs(struct pt_regs * regs) | |
308 | { | |
b3901d54 | 309 | __show_regs(regs); |
c7689837 | 310 | dump_backtrace(regs, NULL, KERN_DEFAULT); |
b3901d54 CM |
311 | } |
312 | ||
eb35bdd7 WD |
313 | static void tls_thread_flush(void) |
314 | { | |
adf75899 | 315 | write_sysreg(0, tpidr_el0); |
eb35bdd7 WD |
316 | |
317 | if (is_compat_task()) { | |
65896545 | 318 | current->thread.uw.tp_value = 0; |
eb35bdd7 WD |
319 | |
320 | /* | |
321 | * We need to ensure ordering between the shadow state and the | |
322 | * hardware state, so that we don't corrupt the hardware state | |
323 | * with a stale shadow state during context switch. | |
324 | */ | |
325 | barrier(); | |
adf75899 | 326 | write_sysreg(0, tpidrro_el0); |
eb35bdd7 WD |
327 | } |
328 | } | |
329 | ||
63f0c603 CM |
330 | static void flush_tagged_addr_state(void) |
331 | { | |
332 | if (IS_ENABLED(CONFIG_ARM64_TAGGED_ADDR_ABI)) | |
333 | clear_thread_flag(TIF_TAGGED_ADDR); | |
334 | } | |
335 | ||
b3901d54 CM |
336 | void flush_thread(void) |
337 | { | |
338 | fpsimd_flush_thread(); | |
eb35bdd7 | 339 | tls_thread_flush(); |
b3901d54 | 340 | flush_ptrace_hw_breakpoint(current); |
63f0c603 | 341 | flush_tagged_addr_state(); |
637ec831 | 342 | flush_mte_state(); |
b3901d54 CM |
343 | } |
344 | ||
345 | void release_thread(struct task_struct *dead_task) | |
346 | { | |
347 | } | |
348 | ||
bc0ee476 DM |
349 | void arch_release_task_struct(struct task_struct *tsk) |
350 | { | |
351 | fpsimd_release_task(tsk); | |
352 | } | |
353 | ||
b3901d54 CM |
354 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
355 | { | |
6eb6c801 JL |
356 | if (current->mm) |
357 | fpsimd_preserve_current_state(); | |
b3901d54 | 358 | *dst = *src; |
bc0ee476 | 359 | |
4585fc59 MM |
360 | /* We rely on the above assignment to initialize dst's thread_flags: */ |
361 | BUILD_BUG_ON(!IS_ENABLED(CONFIG_THREAD_INFO_IN_TASK)); | |
362 | ||
363 | /* | |
364 | * Detach src's sve_state (if any) from dst so that it does not | |
365 | * get erroneously used or freed prematurely. dst's sve_state | |
366 | * will be allocated on demand later on if dst uses SVE. | |
367 | * For consistency, also clear TIF_SVE here: this could be done | |
368 | * later in copy_process(), but to avoid tripping up future | |
369 | * maintainers it is best not to leave TIF_SVE and sve_state in | |
370 | * an inconsistent state, even temporarily. | |
371 | */ | |
372 | dst->thread.sve_state = NULL; | |
373 | clear_tsk_thread_flag(dst, TIF_SVE); | |
374 | ||
637ec831 VF |
375 | /* clear any pending asynchronous tag fault raised by the parent */ |
376 | clear_tsk_thread_flag(dst, TIF_MTE_ASYNC_FAULT); | |
377 | ||
b3901d54 CM |
378 | return 0; |
379 | } | |
380 | ||
381 | asmlinkage void ret_from_fork(void) asm("ret_from_fork"); | |
382 | ||
714acdbd | 383 | int copy_thread(unsigned long clone_flags, unsigned long stack_start, |
a4376f2f | 384 | unsigned long stk_sz, struct task_struct *p, unsigned long tls) |
b3901d54 CM |
385 | { |
386 | struct pt_regs *childregs = task_pt_regs(p); | |
b3901d54 | 387 | |
c34501d2 | 388 | memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context)); |
b3901d54 | 389 | |
071b6d4a DM |
390 | /* |
391 | * In case p was allocated the same task_struct pointer as some | |
392 | * other recently-exited task, make sure p is disassociated from | |
393 | * any cpu that may have run that now-exited task recently. | |
394 | * Otherwise we could erroneously skip reloading the FPSIMD | |
395 | * registers for p. | |
396 | */ | |
397 | fpsimd_flush_task_state(p); | |
398 | ||
33e45234 KM |
399 | ptrauth_thread_init_kernel(p); |
400 | ||
9ac08002 AV |
401 | if (likely(!(p->flags & PF_KTHREAD))) { |
402 | *childregs = *current_pt_regs(); | |
c34501d2 | 403 | childregs->regs[0] = 0; |
d00a3810 WD |
404 | |
405 | /* | |
406 | * Read the current TLS pointer from tpidr_el0 as it may be | |
407 | * out-of-sync with the saved value. | |
408 | */ | |
adf75899 | 409 | *task_user_tls(p) = read_sysreg(tpidr_el0); |
d00a3810 WD |
410 | |
411 | if (stack_start) { | |
412 | if (is_compat_thread(task_thread_info(p))) | |
e0fd18ce | 413 | childregs->compat_sp = stack_start; |
d00a3810 | 414 | else |
e0fd18ce | 415 | childregs->sp = stack_start; |
c34501d2 | 416 | } |
d00a3810 | 417 | |
b3901d54 | 418 | /* |
a4376f2f AA |
419 | * If a TLS pointer was passed to clone, use it for the new |
420 | * thread. | |
b3901d54 | 421 | */ |
c34501d2 | 422 | if (clone_flags & CLONE_SETTLS) |
a4376f2f | 423 | p->thread.uw.tp_value = tls; |
c34501d2 | 424 | } else { |
f80d0340 MR |
425 | /* |
426 | * A kthread has no context to ERET to, so ensure any buggy | |
427 | * ERET is treated as an illegal exception return. | |
428 | * | |
429 | * When a user task is created from a kthread, childregs will | |
430 | * be initialized by start_thread() or start_compat_thread(). | |
431 | */ | |
c34501d2 | 432 | memset(childregs, 0, sizeof(struct pt_regs)); |
f80d0340 | 433 | childregs->pstate = PSR_MODE_EL1h | PSR_IL_BIT; |
133d0518 | 434 | |
c34501d2 CM |
435 | p->thread.cpu_context.x19 = stack_start; |
436 | p->thread.cpu_context.x20 = stk_sz; | |
b3901d54 | 437 | } |
b3901d54 | 438 | p->thread.cpu_context.pc = (unsigned long)ret_from_fork; |
c34501d2 | 439 | p->thread.cpu_context.sp = (unsigned long)childregs; |
b3901d54 CM |
440 | |
441 | ptrace_hw_copy_thread(p); | |
442 | ||
443 | return 0; | |
444 | } | |
445 | ||
936eb65c DM |
446 | void tls_preserve_current_state(void) |
447 | { | |
448 | *task_user_tls(current) = read_sysreg(tpidr_el0); | |
449 | } | |
450 | ||
b3901d54 CM |
451 | static void tls_thread_switch(struct task_struct *next) |
452 | { | |
936eb65c | 453 | tls_preserve_current_state(); |
b3901d54 | 454 | |
18011eac | 455 | if (is_compat_thread(task_thread_info(next))) |
65896545 | 456 | write_sysreg(next->thread.uw.tp_value, tpidrro_el0); |
18011eac WD |
457 | else if (!arm64_kernel_unmapped_at_el0()) |
458 | write_sysreg(0, tpidrro_el0); | |
b3901d54 | 459 | |
18011eac | 460 | write_sysreg(*task_user_tls(next), tpidr_el0); |
b3901d54 CM |
461 | } |
462 | ||
cbdf8a18 MZ |
463 | /* |
464 | * Force SSBS state on context-switch, since it may be lost after migrating | |
465 | * from a CPU which treats the bit as RES0 in a heterogeneous system. | |
466 | */ | |
467 | static void ssbs_thread_switch(struct task_struct *next) | |
468 | { | |
cbdf8a18 MZ |
469 | /* |
470 | * Nothing to do for kernel threads, but 'regs' may be junk | |
471 | * (e.g. idle task) so check the flags and bail early. | |
472 | */ | |
473 | if (unlikely(next->flags & PF_KTHREAD)) | |
474 | return; | |
475 | ||
fca3d33d WD |
476 | /* |
477 | * If all CPUs implement the SSBS extension, then we just need to | |
478 | * context-switch the PSTATE field. | |
479 | */ | |
c2876207 | 480 | if (cpus_have_const_cap(ARM64_SSBS)) |
cbdf8a18 MZ |
481 | return; |
482 | ||
c2876207 | 483 | spectre_v4_enable_task_mitigation(next); |
cbdf8a18 MZ |
484 | } |
485 | ||
c02433dd MR |
486 | /* |
487 | * We store our current task in sp_el0, which is clobbered by userspace. Keep a | |
488 | * shadow copy so that we can restore this upon entry from userspace. | |
489 | * | |
490 | * This is *only* for exception entry from EL0, and is not valid until we | |
491 | * __switch_to() a user task. | |
492 | */ | |
493 | DEFINE_PER_CPU(struct task_struct *, __entry_task); | |
494 | ||
495 | static void entry_task_switch(struct task_struct *next) | |
496 | { | |
497 | __this_cpu_write(__entry_task, next); | |
498 | } | |
499 | ||
d49f7d73 MZ |
500 | /* |
501 | * ARM erratum 1418040 handling, affecting the 32bit view of CNTVCT. | |
502 | * Assuming the virtual counter is enabled at the beginning of times: | |
503 | * | |
504 | * - disable access when switching from a 64bit task to a 32bit task | |
505 | * - enable access when switching from a 32bit task to a 64bit task | |
506 | */ | |
507 | static void erratum_1418040_thread_switch(struct task_struct *prev, | |
508 | struct task_struct *next) | |
509 | { | |
510 | bool prev32, next32; | |
511 | u64 val; | |
512 | ||
f969f038 | 513 | if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_1418040)) |
d49f7d73 MZ |
514 | return; |
515 | ||
516 | prev32 = is_compat_thread(task_thread_info(prev)); | |
517 | next32 = is_compat_thread(task_thread_info(next)); | |
518 | ||
f969f038 | 519 | if (prev32 == next32 || !this_cpu_has_cap(ARM64_WORKAROUND_1418040)) |
d49f7d73 MZ |
520 | return; |
521 | ||
522 | val = read_sysreg(cntkctl_el1); | |
523 | ||
524 | if (!next32) | |
525 | val |= ARCH_TIMER_USR_VCT_ACCESS_EN; | |
526 | else | |
527 | val &= ~ARCH_TIMER_USR_VCT_ACCESS_EN; | |
528 | ||
529 | write_sysreg(val, cntkctl_el1); | |
530 | } | |
531 | ||
b3901d54 CM |
532 | /* |
533 | * Thread switching. | |
534 | */ | |
8f4b326d | 535 | __notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev, |
b3901d54 CM |
536 | struct task_struct *next) |
537 | { | |
538 | struct task_struct *last; | |
539 | ||
540 | fpsimd_thread_switch(next); | |
541 | tls_thread_switch(next); | |
542 | hw_breakpoint_thread_switch(next); | |
3325732f | 543 | contextidr_thread_switch(next); |
c02433dd | 544 | entry_task_switch(next); |
cbdf8a18 | 545 | ssbs_thread_switch(next); |
d49f7d73 | 546 | erratum_1418040_thread_switch(prev, next); |
b3901d54 | 547 | |
5108c67c CM |
548 | /* |
549 | * Complete any pending TLB or cache maintenance on this CPU in case | |
550 | * the thread migrates to a different CPU. | |
22e4ebb9 MD |
551 | * This full barrier is also required by the membarrier system |
552 | * call. | |
5108c67c | 553 | */ |
98f7685e | 554 | dsb(ish); |
b3901d54 | 555 | |
1c101da8 CM |
556 | /* |
557 | * MTE thread switching must happen after the DSB above to ensure that | |
558 | * any asynchronous tag check faults have been logged in the TFSR*_EL1 | |
559 | * registers. | |
560 | */ | |
561 | mte_thread_switch(next); | |
562 | ||
b3901d54 CM |
563 | /* the actual thread switch */ |
564 | last = cpu_switch_to(prev, next); | |
565 | ||
566 | return last; | |
567 | } | |
568 | ||
b3901d54 CM |
569 | unsigned long get_wchan(struct task_struct *p) |
570 | { | |
571 | struct stackframe frame; | |
9bbd4c56 | 572 | unsigned long stack_page, ret = 0; |
b3901d54 CM |
573 | int count = 0; |
574 | if (!p || p == current || p->state == TASK_RUNNING) | |
575 | return 0; | |
576 | ||
9bbd4c56 MR |
577 | stack_page = (unsigned long)try_get_task_stack(p); |
578 | if (!stack_page) | |
579 | return 0; | |
580 | ||
f3dcbe67 DM |
581 | start_backtrace(&frame, thread_saved_fp(p), thread_saved_pc(p)); |
582 | ||
b3901d54 | 583 | do { |
31e43ad3 | 584 | if (unwind_frame(p, &frame)) |
9bbd4c56 MR |
585 | goto out; |
586 | if (!in_sched_functions(frame.pc)) { | |
587 | ret = frame.pc; | |
588 | goto out; | |
589 | } | |
b3901d54 | 590 | } while (count ++ < 16); |
9bbd4c56 MR |
591 | |
592 | out: | |
593 | put_task_stack(p); | |
594 | return ret; | |
b3901d54 CM |
595 | } |
596 | ||
597 | unsigned long arch_align_stack(unsigned long sp) | |
598 | { | |
599 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
600 | sp -= get_random_int() & ~PAGE_MASK; | |
601 | return sp & ~0xf; | |
602 | } | |
603 | ||
d1be5c99 YN |
604 | /* |
605 | * Called from setup_new_exec() after (COMPAT_)SET_PERSONALITY. | |
606 | */ | |
607 | void arch_setup_new_exec(void) | |
608 | { | |
609 | current->mm->context.flags = is_compat_task() ? MMCF_AARCH32 : 0; | |
75031975 MR |
610 | |
611 | ptrauth_thread_init_user(current); | |
780c083a WD |
612 | |
613 | if (task_spec_ssb_noexec(current)) { | |
614 | arch_prctl_spec_ctrl_set(current, PR_SPEC_STORE_BYPASS, | |
615 | PR_SPEC_ENABLE); | |
616 | } | |
d1be5c99 | 617 | } |
63f0c603 CM |
618 | |
619 | #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI | |
620 | /* | |
621 | * Control the relaxed ABI allowing tagged user addresses into the kernel. | |
622 | */ | |
413235fc | 623 | static unsigned int tagged_addr_disabled; |
63f0c603 | 624 | |
93f067f6 | 625 | long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg) |
63f0c603 | 626 | { |
1c101da8 | 627 | unsigned long valid_mask = PR_TAGGED_ADDR_ENABLE; |
93f067f6 | 628 | struct thread_info *ti = task_thread_info(task); |
1c101da8 | 629 | |
93f067f6 | 630 | if (is_compat_thread(ti)) |
63f0c603 | 631 | return -EINVAL; |
1c101da8 CM |
632 | |
633 | if (system_supports_mte()) | |
af5ce952 | 634 | valid_mask |= PR_MTE_TCF_MASK | PR_MTE_TAG_MASK; |
1c101da8 CM |
635 | |
636 | if (arg & ~valid_mask) | |
63f0c603 CM |
637 | return -EINVAL; |
638 | ||
413235fc CM |
639 | /* |
640 | * Do not allow the enabling of the tagged address ABI if globally | |
641 | * disabled via sysctl abi.tagged_addr_disabled. | |
642 | */ | |
643 | if (arg & PR_TAGGED_ADDR_ENABLE && tagged_addr_disabled) | |
644 | return -EINVAL; | |
645 | ||
93f067f6 | 646 | if (set_mte_ctrl(task, arg) != 0) |
1c101da8 CM |
647 | return -EINVAL; |
648 | ||
93f067f6 | 649 | update_ti_thread_flag(ti, TIF_TAGGED_ADDR, arg & PR_TAGGED_ADDR_ENABLE); |
63f0c603 CM |
650 | |
651 | return 0; | |
652 | } | |
653 | ||
93f067f6 | 654 | long get_tagged_addr_ctrl(struct task_struct *task) |
63f0c603 | 655 | { |
1c101da8 | 656 | long ret = 0; |
93f067f6 | 657 | struct thread_info *ti = task_thread_info(task); |
1c101da8 | 658 | |
93f067f6 | 659 | if (is_compat_thread(ti)) |
63f0c603 CM |
660 | return -EINVAL; |
661 | ||
93f067f6 | 662 | if (test_ti_thread_flag(ti, TIF_TAGGED_ADDR)) |
1c101da8 | 663 | ret = PR_TAGGED_ADDR_ENABLE; |
63f0c603 | 664 | |
93f067f6 | 665 | ret |= get_mte_ctrl(task); |
1c101da8 CM |
666 | |
667 | return ret; | |
63f0c603 CM |
668 | } |
669 | ||
670 | /* | |
671 | * Global sysctl to disable the tagged user addresses support. This control | |
672 | * only prevents the tagged address ABI enabling via prctl() and does not | |
673 | * disable it for tasks that already opted in to the relaxed ABI. | |
674 | */ | |
63f0c603 CM |
675 | |
676 | static struct ctl_table tagged_addr_sysctl_table[] = { | |
677 | { | |
413235fc | 678 | .procname = "tagged_addr_disabled", |
63f0c603 | 679 | .mode = 0644, |
413235fc | 680 | .data = &tagged_addr_disabled, |
63f0c603 CM |
681 | .maxlen = sizeof(int), |
682 | .proc_handler = proc_dointvec_minmax, | |
2c614c11 MC |
683 | .extra1 = SYSCTL_ZERO, |
684 | .extra2 = SYSCTL_ONE, | |
63f0c603 CM |
685 | }, |
686 | { } | |
687 | }; | |
688 | ||
689 | static int __init tagged_addr_init(void) | |
690 | { | |
691 | if (!register_sysctl("abi", tagged_addr_sysctl_table)) | |
692 | return -EINVAL; | |
693 | return 0; | |
694 | } | |
695 | ||
696 | core_initcall(tagged_addr_init); | |
697 | #endif /* CONFIG_ARM64_TAGGED_ADDR_ABI */ | |
19c95f26 JT |
698 | |
699 | asmlinkage void __sched arm64_preempt_schedule_irq(void) | |
700 | { | |
701 | lockdep_assert_irqs_disabled(); | |
702 | ||
703 | /* | |
704 | * Preempting a task from an IRQ means we leave copies of PSTATE | |
705 | * on the stack. cpufeature's enable calls may modify PSTATE, but | |
706 | * resuming one of these preempted tasks would undo those changes. | |
707 | * | |
708 | * Only allow a task to be preempted once cpufeatures have been | |
709 | * enabled. | |
710 | */ | |
b51c6ac2 | 711 | if (system_capabilities_finalized()) |
19c95f26 JT |
712 | preempt_schedule_irq(); |
713 | } | |
ab7876a9 DM |
714 | |
715 | #ifdef CONFIG_BINFMT_ELF | |
716 | int arch_elf_adjust_prot(int prot, const struct arch_elf_state *state, | |
717 | bool has_interp, bool is_interp) | |
718 | { | |
5d1b631c MB |
719 | /* |
720 | * For dynamically linked executables the interpreter is | |
721 | * responsible for setting PROT_BTI on everything except | |
722 | * itself. | |
723 | */ | |
ab7876a9 DM |
724 | if (is_interp != has_interp) |
725 | return prot; | |
726 | ||
727 | if (!(state->flags & ARM64_ELF_BTI)) | |
728 | return prot; | |
729 | ||
730 | if (prot & PROT_EXEC) | |
731 | prot |= PROT_BTI; | |
732 | ||
733 | return prot; | |
734 | } | |
735 | #endif |