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arm64: introduce aarch64_insn_gen_add_sub_shifted_reg()
[linux-2.6-block.git] / arch / arm64 / kernel / insn.c
CommitLineData
b11a64a4
JL		 1/*
2 * Copyright (C) 2013 Huawei Ltd.
3 * Author: Jiang Liu <liuj97@gmail.com>
4 *
617d2fbc
ZSL		 5 * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
6 *
b11a64a4
JL		 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
5c5bf25d 19#include <linux/bitops.h>
b11a64a4
JL		 20#include <linux/compiler.h>
21#include <linux/kernel.h>
ae164807
JL		 22#include <linux/smp.h>
23#include <linux/stop_machine.h>
24#include <linux/uaccess.h>
25#include <asm/cacheflush.h>
b11a64a4
JL		 26#include <asm/insn.h>
27
617d2fbc 28#define AARCH64_INSN_SF_BIT BIT(31)
4a89d2c9 29#define AARCH64_INSN_N_BIT BIT(22)
617d2fbc 30
b11a64a4
JL		 31static int aarch64_insn_encoding_class[] = {
32 AARCH64_INSN_CLS_UNKNOWN,
33 AARCH64_INSN_CLS_UNKNOWN,
34 AARCH64_INSN_CLS_UNKNOWN,
35 AARCH64_INSN_CLS_UNKNOWN,
36 AARCH64_INSN_CLS_LDST,
37 AARCH64_INSN_CLS_DP_REG,
38 AARCH64_INSN_CLS_LDST,
39 AARCH64_INSN_CLS_DP_FPSIMD,
40 AARCH64_INSN_CLS_DP_IMM,
41 AARCH64_INSN_CLS_DP_IMM,
42 AARCH64_INSN_CLS_BR_SYS,
43 AARCH64_INSN_CLS_BR_SYS,
44 AARCH64_INSN_CLS_LDST,
45 AARCH64_INSN_CLS_DP_REG,
46 AARCH64_INSN_CLS_LDST,
47 AARCH64_INSN_CLS_DP_FPSIMD,
48};
49
50enum aarch64_insn_encoding_class __kprobes aarch64_get_insn_class(u32 insn)
51{
52 return aarch64_insn_encoding_class[(insn >> 25) & 0xf];
53}
54
55/* NOP is an alias of HINT */
56bool __kprobes aarch64_insn_is_nop(u32 insn)
57{
58 if (!aarch64_insn_is_hint(insn))
59 return false;
60
61 switch (insn & 0xFE0) {
62 case AARCH64_INSN_HINT_YIELD:
63 case AARCH64_INSN_HINT_WFE:
64 case AARCH64_INSN_HINT_WFI:
65 case AARCH64_INSN_HINT_SEV:
66 case AARCH64_INSN_HINT_SEVL:
67 return false;
68 default:
69 return true;
70 }
71}
72
ae164807
JL		 73/*
74 * In ARMv8-A, A64 instructions have a fixed length of 32 bits and are always
75 * little-endian.
76 */
77int __kprobes aarch64_insn_read(void *addr, u32 *insnp)
78{
79 int ret;
80 u32 val;
81
82 ret = probe_kernel_read(&val, addr, AARCH64_INSN_SIZE);
83 if (!ret)
84 *insnp = le32_to_cpu(val);
85
86 return ret;
87}
88
89int __kprobes aarch64_insn_write(void *addr, u32 insn)
90{
91 insn = cpu_to_le32(insn);
92 return probe_kernel_write(addr, &insn, AARCH64_INSN_SIZE);
93}
94
b11a64a4
JL		 95static bool __kprobes __aarch64_insn_hotpatch_safe(u32 insn)
96{
97 if (aarch64_get_insn_class(insn) != AARCH64_INSN_CLS_BR_SYS)
98 return false;
99
100 return aarch64_insn_is_b(insn) ||
101 aarch64_insn_is_bl(insn) ||
102 aarch64_insn_is_svc(insn) ||
103 aarch64_insn_is_hvc(insn) ||
104 aarch64_insn_is_smc(insn) ||
105 aarch64_insn_is_brk(insn) ||
106 aarch64_insn_is_nop(insn);
107}
108
109/*
110 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
111 * Section B2.6.5 "Concurrent modification and execution of instructions":
112 * Concurrent modification and execution of instructions can lead to the
113 * resulting instruction performing any behavior that can be achieved by
114 * executing any sequence of instructions that can be executed from the
115 * same Exception level, except where the instruction before modification
116 * and the instruction after modification is a B, BL, NOP, BKPT, SVC, HVC,
117 * or SMC instruction.
118 */
119bool __kprobes aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn)
120{
121 return __aarch64_insn_hotpatch_safe(old_insn) &&
122 __aarch64_insn_hotpatch_safe(new_insn);
123}
ae164807
JL		 124
125int __kprobes aarch64_insn_patch_text_nosync(void *addr, u32 insn)
126{
127 u32 *tp = addr;
128 int ret;
129
130 /* A64 instructions must be word aligned */
131 if ((uintptr_t)tp & 0x3)
132 return -EINVAL;
133
134 ret = aarch64_insn_write(tp, insn);
135 if (ret == 0)
136 flush_icache_range((uintptr_t)tp,
137 (uintptr_t)tp + AARCH64_INSN_SIZE);
138
139 return ret;
140}
141
142struct aarch64_insn_patch {
143 void **text_addrs;
144 u32 *new_insns;
145 int insn_cnt;
146 atomic_t cpu_count;
147};
148
149static int __kprobes aarch64_insn_patch_text_cb(void *arg)
150{
151 int i, ret = 0;
152 struct aarch64_insn_patch *pp = arg;
153
154 /* The first CPU becomes master */
155 if (atomic_inc_return(&pp->cpu_count) == 1) {
156 for (i = 0; ret == 0 && i < pp->insn_cnt; i++)
157 ret = aarch64_insn_patch_text_nosync(pp->text_addrs[i],
158 pp->new_insns[i]);
159 /*
160 * aarch64_insn_patch_text_nosync() calls flush_icache_range(),
161 * which ends with "dsb; isb" pair guaranteeing global
162 * visibility.
163 */
164 atomic_set(&pp->cpu_count, -1);
165 } else {
166 while (atomic_read(&pp->cpu_count) != -1)
167 cpu_relax();
168 isb();
169 }
170
171 return ret;
172}
173
174int __kprobes aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt)
175{
176 struct aarch64_insn_patch patch = {
177 .text_addrs = addrs,
178 .new_insns = insns,
179 .insn_cnt = cnt,
180 .cpu_count = ATOMIC_INIT(0),
181 };
182
183 if (cnt <= 0)
184 return -EINVAL;
185
186 return stop_machine(aarch64_insn_patch_text_cb, &patch,
187 cpu_online_mask);
188}
189
190int __kprobes aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt)
191{
192 int ret;
193 u32 insn;
194
195 /* Unsafe to patch multiple instructions without synchronizaiton */
196 if (cnt == 1) {
197 ret = aarch64_insn_read(addrs[0], &insn);
198 if (ret)
199 return ret;
200
201 if (aarch64_insn_hotpatch_safe(insn, insns[0])) {
202 /*
203 * ARMv8 architecture doesn't guarantee all CPUs see
204 * the new instruction after returning from function
205 * aarch64_insn_patch_text_nosync(). So send IPIs to
206 * all other CPUs to achieve instruction
207 * synchronization.
208 */
209 ret = aarch64_insn_patch_text_nosync(addrs[0], insns[0]);
210 kick_all_cpus_sync();
211 return ret;
212 }
213 }
214
215 return aarch64_insn_patch_text_sync(addrs, insns, cnt);
216}
c84fced8
JL		 217
218u32 __kprobes aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
219 u32 insn, u64 imm)
220{
221 u32 immlo, immhi, lomask, himask, mask;
222 int shift;
223
224 switch (type) {
225 case AARCH64_INSN_IMM_ADR:
226 lomask = 0x3;
227 himask = 0x7ffff;
228 immlo = imm & lomask;
229 imm >>= 2;
230 immhi = imm & himask;
231 imm = (immlo << 24) | (immhi);
232 mask = (lomask << 24) | (himask);
233 shift = 5;
234 break;
235 case AARCH64_INSN_IMM_26:
236 mask = BIT(26) - 1;
237 shift = 0;
238 break;
239 case AARCH64_INSN_IMM_19:
240 mask = BIT(19) - 1;
241 shift = 5;
242 break;
243 case AARCH64_INSN_IMM_16:
244 mask = BIT(16) - 1;
245 shift = 5;
246 break;
247 case AARCH64_INSN_IMM_14:
248 mask = BIT(14) - 1;
249 shift = 5;
250 break;
251 case AARCH64_INSN_IMM_12:
252 mask = BIT(12) - 1;
253 shift = 10;
254 break;
255 case AARCH64_INSN_IMM_9:
256 mask = BIT(9) - 1;
257 shift = 12;
258 break;
1bba567d
ZSL		 259 case AARCH64_INSN_IMM_7:
260 mask = BIT(7) - 1;
261 shift = 15;
262 break;
5fdc639a 263 case AARCH64_INSN_IMM_6:
4a89d2c9
ZSL		 264 case AARCH64_INSN_IMM_S:
265 mask = BIT(6) - 1;
266 shift = 10;
267 break;
268 case AARCH64_INSN_IMM_R:
269 mask = BIT(6) - 1;
270 shift = 16;
271 break;
c84fced8
JL		 272 default:
273 pr_err("aarch64_insn_encode_immediate: unknown immediate encoding %d\n",
274 type);
275 return 0;
276 }
277
278 /* Update the immediate field. */
279 insn &= ~(mask << shift);
280 insn |= (imm & mask) << shift;
281
282 return insn;
283}
5c5bf25d 284
617d2fbc
ZSL		 285static u32 aarch64_insn_encode_register(enum aarch64_insn_register_type type,
286 u32 insn,
287 enum aarch64_insn_register reg)
288{
289 int shift;
290
291 if (reg < AARCH64_INSN_REG_0 || reg > AARCH64_INSN_REG_SP) {
292 pr_err("%s: unknown register encoding %d\n", __func__, reg);
293 return 0;
294 }
295
296 switch (type) {
297 case AARCH64_INSN_REGTYPE_RT:
9951a157 298 case AARCH64_INSN_REGTYPE_RD:
617d2fbc
ZSL		 299 shift = 0;
300 break;
c0cafbae
ZSL		 301 case AARCH64_INSN_REGTYPE_RN:
302 shift = 5;
303 break;
1bba567d
ZSL		 304 case AARCH64_INSN_REGTYPE_RT2:
305 shift = 10;
306 break;
17cac179
ZSL		 307 case AARCH64_INSN_REGTYPE_RM:
308 shift = 16;
309 break;
617d2fbc
ZSL		 310 default:
311 pr_err("%s: unknown register type encoding %d\n", __func__,
312 type);
313 return 0;
314 }
315
316 insn &= ~(GENMASK(4, 0) << shift);
317 insn |= reg << shift;
318
319 return insn;
320}
321
17cac179
ZSL		 322static u32 aarch64_insn_encode_ldst_size(enum aarch64_insn_size_type type,
323 u32 insn)
324{
325 u32 size;
326
327 switch (type) {
328 case AARCH64_INSN_SIZE_8:
329 size = 0;
330 break;
331 case AARCH64_INSN_SIZE_16:
332 size = 1;
333 break;
334 case AARCH64_INSN_SIZE_32:
335 size = 2;
336 break;
337 case AARCH64_INSN_SIZE_64:
338 size = 3;
339 break;
340 default:
341 pr_err("%s: unknown size encoding %d\n", __func__, type);
342 return 0;
343 }
344
345 insn &= ~GENMASK(31, 30);
346 insn |= size << 30;
347
348 return insn;
349}
350
617d2fbc
ZSL		 351static inline long branch_imm_common(unsigned long pc, unsigned long addr,
352 long range)
5c5bf25d 353{
5c5bf25d
JL		 354 long offset;
355
356 /*
357 * PC: A 64-bit Program Counter holding the address of the current
358 * instruction. A64 instructions must be word-aligned.
359 */
360 BUG_ON((pc & 0x3) || (addr & 0x3));
361
617d2fbc
ZSL		 362 offset = ((long)addr - (long)pc);
363 BUG_ON(offset < -range || offset >= range);
364
365 return offset;
366}
367
368u32 __kprobes aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
369 enum aarch64_insn_branch_type type)
370{
371 u32 insn;
372 long offset;
373
5c5bf25d
JL		 374 /*
375 * B/BL support [-128M, 128M) offset
376 * ARM64 virtual address arrangement guarantees all kernel and module
377 * texts are within +/-128M.
378 */
617d2fbc 379 offset = branch_imm_common(pc, addr, SZ_128M);
5c5bf25d 380
c0cafbae
ZSL		 381 switch (type) {
382 case AARCH64_INSN_BRANCH_LINK:
5c5bf25d 383 insn = aarch64_insn_get_bl_value();
c0cafbae
ZSL		 384 break;
385 case AARCH64_INSN_BRANCH_NOLINK:
5c5bf25d 386 insn = aarch64_insn_get_b_value();
c0cafbae
ZSL		 387 break;
388 default:
389 BUG_ON(1);
390 }
5c5bf25d
JL		 391
392 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn,
393 offset >> 2);
394}
395
617d2fbc
ZSL		 396u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
397 enum aarch64_insn_register reg,
398 enum aarch64_insn_variant variant,
399 enum aarch64_insn_branch_type type)
400{
401 u32 insn;
402 long offset;
403
404 offset = branch_imm_common(pc, addr, SZ_1M);
405
406 switch (type) {
407 case AARCH64_INSN_BRANCH_COMP_ZERO:
408 insn = aarch64_insn_get_cbz_value();
409 break;
410 case AARCH64_INSN_BRANCH_COMP_NONZERO:
411 insn = aarch64_insn_get_cbnz_value();
412 break;
413 default:
414 BUG_ON(1);
415 }
416
417 switch (variant) {
418 case AARCH64_INSN_VARIANT_32BIT:
419 break;
420 case AARCH64_INSN_VARIANT_64BIT:
421 insn |= AARCH64_INSN_SF_BIT;
422 break;
423 default:
424 BUG_ON(1);
425 }
426
427 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
428
429 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
430 offset >> 2);
431}
432
345e0d35
ZSL		 433u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
434 enum aarch64_insn_condition cond)
435{
436 u32 insn;
437 long offset;
438
439 offset = branch_imm_common(pc, addr, SZ_1M);
440
441 insn = aarch64_insn_get_bcond_value();
442
443 BUG_ON(cond < AARCH64_INSN_COND_EQ || cond > AARCH64_INSN_COND_AL);
444 insn |= cond;
445
446 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
447 offset >> 2);
448}
449
5c5bf25d
JL		 450u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_op op)
451{
452 return aarch64_insn_get_hint_value() | op;
453}
454
455u32 __kprobes aarch64_insn_gen_nop(void)
456{
457 return aarch64_insn_gen_hint(AARCH64_INSN_HINT_NOP);
458}
c0cafbae
ZSL		 459
460u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
461 enum aarch64_insn_branch_type type)
462{
463 u32 insn;
464
465 switch (type) {
466 case AARCH64_INSN_BRANCH_NOLINK:
467 insn = aarch64_insn_get_br_value();
468 break;
469 case AARCH64_INSN_BRANCH_LINK:
470 insn = aarch64_insn_get_blr_value();
471 break;
472 case AARCH64_INSN_BRANCH_RETURN:
473 insn = aarch64_insn_get_ret_value();
474 break;
475 default:
476 BUG_ON(1);
477 }
478
479 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, reg);
480}
17cac179
ZSL		 481
482u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
483 enum aarch64_insn_register base,
484 enum aarch64_insn_register offset,
485 enum aarch64_insn_size_type size,
486 enum aarch64_insn_ldst_type type)
487{
488 u32 insn;
489
490 switch (type) {
491 case AARCH64_INSN_LDST_LOAD_REG_OFFSET:
492 insn = aarch64_insn_get_ldr_reg_value();
493 break;
494 case AARCH64_INSN_LDST_STORE_REG_OFFSET:
495 insn = aarch64_insn_get_str_reg_value();
496 break;
497 default:
498 BUG_ON(1);
499 }
500
501 insn = aarch64_insn_encode_ldst_size(size, insn);
502
503 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
504
505 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
506 base);
507
508 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
509 offset);
510}
1bba567d
ZSL		 511
512u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
513 enum aarch64_insn_register reg2,
514 enum aarch64_insn_register base,
515 int offset,
516 enum aarch64_insn_variant variant,
517 enum aarch64_insn_ldst_type type)
518{
519 u32 insn;
520 int shift;
521
522 switch (type) {
523 case AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX:
524 insn = aarch64_insn_get_ldp_pre_value();
525 break;
526 case AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX:
527 insn = aarch64_insn_get_stp_pre_value();
528 break;
529 case AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX:
530 insn = aarch64_insn_get_ldp_post_value();
531 break;
532 case AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX:
533 insn = aarch64_insn_get_stp_post_value();
534 break;
535 default:
536 BUG_ON(1);
537 }
538
539 switch (variant) {
540 case AARCH64_INSN_VARIANT_32BIT:
541 /* offset must be multiples of 4 in the range [-256, 252] */
542 BUG_ON(offset & 0x3);
543 BUG_ON(offset < -256 || offset > 252);
544 shift = 2;
545 break;
546 case AARCH64_INSN_VARIANT_64BIT:
547 /* offset must be multiples of 8 in the range [-512, 504] */
548 BUG_ON(offset & 0x7);
549 BUG_ON(offset < -512 || offset > 504);
550 shift = 3;
551 insn |= AARCH64_INSN_SF_BIT;
552 break;
553 default:
554 BUG_ON(1);
555 }
556
557 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
558 reg1);
559
560 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT2, insn,
561 reg2);
562
563 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
564 base);
565
566 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_7, insn,
567 offset >> shift);
568}
9951a157
ZSL		 569
570u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
571 enum aarch64_insn_register src,
572 int imm, enum aarch64_insn_variant variant,
573 enum aarch64_insn_adsb_type type)
574{
575 u32 insn;
576
577 switch (type) {
578 case AARCH64_INSN_ADSB_ADD:
579 insn = aarch64_insn_get_add_imm_value();
580 break;
581 case AARCH64_INSN_ADSB_SUB:
582 insn = aarch64_insn_get_sub_imm_value();
583 break;
584 case AARCH64_INSN_ADSB_ADD_SETFLAGS:
585 insn = aarch64_insn_get_adds_imm_value();
586 break;
587 case AARCH64_INSN_ADSB_SUB_SETFLAGS:
588 insn = aarch64_insn_get_subs_imm_value();
589 break;
590 default:
591 BUG_ON(1);
592 }
593
594 switch (variant) {
595 case AARCH64_INSN_VARIANT_32BIT:
596 break;
597 case AARCH64_INSN_VARIANT_64BIT:
598 insn |= AARCH64_INSN_SF_BIT;
599 break;
600 default:
601 BUG_ON(1);
602 }
603
604 BUG_ON(imm & ~(SZ_4K - 1));
605
606 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
607
608 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
609
610 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_12, insn, imm);
611}
4a89d2c9
ZSL		 612
613u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
614 enum aarch64_insn_register src,
615 int immr, int imms,
616 enum aarch64_insn_variant variant,
617 enum aarch64_insn_bitfield_type type)
618{
619 u32 insn;
620 u32 mask;
621
622 switch (type) {
623 case AARCH64_INSN_BITFIELD_MOVE:
624 insn = aarch64_insn_get_bfm_value();
625 break;
626 case AARCH64_INSN_BITFIELD_MOVE_UNSIGNED:
627 insn = aarch64_insn_get_ubfm_value();
628 break;
629 case AARCH64_INSN_BITFIELD_MOVE_SIGNED:
630 insn = aarch64_insn_get_sbfm_value();
631 break;
632 default:
633 BUG_ON(1);
634 }
635
636 switch (variant) {
637 case AARCH64_INSN_VARIANT_32BIT:
638 mask = GENMASK(4, 0);
639 break;
640 case AARCH64_INSN_VARIANT_64BIT:
641 insn |= AARCH64_INSN_SF_BIT | AARCH64_INSN_N_BIT;
642 mask = GENMASK(5, 0);
643 break;
644 default:
645 BUG_ON(1);
646 }
647
648 BUG_ON(immr & ~mask);
649 BUG_ON(imms & ~mask);
650
651 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
652
653 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
654
655 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_R, insn, immr);
656
657 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, imms);
658}
6098f2d5
ZSL		 659
660u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
661 int imm, int shift,
662 enum aarch64_insn_variant variant,
663 enum aarch64_insn_movewide_type type)
664{
665 u32 insn;
666
667 switch (type) {
668 case AARCH64_INSN_MOVEWIDE_ZERO:
669 insn = aarch64_insn_get_movz_value();
670 break;
671 case AARCH64_INSN_MOVEWIDE_KEEP:
672 insn = aarch64_insn_get_movk_value();
673 break;
674 case AARCH64_INSN_MOVEWIDE_INVERSE:
675 insn = aarch64_insn_get_movn_value();
676 break;
677 default:
678 BUG_ON(1);
679 }
680
681 BUG_ON(imm & ~(SZ_64K - 1));
682
683 switch (variant) {
684 case AARCH64_INSN_VARIANT_32BIT:
685 BUG_ON(shift != 0 && shift != 16);
686 break;
687 case AARCH64_INSN_VARIANT_64BIT:
688 insn |= AARCH64_INSN_SF_BIT;
689 BUG_ON(shift != 0 && shift != 16 && shift != 32 &&
690 shift != 48);
691 break;
692 default:
693 BUG_ON(1);
694 }
695
696 insn |= (shift >> 4) << 21;
697
698 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
699
700 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm);
701}
5fdc639a
ZSL		 702
703u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
704 enum aarch64_insn_register src,
705 enum aarch64_insn_register reg,
706 int shift,
707 enum aarch64_insn_variant variant,
708 enum aarch64_insn_adsb_type type)
709{
710 u32 insn;
711
712 switch (type) {
713 case AARCH64_INSN_ADSB_ADD:
714 insn = aarch64_insn_get_add_value();
715 break;
716 case AARCH64_INSN_ADSB_SUB:
717 insn = aarch64_insn_get_sub_value();
718 break;
719 case AARCH64_INSN_ADSB_ADD_SETFLAGS:
720 insn = aarch64_insn_get_adds_value();
721 break;
722 case AARCH64_INSN_ADSB_SUB_SETFLAGS:
723 insn = aarch64_insn_get_subs_value();
724 break;
725 default:
726 BUG_ON(1);
727 }
728
729 switch (variant) {
730 case AARCH64_INSN_VARIANT_32BIT:
731 BUG_ON(shift & ~(SZ_32 - 1));
732 break;
733 case AARCH64_INSN_VARIANT_64BIT:
734 insn |= AARCH64_INSN_SF_BIT;
735 BUG_ON(shift & ~(SZ_64 - 1));
736 break;
737 default:
738 BUG_ON(1);
739 }
740
741
742 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
743
744 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
745
746 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
747
748 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
749}
Linux 6.x block layer and io_uring tree(s)