[linux-2.6-block.git] / arch / arm64 / kernel / insn.c

/*
 * Copyright (C) 2013 Huawei Ltd.
 * Author: Jiang Liu <liuj97@gmail.com>
 *
 * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#include <linux/bitops.h>
#include <linux/compiler.h>
#include <linux/kernel.h>
#include <linux/smp.h>
#include <linux/stop_machine.h>
#include <linux/uaccess.h>
#include <asm/cacheflush.h>
#include <asm/insn.h>

#define AARCH64_INSN_SF_BIT	BIT(31)

static int aarch64_insn_encoding_class[] = {
	AARCH64_INSN_CLS_UNKNOWN,
	AARCH64_INSN_CLS_UNKNOWN,
	AARCH64_INSN_CLS_UNKNOWN,
	AARCH64_INSN_CLS_UNKNOWN,
	AARCH64_INSN_CLS_LDST,
	AARCH64_INSN_CLS_DP_REG,
	AARCH64_INSN_CLS_LDST,
	AARCH64_INSN_CLS_DP_FPSIMD,
	AARCH64_INSN_CLS_DP_IMM,
	AARCH64_INSN_CLS_DP_IMM,
	AARCH64_INSN_CLS_BR_SYS,
	AARCH64_INSN_CLS_BR_SYS,
	AARCH64_INSN_CLS_LDST,
	AARCH64_INSN_CLS_DP_REG,
	AARCH64_INSN_CLS_LDST,
	AARCH64_INSN_CLS_DP_FPSIMD,
};

enum aarch64_insn_encoding_class __kprobes aarch64_get_insn_class(u32 insn)
{
	return aarch64_insn_encoding_class[(insn >> 25) & 0xf];
}

/* NOP is an alias of HINT */
bool __kprobes aarch64_insn_is_nop(u32 insn)
{
	if (!aarch64_insn_is_hint(insn))
		return false;

	switch (insn & 0xFE0) {
	case AARCH64_INSN_HINT_YIELD:
	case AARCH64_INSN_HINT_WFE:
	case AARCH64_INSN_HINT_WFI:
	case AARCH64_INSN_HINT_SEV:
	case AARCH64_INSN_HINT_SEVL:
		return false;
	default:
		return true;
	}
}

/*
 * In ARMv8-A, A64 instructions have a fixed length of 32 bits and are always
 * little-endian.
 */
int __kprobes aarch64_insn_read(void *addr, u32 *insnp)
{
	int ret;
	u32 val;

	ret = probe_kernel_read(&val, addr, AARCH64_INSN_SIZE);
	if (!ret)
		*insnp = le32_to_cpu(val);

	return ret;
}

int __kprobes aarch64_insn_write(void *addr, u32 insn)
{
	insn = cpu_to_le32(insn);
	return probe_kernel_write(addr, &insn, AARCH64_INSN_SIZE);
}

static bool __kprobes __aarch64_insn_hotpatch_safe(u32 insn)
{
	if (aarch64_get_insn_class(insn) != AARCH64_INSN_CLS_BR_SYS)
		return false;

	return	aarch64_insn_is_b(insn) ||
		aarch64_insn_is_bl(insn) ||
		aarch64_insn_is_svc(insn) ||
		aarch64_insn_is_hvc(insn) ||
		aarch64_insn_is_smc(insn) ||
		aarch64_insn_is_brk(insn) ||
		aarch64_insn_is_nop(insn);
}

/*
 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
 * Section B2.6.5 "Concurrent modification and execution of instructions":
 * Concurrent modification and execution of instructions can lead to the
 * resulting instruction performing any behavior that can be achieved by
 * executing any sequence of instructions that can be executed from the
 * same Exception level, except where the instruction before modification
 * and the instruction after modification is a B, BL, NOP, BKPT, SVC, HVC,
 * or SMC instruction.
 */
bool __kprobes aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn)
{
	return __aarch64_insn_hotpatch_safe(old_insn) &&
	       __aarch64_insn_hotpatch_safe(new_insn);
}

int __kprobes aarch64_insn_patch_text_nosync(void *addr, u32 insn)
{
	u32 *tp = addr;
	int ret;

	/* A64 instructions must be word aligned */
	if ((uintptr_t)tp & 0x3)
		return -EINVAL;

	ret = aarch64_insn_write(tp, insn);
	if (ret == 0)
		flush_icache_range((uintptr_t)tp,
				   (uintptr_t)tp + AARCH64_INSN_SIZE);

	return ret;
}

struct aarch64_insn_patch {
	void		**text_addrs;
	u32		*new_insns;
	int		insn_cnt;
	atomic_t	cpu_count;
};

static int __kprobes aarch64_insn_patch_text_cb(void *arg)
{
	int i, ret = 0;
	struct aarch64_insn_patch *pp = arg;

	/* The first CPU becomes master */
	if (atomic_inc_return(&pp->cpu_count) == 1) {
		for (i = 0; ret == 0 && i < pp->insn_cnt; i++)
			ret = aarch64_insn_patch_text_nosync(pp->text_addrs[i],
							     pp->new_insns[i]);
		/*
		 * aarch64_insn_patch_text_nosync() calls flush_icache_range(),
		 * which ends with "dsb; isb" pair guaranteeing global
		 * visibility.
		 */
		atomic_set(&pp->cpu_count, -1);
	} else {
		while (atomic_read(&pp->cpu_count) != -1)
			cpu_relax();
		isb();
	}

	return ret;
}

int __kprobes aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt)
{
	struct aarch64_insn_patch patch = {
		.text_addrs = addrs,
		.new_insns = insns,
		.insn_cnt = cnt,
		.cpu_count = ATOMIC_INIT(0),
	};

	if (cnt <= 0)
		return -EINVAL;

	return stop_machine(aarch64_insn_patch_text_cb, &patch,
			    cpu_online_mask);
}

int __kprobes aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt)
{
	int ret;
	u32 insn;

	/* Unsafe to patch multiple instructions without synchronizaiton */
	if (cnt == 1) {
		ret = aarch64_insn_read(addrs[0], &insn);
		if (ret)
			return ret;

		if (aarch64_insn_hotpatch_safe(insn, insns[0])) {
			/*
			 * ARMv8 architecture doesn't guarantee all CPUs see
			 * the new instruction after returning from function
			 * aarch64_insn_patch_text_nosync(). So send IPIs to
			 * all other CPUs to achieve instruction
			 * synchronization.
			 */
			ret = aarch64_insn_patch_text_nosync(addrs[0], insns[0]);
			kick_all_cpus_sync();
			return ret;
		}
	}

	return aarch64_insn_patch_text_sync(addrs, insns, cnt);
}

u32 __kprobes aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
				  u32 insn, u64 imm)
{
	u32 immlo, immhi, lomask, himask, mask;
	int shift;

	switch (type) {
	case AARCH64_INSN_IMM_ADR:
		lomask = 0x3;
		himask = 0x7ffff;
		immlo = imm & lomask;
		imm >>= 2;
		immhi = imm & himask;
		imm = (immlo << 24) | (immhi);
		mask = (lomask << 24) | (himask);
		shift = 5;
		break;
	case AARCH64_INSN_IMM_26:
		mask = BIT(26) - 1;
		shift = 0;
		break;
	case AARCH64_INSN_IMM_19:
		mask = BIT(19) - 1;
		shift = 5;
		break;
	case AARCH64_INSN_IMM_16:
		mask = BIT(16) - 1;
		shift = 5;
		break;
	case AARCH64_INSN_IMM_14:
		mask = BIT(14) - 1;
		shift = 5;
		break;
	case AARCH64_INSN_IMM_12:
		mask = BIT(12) - 1;
		shift = 10;
		break;
	case AARCH64_INSN_IMM_9:
		mask = BIT(9) - 1;
		shift = 12;
		break;
	default:
		pr_err("aarch64_insn_encode_immediate: unknown immediate encoding %d\n",
			type);
		return 0;
	}

	/* Update the immediate field. */
	insn &= ~(mask << shift);
	insn |= (imm & mask) << shift;

	return insn;
}

static u32 aarch64_insn_encode_register(enum aarch64_insn_register_type type,
					u32 insn,
					enum aarch64_insn_register reg)
{
	int shift;

	if (reg < AARCH64_INSN_REG_0 || reg > AARCH64_INSN_REG_SP) {
		pr_err("%s: unknown register encoding %d\n", __func__, reg);
		return 0;
	}

	switch (type) {
	case AARCH64_INSN_REGTYPE_RT:
		shift = 0;
		break;
	case AARCH64_INSN_REGTYPE_RN:
		shift = 5;
		break;
	case AARCH64_INSN_REGTYPE_RM:
		shift = 16;
		break;
	default:
		pr_err("%s: unknown register type encoding %d\n", __func__,
		       type);
		return 0;
	}

	insn &= ~(GENMASK(4, 0) << shift);
	insn |= reg << shift;

	return insn;
}

static u32 aarch64_insn_encode_ldst_size(enum aarch64_insn_size_type type,
					 u32 insn)
{
	u32 size;

	switch (type) {
	case AARCH64_INSN_SIZE_8:
		size = 0;
		break;
	case AARCH64_INSN_SIZE_16:
		size = 1;
		break;
	case AARCH64_INSN_SIZE_32:
		size = 2;
		break;
	case AARCH64_INSN_SIZE_64:
		size = 3;
		break;
	default:
		pr_err("%s: unknown size encoding %d\n", __func__, type);
		return 0;
	}

	insn &= ~GENMASK(31, 30);
	insn |= size << 30;

	return insn;
}

static inline long branch_imm_common(unsigned long pc, unsigned long addr,
				     long range)
{
	long offset;

	/*
	 * PC: A 64-bit Program Counter holding the address of the current
	 * instruction. A64 instructions must be word-aligned.
	 */
	BUG_ON((pc & 0x3) || (addr & 0x3));

	offset = ((long)addr - (long)pc);
	BUG_ON(offset < -range || offset >= range);

	return offset;
}

u32 __kprobes aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
					  enum aarch64_insn_branch_type type)
{
	u32 insn;
	long offset;

	/*
	 * B/BL support [-128M, 128M) offset
	 * ARM64 virtual address arrangement guarantees all kernel and module
	 * texts are within +/-128M.
	 */
	offset = branch_imm_common(pc, addr, SZ_128M);

	switch (type) {
	case AARCH64_INSN_BRANCH_LINK:
		insn = aarch64_insn_get_bl_value();
		break;
	case AARCH64_INSN_BRANCH_NOLINK:
		insn = aarch64_insn_get_b_value();
		break;
	default:
		BUG_ON(1);
	}

	return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn,
					     offset >> 2);
}

u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
				     enum aarch64_insn_register reg,
				     enum aarch64_insn_variant variant,
				     enum aarch64_insn_branch_type type)
{
	u32 insn;
	long offset;

	offset = branch_imm_common(pc, addr, SZ_1M);

	switch (type) {
	case AARCH64_INSN_BRANCH_COMP_ZERO:
		insn = aarch64_insn_get_cbz_value();
		break;
	case AARCH64_INSN_BRANCH_COMP_NONZERO:
		insn = aarch64_insn_get_cbnz_value();
		break;
	default:
		BUG_ON(1);
	}

	switch (variant) {
	case AARCH64_INSN_VARIANT_32BIT:
		break;
	case AARCH64_INSN_VARIANT_64BIT:
		insn |= AARCH64_INSN_SF_BIT;
		break;
	default:
		BUG_ON(1);
	}

	insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);

	return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
					     offset >> 2);
}

u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
				     enum aarch64_insn_condition cond)
{
	u32 insn;
	long offset;

	offset = branch_imm_common(pc, addr, SZ_1M);

	insn = aarch64_insn_get_bcond_value();

	BUG_ON(cond < AARCH64_INSN_COND_EQ || cond > AARCH64_INSN_COND_AL);
	insn |= cond;

	return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
					     offset >> 2);
}

u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_op op)
{
	return aarch64_insn_get_hint_value() | op;
}

u32 __kprobes aarch64_insn_gen_nop(void)
{
	return aarch64_insn_gen_hint(AARCH64_INSN_HINT_NOP);
}

u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
				enum aarch64_insn_branch_type type)
{
	u32 insn;

	switch (type) {
	case AARCH64_INSN_BRANCH_NOLINK:
		insn = aarch64_insn_get_br_value();
		break;
	case AARCH64_INSN_BRANCH_LINK:
		insn = aarch64_insn_get_blr_value();
		break;
	case AARCH64_INSN_BRANCH_RETURN:
		insn = aarch64_insn_get_ret_value();
		break;
	default:
		BUG_ON(1);
	}

	return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, reg);
}

u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
				    enum aarch64_insn_register base,
				    enum aarch64_insn_register offset,
				    enum aarch64_insn_size_type size,
				    enum aarch64_insn_ldst_type type)
{
	u32 insn;

	switch (type) {
	case AARCH64_INSN_LDST_LOAD_REG_OFFSET:
		insn = aarch64_insn_get_ldr_reg_value();
		break;
	case AARCH64_INSN_LDST_STORE_REG_OFFSET:
		insn = aarch64_insn_get_str_reg_value();
		break;
	default:
		BUG_ON(1);
	}

	insn = aarch64_insn_encode_ldst_size(size, insn);

	insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);

	insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
					    base);

	return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
					    offset);
}
Commit	Line	Data
b11a64a4 JL	1	/*
	2	* Copyright (C) 2013 Huawei Ltd.
	3	* Author: Jiang Liu <liuj97@gmail.com>
	4	*
617d2fbc ZSL	5	* Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
617d2fbc ZSL	6	*
b11a64a4 JL	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
5c5bf25d	19	#include <linux/bitops.h>
b11a64a4 JL	20	#include <linux/compiler.h>
b11a64a4 JL	21	#include <linux/kernel.h>
ae164807 JL	22	#include <linux/smp.h>
	23	#include <linux/stop_machine.h>
	24	#include <linux/uaccess.h>
	25	#include <asm/cacheflush.h>
b11a64a4 JL	26	#include <asm/insn.h>
b11a64a4 JL	27
617d2fbc ZSL	28	#define AARCH64_INSN_SF_BIT BIT(31)
617d2fbc ZSL	29
b11a64a4 JL	30	static int aarch64_insn_encoding_class[] = {
	31	AARCH64_INSN_CLS_UNKNOWN,
	32	AARCH64_INSN_CLS_UNKNOWN,
	33	AARCH64_INSN_CLS_UNKNOWN,
	34	AARCH64_INSN_CLS_UNKNOWN,
	35	AARCH64_INSN_CLS_LDST,
	36	AARCH64_INSN_CLS_DP_REG,
	37	AARCH64_INSN_CLS_LDST,
	38	AARCH64_INSN_CLS_DP_FPSIMD,
	39	AARCH64_INSN_CLS_DP_IMM,
	40	AARCH64_INSN_CLS_DP_IMM,
	41	AARCH64_INSN_CLS_BR_SYS,
	42	AARCH64_INSN_CLS_BR_SYS,
	43	AARCH64_INSN_CLS_LDST,
	44	AARCH64_INSN_CLS_DP_REG,
	45	AARCH64_INSN_CLS_LDST,
	46	AARCH64_INSN_CLS_DP_FPSIMD,
	47	};
	48
	49	enum aarch64_insn_encoding_class __kprobes aarch64_get_insn_class(u32 insn)
	50	{
	51	return aarch64_insn_encoding_class[(insn >> 25) & 0xf];
	52	}
	53
	54	/* NOP is an alias of HINT */
	55	bool __kprobes aarch64_insn_is_nop(u32 insn)
	56	{
	57	if (!aarch64_insn_is_hint(insn))
	58	return false;
	59
	60	switch (insn & 0xFE0) {
	61	case AARCH64_INSN_HINT_YIELD:
	62	case AARCH64_INSN_HINT_WFE:
	63	case AARCH64_INSN_HINT_WFI:
	64	case AARCH64_INSN_HINT_SEV:
	65	case AARCH64_INSN_HINT_SEVL:
	66	return false;
	67	default:
	68	return true;
	69	}
	70	}
	71
ae164807 JL	72	/*
	73	* In ARMv8-A, A64 instructions have a fixed length of 32 bits and are always
	74	* little-endian.
	75	*/
	76	int __kprobes aarch64_insn_read(void addr, u32 insnp)
	77	{
	78	int ret;
	79	u32 val;
	80
	81	ret = probe_kernel_read(&val, addr, AARCH64_INSN_SIZE);
	82	if (!ret)
	83	*insnp = le32_to_cpu(val);
	84
	85	return ret;
	86	}
	87
	88	int __kprobes aarch64_insn_write(void *addr, u32 insn)
	89	{
	90	insn = cpu_to_le32(insn);
	91	return probe_kernel_write(addr, &insn, AARCH64_INSN_SIZE);
	92	}
	93
b11a64a4 JL	94	static bool __kprobes __aarch64_insn_hotpatch_safe(u32 insn)
	95	{
	96	if (aarch64_get_insn_class(insn) != AARCH64_INSN_CLS_BR_SYS)
	97	return false;
	98
	99	return aarch64_insn_is_b(insn) \|\|
	100	aarch64_insn_is_bl(insn) \|\|
	101	aarch64_insn_is_svc(insn) \|\|
	102	aarch64_insn_is_hvc(insn) \|\|
	103	aarch64_insn_is_smc(insn) \|\|
	104	aarch64_insn_is_brk(insn) \|\|
	105	aarch64_insn_is_nop(insn);
	106	}
	107
	108	/*
	109	* ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
	110	* Section B2.6.5 "Concurrent modification and execution of instructions":
	111	* Concurrent modification and execution of instructions can lead to the
	112	* resulting instruction performing any behavior that can be achieved by
	113	* executing any sequence of instructions that can be executed from the
	114	* same Exception level, except where the instruction before modification
	115	* and the instruction after modification is a B, BL, NOP, BKPT, SVC, HVC,
	116	* or SMC instruction.
	117	*/
	118	bool __kprobes aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn)
	119	{
	120	return __aarch64_insn_hotpatch_safe(old_insn) &&
	121	__aarch64_insn_hotpatch_safe(new_insn);
	122	}
ae164807 JL	123
	124	int __kprobes aarch64_insn_patch_text_nosync(void *addr, u32 insn)
	125	{
	126	u32 *tp = addr;
	127	int ret;
	128
	129	/* A64 instructions must be word aligned */
	130	if ((uintptr_t)tp & 0x3)
	131	return -EINVAL;
	132
	133	ret = aarch64_insn_write(tp, insn);
	134	if (ret == 0)
	135	flush_icache_range((uintptr_t)tp,
	136	(uintptr_t)tp + AARCH64_INSN_SIZE);
	137
	138	return ret;
	139	}
	140
	141	struct aarch64_insn_patch {
	142	void **text_addrs;
	143	u32 *new_insns;
	144	int insn_cnt;
	145	atomic_t cpu_count;
	146	};
	147
	148	static int __kprobes aarch64_insn_patch_text_cb(void *arg)
	149	{
	150	int i, ret = 0;
	151	struct aarch64_insn_patch *pp = arg;
	152
	153	/* The first CPU becomes master */
	154	if (atomic_inc_return(&pp->cpu_count) == 1) {
	155	for (i = 0; ret == 0 && i < pp->insn_cnt; i++)
	156	ret = aarch64_insn_patch_text_nosync(pp->text_addrs[i],
	157	pp->new_insns[i]);
	158	/*
	159	* aarch64_insn_patch_text_nosync() calls flush_icache_range(),
	160	* which ends with "dsb; isb" pair guaranteeing global
	161	* visibility.
	162	*/
	163	atomic_set(&pp->cpu_count, -1);
	164	} else {
	165	while (atomic_read(&pp->cpu_count) != -1)
	166	cpu_relax();
	167	isb();
	168	}
	169
	170	return ret;
	171	}
	172
	173	int __kprobes aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt)
	174	{
	175	struct aarch64_insn_patch patch = {
	176	.text_addrs = addrs,
	177	.new_insns = insns,
	178	.insn_cnt = cnt,
	179	.cpu_count = ATOMIC_INIT(0),
	180	};
	181
	182	if (cnt <= 0)
	183	return -EINVAL;
	184
	185	return stop_machine(aarch64_insn_patch_text_cb, &patch,
	186	cpu_online_mask);
187	}
188
189	int __kprobes aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt)
190	{
191	int ret;
192	u32 insn;
193
194	/* Unsafe to patch multiple instructions without synchronizaiton */
195	if (cnt == 1) {
196	ret = aarch64_insn_read(addrs[0], &insn);
197	if (ret)
198	return ret;
199
200	if (aarch64_insn_hotpatch_safe(insn, insns[0])) {
201	/*
202	* ARMv8 architecture doesn't guarantee all CPUs see
203	* the new instruction after returning from function
204	* aarch64_insn_patch_text_nosync(). So send IPIs to
205	* all other CPUs to achieve instruction
206	* synchronization.
207	*/
208	ret = aarch64_insn_patch_text_nosync(addrs[0], insns[0]);
209	kick_all_cpus_sync();
210	return ret;
211	}
212	}
213
214	return aarch64_insn_patch_text_sync(addrs, insns, cnt);
215	}
c84fced8 JL	216
	217	u32 __kprobes aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
	218	u32 insn, u64 imm)
	219	{
	220	u32 immlo, immhi, lomask, himask, mask;
	221	int shift;
	222
	223	switch (type) {
	224	case AARCH64_INSN_IMM_ADR:
	225	lomask = 0x3;
	226	himask = 0x7ffff;
	227	immlo = imm & lomask;
	228	imm >>= 2;
	229	immhi = imm & himask;
	230	imm = (immlo << 24) \| (immhi);
	231	mask = (lomask << 24) \| (himask);
	232	shift = 5;
	233	break;
	234	case AARCH64_INSN_IMM_26:
	235	mask = BIT(26) - 1;
	236	shift = 0;
	237	break;
	238	case AARCH64_INSN_IMM_19:
	239	mask = BIT(19) - 1;
	240	shift = 5;
	241	break;
	242	case AARCH64_INSN_IMM_16:
	243	mask = BIT(16) - 1;
	244	shift = 5;
	245	break;
	246	case AARCH64_INSN_IMM_14:
	247	mask = BIT(14) - 1;
	248	shift = 5;
	249	break;
	250	case AARCH64_INSN_IMM_12:
	251	mask = BIT(12) - 1;
	252	shift = 10;
	253	break;
	254	case AARCH64_INSN_IMM_9:
	255	mask = BIT(9) - 1;
	256	shift = 12;
	257	break;
	258	default:
	259	pr_err("aarch64_insn_encode_immediate: unknown immediate encoding %d\n",
	260	type);
	261	return 0;
	262	}
	263
	264	/* Update the immediate field. */
	265	insn &= ~(mask << shift);
	266	insn \|= (imm & mask) << shift;
	267
	268	return insn;
	269	}
5c5bf25d	270
617d2fbc ZSL	271	static u32 aarch64_insn_encode_register(enum aarch64_insn_register_type type,
	272	u32 insn,
	273	enum aarch64_insn_register reg)
	274	{
	275	int shift;
	276
	277	if (reg < AARCH64_INSN_REG_0 \|\| reg > AARCH64_INSN_REG_SP) {
	278	pr_err("%s: unknown register encoding %d\n", __func__, reg);
	279	return 0;
	280	}
	281
	282	switch (type) {
	283	case AARCH64_INSN_REGTYPE_RT:
	284	shift = 0;
	285	break;
c0cafbae ZSL	286	case AARCH64_INSN_REGTYPE_RN:
	287	shift = 5;
	288	break;
17cac179 ZSL	289	case AARCH64_INSN_REGTYPE_RM:
	290	shift = 16;
	291	break;
617d2fbc ZSL	292	default:
	293	pr_err("%s: unknown register type encoding %d\n", __func__,
	294	type);
	295	return 0;
	296	}
	297
	298	insn &= ~(GENMASK(4, 0) << shift);
	299	insn \|= reg << shift;
	300
	301	return insn;
	302	}
	303
17cac179 ZSL	304	static u32 aarch64_insn_encode_ldst_size(enum aarch64_insn_size_type type,
	305	u32 insn)
	306	{
	307	u32 size;
	308
	309	switch (type) {
	310	case AARCH64_INSN_SIZE_8:
	311	size = 0;
	312	break;
	313	case AARCH64_INSN_SIZE_16:
	314	size = 1;
	315	break;
	316	case AARCH64_INSN_SIZE_32:
	317	size = 2;
	318	break;
	319	case AARCH64_INSN_SIZE_64:
	320	size = 3;
	321	break;
	322	default:
	323	pr_err("%s: unknown size encoding %d\n", __func__, type);
	324	return 0;
	325	}
	326
	327	insn &= ~GENMASK(31, 30);
	328	insn \|= size << 30;
	329
	330	return insn;
	331	}
	332
617d2fbc ZSL	333	static inline long branch_imm_common(unsigned long pc, unsigned long addr,
617d2fbc ZSL	334	long range)
5c5bf25d	335	{
5c5bf25d JL	336	long offset;
	337
	338	/*
	339	* PC: A 64-bit Program Counter holding the address of the current
	340	* instruction. A64 instructions must be word-aligned.
	341	*/
	342	BUG_ON((pc & 0x3) \|\| (addr & 0x3));
	343
617d2fbc ZSL	344	offset = ((long)addr - (long)pc);
	345	BUG_ON(offset < -range \|\| offset >= range);
	346
	347	return offset;
	348	}
	349
	350	u32 __kprobes aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
	351	enum aarch64_insn_branch_type type)
	352	{
	353	u32 insn;
	354	long offset;
	355
5c5bf25d JL	356	/*
	357	* B/BL support [-128M, 128M) offset
	358	* ARM64 virtual address arrangement guarantees all kernel and module
	359	* texts are within +/-128M.
	360	*/
617d2fbc	361	offset = branch_imm_common(pc, addr, SZ_128M);
5c5bf25d	362
c0cafbae ZSL	363	switch (type) {
c0cafbae ZSL	364	case AARCH64_INSN_BRANCH_LINK:
5c5bf25d	365	insn = aarch64_insn_get_bl_value();
c0cafbae ZSL	366	break;
c0cafbae ZSL	367	case AARCH64_INSN_BRANCH_NOLINK:
5c5bf25d	368	insn = aarch64_insn_get_b_value();
c0cafbae ZSL	369	break;
	370	default:
	371	BUG_ON(1);
	372	}
5c5bf25d JL	373
	374	return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn,
	375	offset >> 2);
	376	}
	377
617d2fbc ZSL	378	u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
	379	enum aarch64_insn_register reg,
	380	enum aarch64_insn_variant variant,
	381	enum aarch64_insn_branch_type type)
	382	{
	383	u32 insn;
	384	long offset;
	385
	386	offset = branch_imm_common(pc, addr, SZ_1M);
	387
	388	switch (type) {
	389	case AARCH64_INSN_BRANCH_COMP_ZERO:
	390	insn = aarch64_insn_get_cbz_value();
	391	break;
	392	case AARCH64_INSN_BRANCH_COMP_NONZERO:
	393	insn = aarch64_insn_get_cbnz_value();
	394	break;
	395	default:
	396	BUG_ON(1);
	397	}
	398
	399	switch (variant) {
	400	case AARCH64_INSN_VARIANT_32BIT:
	401	break;
	402	case AARCH64_INSN_VARIANT_64BIT:
	403	insn \|= AARCH64_INSN_SF_BIT;
	404	break;
	405	default:
	406	BUG_ON(1);
	407	}
	408
	409	insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
	410
	411	return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
	412	offset >> 2);
	413	}
	414
345e0d35 ZSL	415	u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
	416	enum aarch64_insn_condition cond)
	417	{
	418	u32 insn;
	419	long offset;
	420
	421	offset = branch_imm_common(pc, addr, SZ_1M);
	422
	423	insn = aarch64_insn_get_bcond_value();
	424
	425	BUG_ON(cond < AARCH64_INSN_COND_EQ \|\| cond > AARCH64_INSN_COND_AL);
	426	insn \|= cond;
	427
	428	return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
	429	offset >> 2);
	430	}
	431
5c5bf25d JL	432	u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_op op)
	433	{
	434	return aarch64_insn_get_hint_value() \| op;
	435	}
	436
	437	u32 __kprobes aarch64_insn_gen_nop(void)
	438	{
	439	return aarch64_insn_gen_hint(AARCH64_INSN_HINT_NOP);
	440	}
c0cafbae ZSL	441
	442	u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
	443	enum aarch64_insn_branch_type type)
	444	{
	445	u32 insn;
	446
	447	switch (type) {
	448	case AARCH64_INSN_BRANCH_NOLINK:
	449	insn = aarch64_insn_get_br_value();
	450	break;
	451	case AARCH64_INSN_BRANCH_LINK:
	452	insn = aarch64_insn_get_blr_value();
	453	break;
	454	case AARCH64_INSN_BRANCH_RETURN:
	455	insn = aarch64_insn_get_ret_value();
	456	break;
	457	default:
	458	BUG_ON(1);
	459	}
	460
	461	return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, reg);
	462	}
17cac179 ZSL	463
	464	u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
	465	enum aarch64_insn_register base,
	466	enum aarch64_insn_register offset,
	467	enum aarch64_insn_size_type size,
	468	enum aarch64_insn_ldst_type type)
	469	{
	470	u32 insn;
	471
	472	switch (type) {
	473	case AARCH64_INSN_LDST_LOAD_REG_OFFSET:
	474	insn = aarch64_insn_get_ldr_reg_value();
	475	break;
	476	case AARCH64_INSN_LDST_STORE_REG_OFFSET:
	477	insn = aarch64_insn_get_str_reg_value();
	478	break;
	479	default:
	480	BUG_ON(1);
	481	}
	482
	483	insn = aarch64_insn_encode_ldst_size(size, insn);
	484
	485	insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
	486
	487	insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
	488	base);
	489
	490	return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
	491	offset);
	492	}