projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| fd9fc9f7 MZ |
1 | /* |
| 2 | * Copyright (C) 2012,2013 - ARM Ltd | |
| 3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify | |
| 6 | * it under the terms of the GNU General Public License version 2 as | |
| 7 | * published by the Free Software Foundation. | |
| 8 | * | |
| 9 | * This program is distributed in the hope that it will be useful, | |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 12 | * GNU General Public License for more details. | |
| 13 | * | |
| 14 | * You should have received a copy of the GNU General Public License | |
| 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
| 16 | */ | |
| 17 | ||
| 18 | #ifndef __ARM_KVM_ASM_H__ | |
| 19 | #define __ARM_KVM_ASM_H__ | |
| 20 | ||
| 21 | /* | |
| 22 | * 0 is reserved as an invalid value. | |
| 23 | * Order *must* be kept in sync with the hyp switch code. | |
| 24 | */ | |
| 25 | #define MPIDR_EL1 1 /* MultiProcessor Affinity Register */ | |
| 26 | #define CSSELR_EL1 2 /* Cache Size Selection Register */ | |
| 27 | #define SCTLR_EL1 3 /* System Control Register */ | |
| 28 | #define ACTLR_EL1 4 /* Auxilliary Control Register */ | |
| 29 | #define CPACR_EL1 5 /* Coprocessor Access Control */ | |
| 30 | #define TTBR0_EL1 6 /* Translation Table Base Register 0 */ | |
| 31 | #define TTBR1_EL1 7 /* Translation Table Base Register 1 */ | |
| 32 | #define TCR_EL1 8 /* Translation Control Register */ | |
| 33 | #define ESR_EL1 9 /* Exception Syndrome Register */ | |
| 34 | #define AFSR0_EL1 10 /* Auxilary Fault Status Register 0 */ | |
| 35 | #define AFSR1_EL1 11 /* Auxilary Fault Status Register 1 */ | |
| 36 | #define FAR_EL1 12 /* Fault Address Register */ | |
| 37 | #define MAIR_EL1 13 /* Memory Attribute Indirection Register */ | |
| 38 | #define VBAR_EL1 14 /* Vector Base Address Register */ | |
| 39 | #define CONTEXTIDR_EL1 15 /* Context ID Register */ | |
| 40 | #define TPIDR_EL0 16 /* Thread ID, User R/W */ | |
| 41 | #define TPIDRRO_EL0 17 /* Thread ID, User R/O */ | |
| 42 | #define TPIDR_EL1 18 /* Thread ID, Privileged */ | |
| 43 | #define AMAIR_EL1 19 /* Aux Memory Attribute Indirection Register */ | |
| 44 | #define CNTKCTL_EL1 20 /* Timer Control Register (EL1) */ | |
| 45 | #define NR_SYS_REGS 21 | |
| 46 | ||
| 47 | #define ARM_EXCEPTION_IRQ 0 | |
| 48 | #define ARM_EXCEPTION_TRAP 1 | |
| 49 | ||
| 50 | #ifndef __ASSEMBLY__ | |
| 51 | struct kvm; | |
| 52 | struct kvm_vcpu; | |
| 53 | ||
| 54 | extern char __kvm_hyp_init[]; | |
| 55 | extern char __kvm_hyp_init_end[]; | |
| 56 | ||
| 57 | extern char __kvm_hyp_vector[]; | |
| 58 | ||
| 59 | extern char __kvm_hyp_code_start[]; | |
| 60 | extern char __kvm_hyp_code_end[]; | |
| 61 | ||
| 62 | extern void __kvm_flush_vm_context(void); | |
| 63 | extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa); | |
| 64 | ||
| 65 | extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu); | |
| 66 | #endif | |
| 67 | ||
| 68 | #endif /* __ARM_KVM_ASM_H__ */ |